From: Heiko Stuebner <heiko@sntech.de>
To: Shunqian Zheng <zhengsq@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dianders@chromium.org
Subject: Re: [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO
Date: Mon, 12 Mar 2018 11:52:54 +0100 [thread overview]
Message-ID: <4610682.YhluMk2iks@phil> (raw)
In-Reply-To: <1520819448-8316-1-git-send-email-zhengsq@rock-chips.com>
Am Montag, 12. März 2018, 02:50:48 CET schrieb Shunqian Zheng:
> The ACLK_VIO is a parent clock used by a several children,
> its suggested clock rate is 400MHz. Right now it gets 400MHz
> because it sources from CPLL(800M) and divides by 2 after reset.
> It's good not to rely on default values like this, so let's
> explicitly set it.
> NOTE: it's expected that at least one board may override cru node and
> set the CPLL to 1.6 GHz. On that board it will be very important to be
> explicit about aclk-vio being 400 MHz.
>
> Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
applied for 4.17
Thanks
Heiko
prev parent reply other threads:[~2018-03-12 10:52 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-12 1:50 [PATCH] arm64: dts: rockchip: assign clock rate for ACLK_VIO Shunqian Zheng
2018-03-12 2:14 ` Doug Anderson
2018-03-12 10:52 ` Heiko Stuebner [this message]
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