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Sat, 08 Mar 2025 22:43:40 -0800 (PST) Received: from jernej-laptop.localnet ([188.159.248.16]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac287653e64sm109036266b.136.2025.03.08.22.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Mar 2025 22:43:39 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 05/14] clk: sunxi-ng: Add support for the A523/T527 CCU PLLs Date: Sun, 09 Mar 2025 07:43:38 +0100 Message-ID: <4633243.LvFx2qVVIh@jernej-laptop> In-Reply-To: <20250307002628.10684-6-andre.przywara@arm.com> References: <20250307002628.10684-1-andre.przywara@arm.com> <20250307002628.10684-6-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne petek, 7. marec 2025 ob 01:26:19 Srednjeevropski standardni =C4=8Das je= Andre Przywara napisal(a): > Add the PLL clocks of the main CCU of the Allwinner A523 and T527 SoCs. > The clocks were modelled after the A523 and T527 manual, and double > checked by writing all 1's into the respective register, to spot all > implemented bits. >=20 > The PLL and mod clocks for the two CPU clusters and the DSU are part of > a separate CCU, also most audio clocks are collected in a DSP CCU, so > both of these clock groups are missing from this driver. >=20 > Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Best regards, Jernej