* [PATCH v4 01/10] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 02/10] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add new struct members and auxiliary_device_id of resets to support
System-Top-Group, Image-Signal-Process and Video-Output on the StarFive
JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
.../reset/starfive/reset-starfive-jh7110.c | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
index c1b3a490d951..4eb2da4a22c4 100644
--- a/drivers/reset/starfive/reset-starfive-jh7110.c
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -29,6 +29,24 @@ static const struct jh7110_reset_info jh7110_aon_info = {
.status_offset = 0x3C,
};
+static const struct jh7110_reset_info jh7110_stg_info = {
+ .nr_resets = JH7110_STGRST_END,
+ .assert_offset = 0x74,
+ .status_offset = 0x78,
+};
+
+static const struct jh7110_reset_info jh7110_isp_info = {
+ .nr_resets = JH7110_ISPRST_END,
+ .assert_offset = 0x38,
+ .status_offset = 0x3C,
+};
+
+static const struct jh7110_reset_info jh7110_vout_info = {
+ .nr_resets = JH7110_VOUTRST_END,
+ .assert_offset = 0x48,
+ .status_offset = 0x4C,
+};
+
static int jh7110_reset_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
@@ -55,6 +73,18 @@ static const struct auxiliary_device_id jh7110_reset_ids[] = {
.name = "clk_starfive_jh7110_sys.rst-aon",
.driver_data = (kernel_ulong_t)&jh7110_aon_info,
},
+ {
+ .name = "clk_starfive_jh7110_sys.rst-stg",
+ .driver_data = (kernel_ulong_t)&jh7110_stg_info,
+ },
+ {
+ .name = "clk_starfive_jh7110_sys.rst-isp",
+ .driver_data = (kernel_ulong_t)&jh7110_isp_info,
+ },
+ {
+ .name = "clk_starfive_jh7110_sys.rst-vout",
+ .driver_data = (kernel_ulong_t)&jh7110_vout_info,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids);
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 02/10] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 01/10] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 03/10] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
` (7 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++
.../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++
3 files changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
new file mode 100644
index 000000000000..b64ccd84200a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 System-Top-Group Clock and Reset Generator
+
+maintainers:
+ - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-stgcrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: HIFI4 core
+ - description: STG AXI/AHB
+ - description: USB (125 MHz)
+ - description: CPU Bus
+ - description: HIFI4 Axi
+ - description: NOC STG Bus
+ - description: APB Bus
+
+ clock-names:
+ items:
+ - const: osc
+ - const: hifi4_core
+ - const: stg_axiahb
+ - const: usb_125m
+ - const: cpu_bus
+ - const: hifi4_axi
+ - const: nocstg_bus
+ - const: apb_bus
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+ stgcrg: clock-controller@10230000 {
+ compatible = "starfive,jh7110-stgcrg";
+ reg = <0x10230000 0x10000>;
+ clocks = <&osc>,
+ <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_USB_125M>,
+ <&syscrg JH7110_SYSCLK_CPU_BUS>,
+ <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
+ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>;
+ clock-names = "osc", "hifi4_core",
+ "stg_axiahb", "usb_125m",
+ "cpu_bus", "hifi4_axi",
+ "nocstg_bus", "apb_bus";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 06257bfd9ac1..6c8e8b4cf1f6 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright 2022 StarFive Technology Co., Ltd.
*/
#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
@@ -218,4 +219,37 @@
#define JH7110_AONCLK_END 14
+/* STGCRG clocks */
+#define JH7110_STGCLK_HIFI4_CLK_CORE 0
+#define JH7110_STGCLK_USB0_APB 1
+#define JH7110_STGCLK_USB0_UTMI_APB 2
+#define JH7110_STGCLK_USB0_AXI 3
+#define JH7110_STGCLK_USB0_LPM 4
+#define JH7110_STGCLK_USB0_STB 5
+#define JH7110_STGCLK_USB0_APP_125 6
+#define JH7110_STGCLK_USB0_REFCLK 7
+#define JH7110_STGCLK_PCIE0_AXI_MST0 8
+#define JH7110_STGCLK_PCIE0_APB 9
+#define JH7110_STGCLK_PCIE0_TL 10
+#define JH7110_STGCLK_PCIE1_AXI_MST0 11
+#define JH7110_STGCLK_PCIE1_APB 12
+#define JH7110_STGCLK_PCIE1_TL 13
+#define JH7110_STGCLK_PCIE_SLV_MAIN 14
+#define JH7110_STGCLK_SEC_AHB 15
+#define JH7110_STGCLK_SEC_MISC_AHB 16
+#define JH7110_STGCLK_GRP0_MAIN 17
+#define JH7110_STGCLK_GRP0_BUS 18
+#define JH7110_STGCLK_GRP0_STG 19
+#define JH7110_STGCLK_GRP1_MAIN 20
+#define JH7110_STGCLK_GRP1_BUS 21
+#define JH7110_STGCLK_GRP1_STG 22
+#define JH7110_STGCLK_GRP1_HIFI 23
+#define JH7110_STGCLK_E2_RTC 24
+#define JH7110_STGCLK_E2_CORE 25
+#define JH7110_STGCLK_E2_DBG 26
+#define JH7110_STGCLK_DMA1P_AXI 27
+#define JH7110_STGCLK_DMA1P_AHB 28
+
+#define JH7110_STGCLK_END 29
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index d78e38690ceb..4e96ab81dd8e 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
@@ -151,4 +152,31 @@
#define JH7110_AONRST_END 8
+/* STGCRG resets */
+#define JH7110_STGRST_SYSCON 0
+#define JH7110_STGRST_HIFI4_CORE 1
+#define JH7110_STGRST_HIFI4_AXI 2
+#define JH7110_STGRST_SEC_AHB 3
+#define JH7110_STGRST_E24_CORE 4
+#define JH7110_STGRST_DMA1P_AXI 5
+#define JH7110_STGRST_DMA1P_AHB 6
+#define JH7110_STGRST_USB0_AXI 7
+#define JH7110_STGRST_USB0_APB 8
+#define JH7110_STGRST_USB0_UTMI_APB 9
+#define JH7110_STGRST_USB0_PWRUP 10
+#define JH7110_STGRST_PCIE0_AXI_MST0 11
+#define JH7110_STGRST_PCIE0_AXI_SLV0 12
+#define JH7110_STGRST_PCIE0_AXI_SLV 13
+#define JH7110_STGRST_PCIE0_BRG 14
+#define JH7110_STGRST_PCIE0_CORE 15
+#define JH7110_STGRST_PCIE0_APB 16
+#define JH7110_STGRST_PCIE1_AXI_MST0 17
+#define JH7110_STGRST_PCIE1_AXI_SLV0 18
+#define JH7110_STGRST_PCIE1_AXI_SLV 19
+#define JH7110_STGRST_PCIE1_BRG 20
+#define JH7110_STGRST_PCIE1_CORE 21
+#define JH7110_STGRST_PCIE1_APB 22
+
+#define JH7110_STGRST_END 23
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 03/10] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 01/10] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 02/10] dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 04/10] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
` (6 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Add driver for the StarFive JH7110 System-Top-Group clock controller.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 11 ++
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-stg.c | 175 ++++++++++++++++++
3 files changed, 187 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-stg.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 71c1148ee5f6..a60abed21650 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -42,3 +42,14 @@ config CLK_STARFIVE_JH7110_AON
help
Say yes here to support the always-on clock controller on the
StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_STG
+ tristate "StarFive JH7110 System-Top-Group clock support"
+ depends on CLK_STARFIVE_JH7110_SYS
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_JH71X0
+ select RESET_STARFIVE_JH7110
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support the System-Top-Group clock controller
+ on the StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index f3df7d957b1e..b81e97ee2659 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
new file mode 100644
index 000000000000..a0cf6450874f
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 System-Top-Group Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110.h"
+
+/* external clocks */
+#define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0)
+#define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1)
+#define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2)
+#define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3)
+#define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4)
+#define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5)
+#define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6)
+#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7)
+#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8)
+
+static const struct jh71x0_clk_data jh7110_stgclk_data[] = {
+ /* hifi4 */
+ JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
+ JH7110_STGCLK_HIFI4_CORE),
+ /* usb */
+ JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
+ JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
+ JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
+ JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
+ /* pci-e */
+ JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
+ JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ /* security */
+ JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+ /* stg mtrx */
+ JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_CPU_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
+ JH7110_STGCLK_NOCSTG_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_CPU_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
+ JH7110_STGCLK_NOCSTG_BUS),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
+ JH7110_STGCLK_HIFI4_AXI),
+ /* e24_rvpi */
+ JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
+ JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
+ /* dw_sgdma1p */
+ JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+};
+
+static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_STGCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_stgcrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ dev_set_drvdata(priv->dev, (void *)(&priv->base));
+
+ for (idx = 0; idx < JH7110_STGCLK_END; idx++) {
+ u32 max = jh7110_stgclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_stgclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_stgclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {
+ "osc",
+ "hifi4_core",
+ "stg_axiahb",
+ "usb_125m",
+ "cpu_bus",
+ "hifi4_axi",
+ "nocstg_bus",
+ "apb_bus"
+ };
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_stgclk_data[idx].parents[i];
+
+ if (pidx < JH7110_STGCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_STGCLK_EXT_END)
+ parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh7110_reset_controller_register(priv, "rst-stg", 2);
+}
+
+static const struct of_device_id jh7110_stgcrg_match[] = {
+ { .compatible = "starfive,jh7110-stgcrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match);
+
+static struct platform_driver jh7110_stgcrg_driver = {
+ .probe = jh7110_stgcrg_probe,
+ .driver = {
+ .name = "clk-starfive-jh7110-stg",
+ .of_match_table = jh7110_stgcrg_match,
+ },
+};
+module_platform_driver(jh7110_stgcrg_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
+MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 04/10] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
` (2 preceding siblings ...)
2023-04-11 13:55 ` [PATCH v4 03/10] clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 05/10] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
` (5 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../clock/starfive,jh7110-ispcrg.yaml | 87 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh7110-crg.h | 18 ++++
.../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++
3 files changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
new file mode 100644
index 000000000000..3b8b85be5cd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
+
+maintainers:
+ - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-ispcrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: ISP Top core
+ - description: ISP Top Axi
+ - description: NOC ISP Bus
+ - description: external DVP
+
+ clock-names:
+ items:
+ - const: isp_top_core
+ - const: isp_top_axi
+ - const: noc_bus_isp_axi
+ - const: dvp_clk
+
+ resets:
+ items:
+ - description: ISP Top core
+ - description: ISP Top Axi
+ - description: NOC ISP Bus
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+ power-domains:
+ maxItems: 1
+ description:
+ ISP domain power
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - '#clock-cells'
+ - '#reset-cells'
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+ #include <dt-bindings/power/starfive,jh7110-pmu.h>
+ #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+ ispcrg: clock-controller@19810000 {
+ compatible = "starfive,jh7110-ispcrg";
+ reg = <0x19810000 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
+ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
+ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
+ <&dvp_clk>;
+ clock-names = "isp_top_core", "isp_top_axi",
+ "noc_bus_isp_axi", "dvp_clk";
+ resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
+ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
+ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ power-domains = <&pwrc JH7110_PD_ISP>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 6c8e8b4cf1f6..39acf30db491 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -252,4 +252,22 @@
#define JH7110_STGCLK_END 29
+/* ISPCRG clocks */
+#define JH7110_ISPCLK_DOM4_APB_FUNC 0
+#define JH7110_ISPCLK_MIPI_RX0_PXL 1
+#define JH7110_ISPCLK_DVP_INV 2
+#define JH7110_ISPCLK_M31DPHY_CFG_IN 3
+#define JH7110_ISPCLK_M31DPHY_REF_IN 4
+#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5
+#define JH7110_ISPCLK_VIN_APB 6
+#define JH7110_ISPCLK_VIN_SYS 7
+#define JH7110_ISPCLK_VIN_PIXEL_IF0 8
+#define JH7110_ISPCLK_VIN_PIXEL_IF1 9
+#define JH7110_ISPCLK_VIN_PIXEL_IF2 10
+#define JH7110_ISPCLK_VIN_PIXEL_IF3 11
+#define JH7110_ISPCLK_VIN_P_AXI_WR 12
+#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13
+
+#define JH7110_ISPCLK_END 14
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index 4e96ab81dd8e..2c5d9dcefffa 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -179,4 +179,20 @@
#define JH7110_STGRST_END 23
+/* ISPCRG resets */
+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
+#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
+#define JH7110_ISPRST_M31DPHY_HW 2
+#define JH7110_ISPRST_M31DPHY_B09_AON 3
+#define JH7110_ISPRST_VIN_APB 4
+#define JH7110_ISPRST_VIN_PIXEL_IF0 5
+#define JH7110_ISPRST_VIN_PIXEL_IF1 6
+#define JH7110_ISPRST_VIN_PIXEL_IF2 7
+#define JH7110_ISPRST_VIN_PIXEL_IF3 8
+#define JH7110_ISPRST_VIN_SYS 9
+#define JH7110_ISPRST_VIN_P_AXI_RD 10
+#define JH7110_ISPRST_VIN_P_AXI_WR 11
+
+#define JH7110_ISPRST_END 12
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 05/10] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
` (3 preceding siblings ...)
2023-04-11 13:55 ` [PATCH v4 04/10] dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 06/10] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
` (4 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add driver for the StarFive JH7110 Image-Signal-Process clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG first before registering.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 11 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-isp.c | 232 ++++++++++++++++++
3 files changed, 244 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-isp.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index a60abed21650..be02eabebeff 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -53,3 +53,14 @@ config CLK_STARFIVE_JH7110_STG
help
Say yes here to support the System-Top-Group clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_ISP
+ tristate "StarFive JH7110 Image-Signal-Process clock support"
+ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_JH71X0
+ select RESET_STARFIVE_JH7110
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support the Image-Signal-Process clock controller
+ on the StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index b81e97ee2659..76fb9f8d628b 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
new file mode 100644
index 000000000000..a676ba3aa108
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Image-Signal-Process Clock Driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110.h"
+
+/* external clocks */
+#define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0)
+#define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1)
+#define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2)
+#define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3)
+#define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4)
+
+/* ISP domian clocks */
+struct isp_top_crg {
+ struct clk_bulk_data *top_clks;
+ int top_clks_num;
+ void __iomem *base;
+};
+
+static struct clk_bulk_data jh7110_isp_top_clks[] = {
+ { .id = "isp_top_core" },
+ { .id = "isp_top_axi" }
+};
+
+static const struct jh71x0_clk_data jh7110_ispclk_data[] = {
+ /* syscon */
+ JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
+ JH7110_ISPCLK_ISP_TOP_AXI),
+ JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
+ /* vin */
+ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
+ JH7110_ISPCLK_DOM4_APB_FUNC),
+ JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
+ JH7110_ISPCLK_MIPI_RX0_PXL,
+ JH7110_ISPCLK_DVP_INV),
+ /* ispv2_top_wrapper */
+ JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
+ JH7110_ISPCLK_MIPI_RX0_PXL,
+ JH7110_ISPCLK_DVP_INV),
+};
+
+static struct isp_top_crg *top_crg_from(void __iomem **base)
+{
+ return container_of(base, struct isp_top_crg, base);
+}
+
+static inline int jh7110_isp_top_crg_init(struct jh71x0_clk_priv *priv, struct isp_top_crg *top)
+{
+ struct reset_control *top_rsts;
+ int ret;
+
+ top->top_clks = jh7110_isp_top_clks;
+ top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks);
+ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
+
+ /* The resets should be shared and other ISP modules will use its. */
+ top_rsts = devm_reset_control_array_get_shared(priv->dev);
+ if (IS_ERR(top_rsts))
+ return dev_err_probe(priv->dev, PTR_ERR(top_rsts),
+ "failed to get top resets\n");
+
+ ret = clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to enable top clocks\n");
+
+ return reset_control_deassert(top_rsts);
+}
+
+static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_ISPCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_ispcrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ struct isp_top_crg *top;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_ISPCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
+ if (!top)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ pm_runtime_enable(priv->dev);
+ ret = pm_runtime_get_sync(priv->dev);
+ if (ret < 0)
+ return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
+
+ ret = jh7110_isp_top_crg_init(priv, top);
+ if (ret)
+ goto err_clk;
+
+ top->base = priv->base;
+ dev_set_drvdata(priv->dev, (void *)(&top->base));
+
+ for (idx = 0; idx < JH7110_ISPCLK_END; idx++) {
+ u32 max = jh7110_ispclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_ispclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_ispclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ unsigned int i;
+ const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = {
+ "isp_top_core",
+ "isp_top_axi",
+ "noc_bus_isp_axi",
+ "dvp_clk"
+ };
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_ispclk_data[idx].parents[i];
+
+ if (pidx < JH7110_ISPCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else
+ parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ goto err_exit;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_ispclk_get, priv);
+ if (ret)
+ goto err_exit;
+
+ ret = jh7110_reset_controller_register(priv, "rst-isp", 3);
+ if (ret)
+ goto err_exit;
+
+ return 0;
+
+err_exit:
+ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
+err_clk:
+ pm_runtime_put_sync(priv->dev);
+ pm_runtime_disable(priv->dev);
+ return ret;
+}
+
+static int jh7110_ispcrg_remove(struct platform_device *pdev)
+{
+ void __iomem **base = dev_get_drvdata(&pdev->dev);
+ struct isp_top_crg *top = top_crg_from(base);
+
+ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_ispcrg_match[] = {
+ { .compatible = "starfive,jh7110-ispcrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match);
+
+static struct platform_driver jh7110_ispcrg_driver = {
+ .probe = jh7110_ispcrg_probe,
+ .remove = jh7110_ispcrg_remove,
+ .driver = {
+ .name = "clk-starfive-jh7110-isp",
+ .of_match_table = jh7110_ispcrg_match,
+ },
+};
+module_platform_driver(jh7110_ispcrg_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 06/10] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
` (4 preceding siblings ...)
2023-04-11 13:55 ` [PATCH v4 05/10] clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
` (3 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../clock/starfive,jh7110-voutcrg.yaml | 90 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh7110-crg.h | 22 +++++
.../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++
3 files changed, 128 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
new file mode 100644
index 000000000000..af77bd8c86b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Video-Output Clock and Reset Generator
+
+maintainers:
+ - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-voutcrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Vout Top core
+ - description: Vout Top Ahb
+ - description: Vout Top Axi
+ - description: Vout Top HDMI MCLK
+ - description: I2STX0 BCLK
+ - description: external HDMI pixel
+
+ clock-names:
+ items:
+ - const: vout_src
+ - const: vout_top_ahb
+ - const: vout_top_axi
+ - const: vout_top_hdmitx0_mclk
+ - const: i2stx0_bclk
+ - const: hdmitx0_pixelclk
+
+ resets:
+ maxItems: 1
+ description: Vout Top core
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+ power-domains:
+ maxItems: 1
+ description:
+ Vout domain power
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - '#clock-cells'
+ - '#reset-cells'
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+ #include <dt-bindings/power/starfive,jh7110-pmu.h>
+ #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+ voutcrg: clock-controller@295C0000 {
+ compatible = "starfive,jh7110-voutcrg";
+ reg = <0x295C0000 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
+ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
+ <&hdmitx0_pixelclk>;
+ clock-names = "vout_src", "vout_top_ahb",
+ "vout_top_axi", "vout_top_hdmitx0_mclk",
+ "i2stx0_bclk", "hdmitx0_pixelclk";
+ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ power-domains = <&pwrc JH7110_PD_VOUT>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 39acf30db491..016227c64a27 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -270,4 +270,26 @@
#define JH7110_ISPCLK_END 14
+/* VOUTCRG clocks */
+#define JH7110_VOUTCLK_APB 0
+#define JH7110_VOUTCLK_DC8200_PIX 1
+#define JH7110_VOUTCLK_DSI_SYS 2
+#define JH7110_VOUTCLK_TX_ESC 3
+#define JH7110_VOUTCLK_DC8200_AXI 4
+#define JH7110_VOUTCLK_DC8200_CORE 5
+#define JH7110_VOUTCLK_DC8200_AHB 6
+#define JH7110_VOUTCLK_DC8200_PIX0 7
+#define JH7110_VOUTCLK_DC8200_PIX1 8
+#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9
+#define JH7110_VOUTCLK_DSITX_APB 10
+#define JH7110_VOUTCLK_DSITX_SYS 11
+#define JH7110_VOUTCLK_DSITX_DPI 12
+#define JH7110_VOUTCLK_DSITX_TXESC 13
+#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14
+#define JH7110_VOUTCLK_HDMI_TX_MCLK 15
+#define JH7110_VOUTCLK_HDMI_TX_BCLK 16
+#define JH7110_VOUTCLK_HDMI_TX_SYS 17
+
+#define JH7110_VOUTCLK_END 18
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index 2c5d9dcefffa..eaf4a0d84f6a 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -195,4 +195,20 @@
#define JH7110_ISPRST_END 12
+/* VOUTCRG resets */
+#define JH7110_VOUTRST_DC8200_AXI 0
+#define JH7110_VOUTRST_DC8200_AHB 1
+#define JH7110_VOUTRST_DC8200_CORE 2
+#define JH7110_VOUTRST_DSITX_DPI 3
+#define JH7110_VOUTRST_DSITX_APB 4
+#define JH7110_VOUTRST_DSITX_RXESC 5
+#define JH7110_VOUTRST_DSITX_SYS 6
+#define JH7110_VOUTRST_DSITX_TXBYTEHS 7
+#define JH7110_VOUTRST_DSITX_TXESC 8
+#define JH7110_VOUTRST_HDMI_TX_HDMI 9
+#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10
+#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11
+
+#define JH7110_VOUTRST_END 12
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
` (5 preceding siblings ...)
2023-04-11 13:55 ` [PATCH v4 06/10] dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 18:33 ` Stephen Boyd
2023-04-11 13:55 ` [PATCH v4 08/10] MAINTAINERS: Update maintainer of JH71x0 clock drivers Xingyu Wu
` (2 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add driver for the StarFive JH7110 Video-Output clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG first before registering.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 11 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-vout.c | 239 ++++++++++++++++++
3 files changed, 251 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index be02eabebeff..b0c7744965d7 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -64,3 +64,14 @@ config CLK_STARFIVE_JH7110_ISP
help
Say yes here to support the Image-Signal-Process clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_VOUT
+ tristate "StarFive JH7110 Video-Output clock support"
+ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_JH71X0
+ select RESET_STARFIVE_JH7110
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support the Video-Output clock controller
+ on the StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 76fb9f8d628b..841377e45bb6 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
new file mode 100644
index 000000000000..4c6f5ae198cf
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Video-Output Clock Driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110.h"
+
+/* external clocks */
+#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
+#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
+#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
+#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
+#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
+#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
+#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
+
+/* VOUT domian clocks */
+struct vout_top_crg {
+ struct clk_bulk_data *top_clks;
+ int top_clks_num;
+ void __iomem *base;
+};
+
+static struct clk_bulk_data jh7110_vout_top_clks[] = {
+ { .id = "vout_src" },
+ { .id = "vout_top_ahb" }
+};
+
+static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
+ /* divider */
+ JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
+ JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
+ JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ /* dc8200 */
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ /* LCD */
+ JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX0,
+ JH7110_VOUTCLK_DC8200_PIX1),
+ /* dsiTx */
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
+ JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
+ /* mipitx DPHY */
+ JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
+ JH7110_VOUTCLK_TX_ESC),
+ /* hdmi */
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
+ JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
+ JH7110_VOUTCLK_I2STX0_BCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
+};
+
+static struct vout_top_crg *top_crg_from(void __iomem **base)
+{
+ return container_of(base, struct vout_top_crg, base);
+}
+
+static int jh7110_vout_top_crg_init(struct jh71x0_clk_priv *priv, struct vout_top_crg *top)
+{
+ struct reset_control *top_rst;
+ int ret;
+
+ top->top_clks = jh7110_vout_top_clks;
+ top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
+ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
+
+ /* The reset should be shared and other Vout modules will use its. */
+ top_rst = devm_reset_control_get_shared(priv->dev, NULL);
+ if (IS_ERR(top_rst))
+ return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
+
+ ret = clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to enable top clocks\n");
+
+ return reset_control_deassert(top_rst);
+}
+
+static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_VOUTCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_voutcrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ struct vout_top_crg *top;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_VOUTCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
+ if (!top)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ pm_runtime_enable(priv->dev);
+ ret = pm_runtime_get_sync(priv->dev);
+ if (ret < 0)
+ return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
+
+ ret = jh7110_vout_top_crg_init(priv, top);
+ if (ret)
+ goto err_clk;
+
+ top->base = priv->base;
+ dev_set_drvdata(priv->dev, (void *)(&top->base));
+
+ for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
+ u32 max = jh7110_voutclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_voutclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_voutclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ unsigned int i;
+ const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
+ "vout_src",
+ "vout_top_ahb",
+ "vout_top_axi",
+ "vout_top_hdmitx0_mclk",
+ "i2stx0_bclk",
+ "hdmitx0_pixelclk"
+ };
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
+
+ if (pidx < JH7110_VOUTCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_VOUTCLK_EXT_END)
+ parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ goto err_exit;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
+ if (ret)
+ goto err_exit;
+
+ ret = jh7110_reset_controller_register(priv, "rst-vout", 4);
+ if (ret)
+ goto err_exit;
+
+ return 0;
+
+err_exit:
+ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
+err_clk:
+ pm_runtime_put_sync(priv->dev);
+ pm_runtime_disable(priv->dev);
+ return ret;
+}
+
+static int jh7110_voutcrg_remove(struct platform_device *pdev)
+{
+ void __iomem **base = dev_get_drvdata(&pdev->dev);
+ struct vout_top_crg *top = top_crg_from(base);
+
+ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_voutcrg_match[] = {
+ { .compatible = "starfive,jh7110-voutcrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
+
+static struct platform_driver jh7110_voutcrg_driver = {
+ .probe = jh7110_voutcrg_probe,
+ .remove = jh7110_voutcrg_remove,
+ .driver = {
+ .name = "clk-starfive-jh7110-vout",
+ .of_match_table = jh7110_voutcrg_match,
+ },
+};
+module_platform_driver(jh7110_voutcrg_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-11 13:55 ` [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
@ 2023-04-11 18:33 ` Stephen Boyd
2023-04-12 6:15 ` Xingyu Wu
0 siblings, 1 reply; 18+ messages in thread
From: Stephen Boyd @ 2023-04-11 18:33 UTC (permalink / raw)
To: Conor Dooley, Emil Renner Berthing, Krzysztof Kozlowski,
Michael Turquette, Philipp Zabel, Xingyu Wu, devicetree,
linux-riscv
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Quoting Xingyu Wu (2023-04-11 06:55:55)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> new file mode 100644
> index 000000000000..4c6f5ae198cf
> --- /dev/null
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> @@ -0,0 +1,239 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive JH7110 Video-Output Clock Driver
> + *
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
Include module.h, device.h, and kernel.h for things like ERR_PTR().
Probably need to include a reset header as well for reset APIs.
> +
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +
> +#include "clk-starfive-jh7110.h"
> +
> +/* external clocks */
> +#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
> +#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
> +#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
> +#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
> +#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
> +#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
> +#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
> +
> +/* VOUT domian clocks */
> +struct vout_top_crg {
> + struct clk_bulk_data *top_clks;
> + int top_clks_num;
size_t?
> + void __iomem *base;
> +};
> +
> +static struct clk_bulk_data jh7110_vout_top_clks[] = {
> + { .id = "vout_src" },
> + { .id = "vout_top_ahb" }
> +};
> +
> +static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
> + /* divider */
> + JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
> + JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
> + JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
> + JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
> + /* dc8200 */
> + JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
> + JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
> + JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
> + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX,
> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX,
> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> + /* LCD */
> + JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX0,
> + JH7110_VOUTCLK_DC8200_PIX1),
> + /* dsiTx */
> + JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
> + JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
> + JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX,
> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> + JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
> + /* mipitx DPHY */
> + JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
> + JH7110_VOUTCLK_TX_ESC),
> + /* hdmi */
> + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
> + JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
> + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
> + JH7110_VOUTCLK_I2STX0_BCLK),
> + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
> +};
> +
> +static struct vout_top_crg *top_crg_from(void __iomem **base)
> +{
> + return container_of(base, struct vout_top_crg, base);
> +}
> +
> +static int jh7110_vout_top_crg_init(struct jh71x0_clk_priv *priv, struct vout_top_crg *top)
> +{
> + struct reset_control *top_rst;
> + int ret;
> +
> + top->top_clks = jh7110_vout_top_clks;
> + top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
> + ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
> + if (ret)
> + return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
> +
> + /* The reset should be shared and other Vout modules will use its. */
> + top_rst = devm_reset_control_get_shared(priv->dev, NULL);
> + if (IS_ERR(top_rst))
> + return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
> +
> + ret = clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
> + if (ret)
> + return dev_err_probe(priv->dev, ret, "failed to enable top clocks\n");
> +
> + return reset_control_deassert(top_rst);
> +}
> +
> +static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct jh71x0_clk_priv *priv = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx < JH7110_VOUTCLK_END)
> + return &priv->reg[idx].hw;
> +
> + return ERR_PTR(-EINVAL);
> +}
> +
> +static int jh7110_voutcrg_probe(struct platform_device *pdev)
> +{
> + struct jh71x0_clk_priv *priv;
> + struct vout_top_crg *top;
> + unsigned int idx;
> + int ret;
> +
> + priv = devm_kzalloc(&pdev->dev,
> + struct_size(priv, reg, JH7110_VOUTCLK_END),
> + GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
> + if (!top)
> + return -ENOMEM;
> +
> + spin_lock_init(&priv->rmw_lock);
> + priv->dev = &pdev->dev;
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + pm_runtime_enable(priv->dev);
Use devm_pm_runtime_enable()?
> + ret = pm_runtime_get_sync(priv->dev);
And use pm_runtime_resume_and_get() here?
> + if (ret < 0)
> + return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
> +
> + ret = jh7110_vout_top_crg_init(priv, top);
> + if (ret)
> + goto err_clk;
> +
> + top->base = priv->base;
> + dev_set_drvdata(priv->dev, (void *)(&top->base));
See comment later about setting this to 'top' instead. Casting away
iomem markings is not good hygiene.
> +
> + for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
> + u32 max = jh7110_voutclk_data[idx].max;
> + struct clk_parent_data parents[4] = {};
> + struct clk_init_data init = {
> + .name = jh7110_voutclk_data[idx].name,
> + .ops = starfive_jh71x0_clk_ops(max),
> + .parent_data = parents,
> + .num_parents =
> + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + .flags = jh7110_voutclk_data[idx].flags,
> + };
> + struct jh71x0_clk *clk = &priv->reg[idx];
> + unsigned int i;
> + const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
> + "vout_src",
> + "vout_top_ahb",
> + "vout_top_axi",
> + "vout_top_hdmitx0_mclk",
> + "i2stx0_bclk",
> + "hdmitx0_pixelclk"
> + };
> +
> + for (i = 0; i < init.num_parents; i++) {
> + unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
> +
> + if (pidx < JH7110_VOUTCLK_END)
> + parents[i].hw = &priv->reg[pidx].hw;
> + else if (pidx < JH7110_VOUTCLK_EXT_END)
> + parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
Can you use .index instead?
> + }
> +
> + clk->hw.init = &init;
> + clk->idx = idx;
> + clk->max_div = max & JH71X0_CLK_DIV_MASK;
> +
> + ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> + if (ret)
> + goto err_exit;
> + }
> +
> + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
> + if (ret)
> + goto err_exit;
> +
> + ret = jh7110_reset_controller_register(priv, "rst-vout", 4);
> + if (ret)
> + goto err_exit;
> +
> + return 0;
> +
> +err_exit:
> + clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
> +err_clk:
> + pm_runtime_put_sync(priv->dev);
> + pm_runtime_disable(priv->dev);
> + return ret;
> +}
> +
> +static int jh7110_voutcrg_remove(struct platform_device *pdev)
> +{
> + void __iomem **base = dev_get_drvdata(&pdev->dev);
Why not set the driver data to be vout_top_crg?
> + struct vout_top_crg *top = top_crg_from(base);
And get rid of this top_crg_from() API?
> +
> + clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
> + pm_runtime_disable(&pdev->dev);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id jh7110_voutcrg_match[] = {
> + { .compatible = "starfive,jh7110-voutcrg" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
> +
> +static struct platform_driver jh7110_voutcrg_driver = {
> + .probe = jh7110_voutcrg_probe,
> + .remove = jh7110_voutcrg_remove,
Use remove_new please.
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-11 18:33 ` Stephen Boyd
@ 2023-04-12 6:15 ` Xingyu Wu
2023-04-13 4:04 ` Stephen Boyd
0 siblings, 1 reply; 18+ messages in thread
From: Xingyu Wu @ 2023-04-12 6:15 UTC (permalink / raw)
To: Stephen Boyd, Conor Dooley, Emil Renner Berthing,
Krzysztof Kozlowski, Michael Turquette, Philipp Zabel, devicetree,
linux-riscv
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
linux-kernel, linux-clk
On 2023/4/12 2:33, Stephen Boyd wrote:
> Quoting Xingyu Wu (2023-04-11 06:55:55)
>> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
>> new file mode 100644
>> index 000000000000..4c6f5ae198cf
>> --- /dev/null
>> +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
>> @@ -0,0 +1,239 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * StarFive JH7110 Video-Output Clock Driver
>> + *
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/io.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/reset.h>
>
> Include module.h, device.h, and kernel.h for things like ERR_PTR().
The local headfile 'clk-starfive-jh71x0.h' from the basic JH71x0 clock driver
already includes the device.h.
And I found the module.h is included in device/driver.h file and then it is included
in the device.h file.
The kernel.h is included in the clk.h file.
So do I still need to list them?
> Probably need to include a reset header as well for reset APIs.
The reset APIs like devm_reset_control_get_shared() and reset_control_deassert()
come from the reset.h file and I have included it.
>
>> +
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +
>> +#include "clk-starfive-jh7110.h"
>> +
>> +/* external clocks */
>> +#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
>> +#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
>> +#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
>> +#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
>> +#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
>> +#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
>> +#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
>> +
>> +/* VOUT domian clocks */
>> +struct vout_top_crg {
>> + struct clk_bulk_data *top_clks;
>> + int top_clks_num;
>
> size_t?
Will modify to 'unsigned int'.
>
>> + void __iomem *base;
>> +};
>> +
>> +static struct clk_bulk_data jh7110_vout_top_clks[] = {
>> + { .id = "vout_src" },
>> + { .id = "vout_top_ahb" }
>> +};
>> +
>> +static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
>> + /* divider */
>> + JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
>> + JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
>> + JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
>> + JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
>> + /* dc8200 */
>> + JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
>> + JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
>> + JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
>> + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
>> + JH7110_VOUTCLK_DC8200_PIX,
>> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
>> + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
>> + JH7110_VOUTCLK_DC8200_PIX,
>> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
>> + /* LCD */
>> + JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
>> + JH7110_VOUTCLK_DC8200_PIX0,
>> + JH7110_VOUTCLK_DC8200_PIX1),
>> + /* dsiTx */
>> + JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
>> + JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
>> + JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
>> + JH7110_VOUTCLK_DC8200_PIX,
>> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
>> + JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
>> + /* mipitx DPHY */
>> + JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
>> + JH7110_VOUTCLK_TX_ESC),
>> + /* hdmi */
>> + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
>> + JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
>> + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
>> + JH7110_VOUTCLK_I2STX0_BCLK),
>> + JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
>> +};
>> +
>> +static struct vout_top_crg *top_crg_from(void __iomem **base)
>> +{
>> + return container_of(base, struct vout_top_crg, base);
>> +}
>> +
>> +static int jh7110_vout_top_crg_init(struct jh71x0_clk_priv *priv, struct vout_top_crg *top)
>> +{
>> + struct reset_control *top_rst;
>> + int ret;
>> +
>> + top->top_clks = jh7110_vout_top_clks;
>> + top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
>> + ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
>> + if (ret)
>> + return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
>> +
>> + /* The reset should be shared and other Vout modules will use its. */
>> + top_rst = devm_reset_control_get_shared(priv->dev, NULL);
>> + if (IS_ERR(top_rst))
>> + return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
>> +
>> + ret = clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
>> + if (ret)
>> + return dev_err_probe(priv->dev, ret, "failed to enable top clocks\n");
>> +
>> + return reset_control_deassert(top_rst);
>> +}
>> +
>> +static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
>> +{
>> + struct jh71x0_clk_priv *priv = data;
>> + unsigned int idx = clkspec->args[0];
>> +
>> + if (idx < JH7110_VOUTCLK_END)
>> + return &priv->reg[idx].hw;
>> +
>> + return ERR_PTR(-EINVAL);
>> +}
>> +
>> +static int jh7110_voutcrg_probe(struct platform_device *pdev)
>> +{
>> + struct jh71x0_clk_priv *priv;
>> + struct vout_top_crg *top;
>> + unsigned int idx;
>> + int ret;
>> +
>> + priv = devm_kzalloc(&pdev->dev,
>> + struct_size(priv, reg, JH7110_VOUTCLK_END),
>> + GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
>> + if (!top)
>> + return -ENOMEM;
>> +
>> + spin_lock_init(&priv->rmw_lock);
>> + priv->dev = &pdev->dev;
>> + priv->base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(priv->base))
>> + return PTR_ERR(priv->base);
>> +
>> + pm_runtime_enable(priv->dev);
>
> Use devm_pm_runtime_enable()?
Will fix.
>
>> + ret = pm_runtime_get_sync(priv->dev);
>
> And use pm_runtime_resume_and_get() here?
Will fix.
>
>> + if (ret < 0)
>> + return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
>> +
>> + ret = jh7110_vout_top_crg_init(priv, top);
>> + if (ret)
>> + goto err_clk;
>> +
>> + top->base = priv->base;
>> + dev_set_drvdata(priv->dev, (void *)(&top->base));
>
> See comment later about setting this to 'top' instead. Casting away
> iomem markings is not good hygiene.
JH7110 resets as the auxiliary device of clocks use the same iomem as the clocks
and the iomem will be got by dev_get_drvdata() in the 7110 reset drivers when registering reset.
So I follow the basic 7110 reset driver and also set the iomem not top_crg struct.
>
>> +
>> + for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
>> + u32 max = jh7110_voutclk_data[idx].max;
>> + struct clk_parent_data parents[4] = {};
>> + struct clk_init_data init = {
>> + .name = jh7110_voutclk_data[idx].name,
>> + .ops = starfive_jh71x0_clk_ops(max),
>> + .parent_data = parents,
>> + .num_parents =
>> + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
>> + .flags = jh7110_voutclk_data[idx].flags,
>> + };
>> + struct jh71x0_clk *clk = &priv->reg[idx];
>> + unsigned int i;
>> + const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
>> + "vout_src",
>> + "vout_top_ahb",
>> + "vout_top_axi",
>> + "vout_top_hdmitx0_mclk",
>> + "i2stx0_bclk",
>> + "hdmitx0_pixelclk"
>> + };
>> +
>> + for (i = 0; i < init.num_parents; i++) {
>> + unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
>> +
>> + if (pidx < JH7110_VOUTCLK_END)
>> + parents[i].hw = &priv->reg[pidx].hw;
>> + else if (pidx < JH7110_VOUTCLK_EXT_END)
>> + parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
>
> Can you use .index instead?
OK, I try to use it instead.
>
>> + }
>> +
>> + clk->hw.init = &init;
>> + clk->idx = idx;
>> + clk->max_div = max & JH71X0_CLK_DIV_MASK;
>> +
>> + ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
>> + if (ret)
>> + goto err_exit;
>> + }
>> +
>> + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
>> + if (ret)
>> + goto err_exit;
>> +
>> + ret = jh7110_reset_controller_register(priv, "rst-vout", 4);
>> + if (ret)
>> + goto err_exit;
>> +
>> + return 0;
>> +
>> +err_exit:
>> + clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
>> +err_clk:
>> + pm_runtime_put_sync(priv->dev);
>> + pm_runtime_disable(priv->dev);
>> + return ret;
>> +}
>> +
>> +static int jh7110_voutcrg_remove(struct platform_device *pdev)
>> +{
>> + void __iomem **base = dev_get_drvdata(&pdev->dev);
>
> Why not set the driver data to be vout_top_crg?
The reason is stated above.
>
>> + struct vout_top_crg *top = top_crg_from(base);
>
> And get rid of this top_crg_from() API?
>
>> +
>> + clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
>> + pm_runtime_disable(&pdev->dev);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id jh7110_voutcrg_match[] = {
>> + { .compatible = "starfive,jh7110-voutcrg" },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
>> +
>> +static struct platform_driver jh7110_voutcrg_driver = {
>> + .probe = jh7110_voutcrg_probe,
>> + .remove = jh7110_voutcrg_remove,
>
> Use remove_new please.
Will fix.
Thanks.
Best regards,
Xingyu Wu
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-12 6:15 ` Xingyu Wu
@ 2023-04-13 4:04 ` Stephen Boyd
2023-04-13 13:31 ` Xingyu Wu
2023-04-13 13:52 ` Conor Dooley
0 siblings, 2 replies; 18+ messages in thread
From: Stephen Boyd @ 2023-04-13 4:04 UTC (permalink / raw)
To: Conor Dooley, Emil Renner Berthing, Krzysztof Kozlowski,
Michael Turquette, Philipp Zabel, Xingyu Wu, devicetree,
linux-riscv
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
linux-kernel, linux-clk
Quoting Xingyu Wu (2023-04-11 23:15:26)
> On 2023/4/12 2:33, Stephen Boyd wrote:
> > Quoting Xingyu Wu (2023-04-11 06:55:55)
> >> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> >> new file mode 100644
> >> index 000000000000..4c6f5ae198cf
> >> --- /dev/null
> >> +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> >> @@ -0,0 +1,239 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * StarFive JH7110 Video-Output Clock Driver
> >> + *
> >> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> >> + */
> >> +
> >> +#include <linux/clk.h>
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/io.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/pm_runtime.h>
> >> +#include <linux/reset.h>
> >
> > Include module.h, device.h, and kernel.h for things like ERR_PTR().
>
> The local headfile 'clk-starfive-jh71x0.h' from the basic JH71x0 clock driver
> already includes the device.h.
> And I found the module.h is included in device/driver.h file and then it is included
> in the device.h file.
> The kernel.h is included in the clk.h file.
> So do I still need to list them?
Yes.
>
> > Probably need to include a reset header as well for reset APIs.
>
> The reset APIs like devm_reset_control_get_shared() and reset_control_deassert()
> come from the reset.h file and I have included it.
Cool, I missed it.
>
> >
> >> +
> >> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> >> +
> >> +#include "clk-starfive-jh7110.h"
> >> +
> >> +/* external clocks */
> >> +#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
> >> +#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
> >> +#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
> >> +#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
> >> +#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
> >> +#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
> >> +#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
> >> +
> >> +/* VOUT domian clocks */
> >> +struct vout_top_crg {
> >> + struct clk_bulk_data *top_clks;
> >> + int top_clks_num;
> >
> > size_t?
>
> Will modify to 'unsigned int'.
Why not size_t?
>
> >
> >> + if (ret < 0)
> >> + return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
> >> +
> >> + ret = jh7110_vout_top_crg_init(priv, top);
> >> + if (ret)
> >> + goto err_clk;
> >> +
> >> + top->base = priv->base;
> >> + dev_set_drvdata(priv->dev, (void *)(&top->base));
> >
> > See comment later about setting this to 'top' instead. Casting away
> > iomem markings is not good hygiene.
>
> JH7110 resets as the auxiliary device of clocks use the same iomem as the clocks
> and the iomem will be got by dev_get_drvdata() in the 7110 reset drivers when registering reset.
> So I follow the basic 7110 reset driver and also set the iomem not top_crg struct.
Oh I totally missed that this is how it's been done for the other
starfive driver. It's still not good hygiene to stash the iomem pointer
that way because the iomem marking is lost and has to be recovered. Can
you make a wrapper struct, either for the adev or to pass in struct
device::platform_data?
---8<---
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 5ec210644e1d..851b93d0f371 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -11,6 +11,9 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <soc/starfive/reset-starfive-jh71x0.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
@@ -335,26 +338,32 @@ static void jh7110_reset_unregister_adev(void *_adev)
struct auxiliary_device *adev = _adev;
auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
}
static void jh7110_reset_adev_release(struct device *dev)
{
struct auxiliary_device *adev = to_auxiliary_dev(dev);
+ struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
- auxiliary_device_uninit(adev);
+ kfree(rdev);
}
int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
const char *adev_name,
u32 adev_id)
{
+ struct jh71x0_reset_adev *rdev;
struct auxiliary_device *adev;
int ret;
- adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
- if (!adev)
+ rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
+ if (!rdev)
return -ENOMEM;
+ rdev->base = priv->base;
+
+ adev = &rdev->adev;
adev->name = adev_name;
adev->dev.parent = priv->dev;
adev->dev.release = jh7110_reset_adev_release;
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
index c1b3a490d951..2d26ae95c8cc 100644
--- a/drivers/reset/starfive/reset-starfive-jh7110.c
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -7,6 +7,8 @@
#include <linux/auxiliary_bus.h>
+#include <soc/starfive/reset-starfive-jh71x0.h>
+
#include "reset-starfive-jh71x0.h"
#include <dt-bindings/reset/starfive,jh7110-crg.h>
@@ -33,14 +35,15 @@ static int jh7110_reset_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
- void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
+ struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
+ void __iomem *base = rdev->base;
if (!info || !base)
return -ENODEV;
return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
- *base + info->assert_offset,
- *base + info->status_offset,
+ base + info->assert_offset,
+ base + info->status_offset,
NULL,
info->nr_resets,
NULL);
diff --git a/include/soc/starfive/reset-starfive-jh71x0.h b/include/soc/starfive/reset-starfive-jh71x0.h
new file mode 100644
index 000000000000..47b486ececc5
--- /dev/null
+++ b/include/soc/starfive/reset-starfive-jh71x0.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_STARFIVE_RESET_JH71X0_H
+#define __SOC_STARFIVE_RESET_JH71X0_H
+
+#include <linux/auxiliary_bus.h>
+#include <linux/compiler_types.h>
+#include <linux/container_of.h>
+
+struct jh71x0_reset_adev {
+ void __iomem *base;
+ struct auxiliary_device adev;
+};
+
+#define to_jh71x0_reset_adev(_adev) \
+ container_of((_adev), struct jh71x0_reset_adev, adev)
+
+#endif
--
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-13 4:04 ` Stephen Boyd
@ 2023-04-13 13:31 ` Xingyu Wu
2023-04-13 18:38 ` Stephen Boyd
2023-04-13 13:52 ` Conor Dooley
1 sibling, 1 reply; 18+ messages in thread
From: Xingyu Wu @ 2023-04-13 13:31 UTC (permalink / raw)
To: Stephen Boyd, Conor Dooley, Emil Renner Berthing,
Krzysztof Kozlowski, Michael Turquette, Philipp Zabel, devicetree,
linux-riscv
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
linux-kernel, linux-clk
On 2023/4/13 12:04, Stephen Boyd wrote:
> Quoting Xingyu Wu (2023-04-11 23:15:26)
>> On 2023/4/12 2:33, Stephen Boyd wrote:
>> > Quoting Xingyu Wu (2023-04-11 06:55:55)
>> >> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
>> >> new file mode 100644
>> >> index 000000000000..4c6f5ae198cf
>> >> --- /dev/null
>> >> +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
>> >> @@ -0,0 +1,239 @@
>> >> +// SPDX-License-Identifier: GPL-2.0
>> >> +/*
>> >> + * StarFive JH7110 Video-Output Clock Driver
>> >> + *
>> >> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> >> + */
>> >> +
>> >> +#include <linux/clk.h>
>> >> +#include <linux/clk-provider.h>
>> >> +#include <linux/io.h>
>> >> +#include <linux/platform_device.h>
>> >> +#include <linux/pm_runtime.h>
>> >> +#include <linux/reset.h>
>> >
>> > Include module.h, device.h, and kernel.h for things like ERR_PTR().
>>
>> The local headfile 'clk-starfive-jh71x0.h' from the basic JH71x0 clock driver
>> already includes the device.h.
>> And I found the module.h is included in device/driver.h file and then it is included
>> in the device.h file.
>> The kernel.h is included in the clk.h file.
>> So do I still need to list them?
>
> Yes.
OK, will fix.
>
>>
>> > Probably need to include a reset header as well for reset APIs.
>>
>> The reset APIs like devm_reset_control_get_shared() and reset_control_deassert()
>> come from the reset.h file and I have included it.
>
> Cool, I missed it.
>
>>
>> >
>> >> +
>> >> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> >> +
>> >> +#include "clk-starfive-jh7110.h"
>> >> +
>> >> +/* external clocks */
>> >> +#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
>> >> +#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
>> >> +#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
>> >> +#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
>> >> +#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
>> >> +#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
>> >> +#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
>> >> +
>> >> +/* VOUT domian clocks */
>> >> +struct vout_top_crg {
>> >> + struct clk_bulk_data *top_clks;
>> >> + int top_clks_num;
>> >
>> > size_t?
>>
>> Will modify to 'unsigned int'.
>
> Why not size_t?
OK,I will use size_t.
>
>>
>> >
>> >> + if (ret < 0)
>> >> + return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
>> >> +
>> >> + ret = jh7110_vout_top_crg_init(priv, top);
>> >> + if (ret)
>> >> + goto err_clk;
>> >> +
>> >> + top->base = priv->base;
>> >> + dev_set_drvdata(priv->dev, (void *)(&top->base));
>> >
>> > See comment later about setting this to 'top' instead. Casting away
>> > iomem markings is not good hygiene.
>>
>> JH7110 resets as the auxiliary device of clocks use the same iomem as the clocks
>> and the iomem will be got by dev_get_drvdata() in the 7110 reset drivers when registering reset.
>> So I follow the basic 7110 reset driver and also set the iomem not top_crg struct.
>
> Oh I totally missed that this is how it's been done for the other
> starfive driver. It's still not good hygiene to stash the iomem pointer
> that way because the iomem marking is lost and has to be recovered. Can
> you make a wrapper struct, either for the adev or to pass in struct
> device::platform_data?
>
> ---8<---
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> index 5ec210644e1d..851b93d0f371 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -11,6 +11,9 @@
> #include <linux/init.h>
> #include <linux/io.h>
> #include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <soc/starfive/reset-starfive-jh71x0.h>
>
> #include <dt-bindings/clock/starfive,jh7110-crg.h>
>
> @@ -335,26 +338,32 @@ static void jh7110_reset_unregister_adev(void *_adev)
> struct auxiliary_device *adev = _adev;
>
> auxiliary_device_delete(adev);
> + auxiliary_device_uninit(adev);
> }
>
> static void jh7110_reset_adev_release(struct device *dev)
> {
> struct auxiliary_device *adev = to_auxiliary_dev(dev);
> + struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
>
> - auxiliary_device_uninit(adev);
> + kfree(rdev);
> }
>
> int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> const char *adev_name,
> u32 adev_id)
> {
> + struct jh71x0_reset_adev *rdev;
> struct auxiliary_device *adev;
> int ret;
>
> - adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
> - if (!adev)
> + rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
Can there use 'devm_kzalloc'? Are you not using this because the struct is public and clock driver
and reset driver both use it. But I think the both clock driver and reset driver are the same
device and can use 'devm_kzalloc'.
> + if (!rdev)
> return -ENOMEM;
>
> + rdev->base = priv->base;
> +
> + adev = &rdev->adev;
> adev->name = adev_name;
> adev->dev.parent = priv->dev;
> adev->dev.release = jh7110_reset_adev_release;
> diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
> index c1b3a490d951..2d26ae95c8cc 100644
> --- a/drivers/reset/starfive/reset-starfive-jh7110.c
> +++ b/drivers/reset/starfive/reset-starfive-jh7110.c
> @@ -7,6 +7,8 @@
>
> #include <linux/auxiliary_bus.h>
>
> +#include <soc/starfive/reset-starfive-jh71x0.h>
> +
> #include "reset-starfive-jh71x0.h"
>
> #include <dt-bindings/reset/starfive,jh7110-crg.h>
> @@ -33,14 +35,15 @@ static int jh7110_reset_probe(struct auxiliary_device *adev,
> const struct auxiliary_device_id *id)
> {
> struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
> - void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
> + struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
> + void __iomem *base = rdev->base;
>
> if (!info || !base)
> return -ENODEV;
>
> return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
> - *base + info->assert_offset,
> - *base + info->status_offset,
> + base + info->assert_offset,
> + base + info->status_offset,
> NULL,
> info->nr_resets,
> NULL);
> diff --git a/include/soc/starfive/reset-starfive-jh71x0.h b/include/soc/starfive/reset-starfive-jh71x0.h
> new file mode 100644
> index 000000000000..47b486ececc5
> --- /dev/null
> +++ b/include/soc/starfive/reset-starfive-jh71x0.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __SOC_STARFIVE_RESET_JH71X0_H
> +#define __SOC_STARFIVE_RESET_JH71X0_H
> +
> +#include <linux/auxiliary_bus.h>
> +#include <linux/compiler_types.h>
> +#include <linux/container_of.h>
> +
> +struct jh71x0_reset_adev {
> + void __iomem *base;
> + struct auxiliary_device adev;
> +};
> +
> +#define to_jh71x0_reset_adev(_adev) \
> + container_of((_adev), struct jh71x0_reset_adev, adev)
> +
> +#endif
That's great. It don't need to set iomem to driver_data and I can set the struct data like 'top_crg'
to driver_data in VOUTCRG and ISPCRG driver. I try to modify it in next patchset.
Thanks for your suggestion.
Best regards,
Xingyu Wu
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-13 13:31 ` Xingyu Wu
@ 2023-04-13 18:38 ` Stephen Boyd
2023-04-14 1:37 ` Xingyu Wu
0 siblings, 1 reply; 18+ messages in thread
From: Stephen Boyd @ 2023-04-13 18:38 UTC (permalink / raw)
To: Conor Dooley, Emil Renner Berthing, Krzysztof Kozlowski,
Michael Turquette, Philipp Zabel, Xingyu Wu, devicetree,
linux-riscv
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
linux-kernel, linux-clk
Quoting Xingyu Wu (2023-04-13 06:31:12)
> On 2023/4/13 12:04, Stephen Boyd wrote:
> > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > index 5ec210644e1d..851b93d0f371 100644
> > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> > @@ -11,6 +11,9 @@
> > #include <linux/init.h>
> > #include <linux/io.h>
> > #include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include <soc/starfive/reset-starfive-jh71x0.h>
> >
> > #include <dt-bindings/clock/starfive,jh7110-crg.h>
> >
> > @@ -335,26 +338,32 @@ static void jh7110_reset_unregister_adev(void *_adev)
> > struct auxiliary_device *adev = _adev;
> >
> > auxiliary_device_delete(adev);
> > + auxiliary_device_uninit(adev);
> > }
> >
> > static void jh7110_reset_adev_release(struct device *dev)
> > {
> > struct auxiliary_device *adev = to_auxiliary_dev(dev);
> > + struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
> >
> > - auxiliary_device_uninit(adev);
> > + kfree(rdev);
> > }
> >
> > int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> > const char *adev_name,
> > u32 adev_id)
> > {
> > + struct jh71x0_reset_adev *rdev;
> > struct auxiliary_device *adev;
> > int ret;
> >
> > - adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
> > - if (!adev)
> > + rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
>
> Can there use 'devm_kzalloc'? Are you not using this because the struct is public and clock driver
> and reset driver both use it. But I think the both clock driver and reset driver are the same
> device and can use 'devm_kzalloc'.
No. The release function for the auxiliary_device is supposed to free
the memory. It shouldn't be tied to the lifetime of anything like the
lifetime of the clk driver being bound.
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-13 18:38 ` Stephen Boyd
@ 2023-04-14 1:37 ` Xingyu Wu
0 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-14 1:37 UTC (permalink / raw)
To: Stephen Boyd, Conor Dooley, Emil Renner Berthing,
Krzysztof Kozlowski, Michael Turquette, Philipp Zabel, devicetree,
linux-riscv
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
linux-kernel, linux-clk
On 2023/4/14 2:38, Stephen Boyd wrote:
> Quoting Xingyu Wu (2023-04-13 06:31:12)
>> On 2023/4/13 12:04, Stephen Boyd wrote:
>> > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
>> > index 5ec210644e1d..851b93d0f371 100644
>> > --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
>> > +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
>> > @@ -11,6 +11,9 @@
>> > #include <linux/init.h>
>> > #include <linux/io.h>
>> > #include <linux/platform_device.h>
>> > +#include <linux/slab.h>
>> > +
>> > +#include <soc/starfive/reset-starfive-jh71x0.h>
>> >
>> > #include <dt-bindings/clock/starfive,jh7110-crg.h>
>> >
>> > @@ -335,26 +338,32 @@ static void jh7110_reset_unregister_adev(void *_adev)
>> > struct auxiliary_device *adev = _adev;
>> >
>> > auxiliary_device_delete(adev);
>> > + auxiliary_device_uninit(adev);
>> > }
>> >
>> > static void jh7110_reset_adev_release(struct device *dev)
>> > {
>> > struct auxiliary_device *adev = to_auxiliary_dev(dev);
>> > + struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
>> >
>> > - auxiliary_device_uninit(adev);
>> > + kfree(rdev);
>> > }
>> >
>> > int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
>> > const char *adev_name,
>> > u32 adev_id)
>> > {
>> > + struct jh71x0_reset_adev *rdev;
>> > struct auxiliary_device *adev;
>> > int ret;
>> >
>> > - adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
>> > - if (!adev)
>> > + rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
>>
>> Can there use 'devm_kzalloc'? Are you not using this because the struct is public and clock driver
>> and reset driver both use it. But I think the both clock driver and reset driver are the same
>> device and can use 'devm_kzalloc'.
>
> No. The release function for the auxiliary_device is supposed to free
> the memory. It shouldn't be tied to the lifetime of anything like the
> lifetime of the clk driver being bound.
Get it. Thanks.
Best regards,
Xingyu Wu
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver
2023-04-13 4:04 ` Stephen Boyd
2023-04-13 13:31 ` Xingyu Wu
@ 2023-04-13 13:52 ` Conor Dooley
1 sibling, 0 replies; 18+ messages in thread
From: Conor Dooley @ 2023-04-13 13:52 UTC (permalink / raw)
To: Stephen Boyd
Cc: Conor Dooley, Emil Renner Berthing, Krzysztof Kozlowski,
Michael Turquette, Philipp Zabel, Xingyu Wu, devicetree,
linux-riscv, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Hal Feng, linux-kernel, linux-clk
[-- Attachment #1: Type: text/plain, Size: 1599 bytes --]
On Wed, Apr 12, 2023 at 09:04:08PM -0700, Stephen Boyd wrote:
> Quoting Xingyu Wu (2023-04-11 23:15:26)
> > On 2023/4/12 2:33, Stephen Boyd wrote:
> > > Quoting Xingyu Wu (2023-04-11 06:55:55)
> > >> + if (ret < 0)
> > >> + return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
> > >> +
> > >> + ret = jh7110_vout_top_crg_init(priv, top);
> > >> + if (ret)
> > >> + goto err_clk;
> > >> +
> > >> + top->base = priv->base;
> > >> + dev_set_drvdata(priv->dev, (void *)(&top->base));
> > >
> > > See comment later about setting this to 'top' instead. Casting away
> > > iomem markings is not good hygiene.
> >
> > JH7110 resets as the auxiliary device of clocks use the same iomem as the clocks
> > and the iomem will be got by dev_get_drvdata() in the 7110 reset drivers when registering reset.
> > So I follow the basic 7110 reset driver and also set the iomem not top_crg struct.
>
> Oh I totally missed that this is how it's been done for the other
> starfive driver. It's still not good hygiene to stash the iomem pointer
> that way because the iomem marking is lost and has to be recovered. Can
> you make a wrapper struct, either for the adev or to pass in struct
> device::platform_data?
FWIW, this did come up on an earlier version of the other starfive
driver:
https://lore.kernel.org/linux-clk/e0d8f9ba-5bf4-d7dd-5110-20d4196556f9@starfivetech.com/
I probably should've pushed Hal to use a struct, but evidently I didn't
reply to his final message there, so apologies for that!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 08/10] MAINTAINERS: Update maintainer of JH71x0 clock drivers
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
` (6 preceding siblings ...)
2023-04-11 13:55 ` [PATCH v4 07/10] clk: starfive: Add StarFive JH7110 Video-Output clock driver Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 09/10] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 10/10] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add a new maintainer which is in charge of StarFive JH7110
STG/ISP/VOUT clock drivers.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4c0b39c44957..5f9c544bc189 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19914,6 +19914,7 @@ F: drivers/mmc/host/dw_mmc-starfive.c
STARFIVE JH71X0 CLOCK DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
M: Hal Feng <hal.feng@starfivetech.com>
+M: Xingyu Wu <xingyu.wu@starfivetech.com>
S: Maintained
F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
F: drivers/clk/starfive/clk-starfive-jh71*
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 09/10] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
` (7 preceding siblings ...)
2023-04-11 13:55 ` [PATCH v4 08/10] MAINTAINERS: Update maintainer of JH71x0 clock drivers Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
2023-04-11 13:55 ` [PATCH v4 10/10] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes Xingyu Wu
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
.../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 2a6d81609284..1155b97b593d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -38,6 +38,10 @@ gpio-restart {
};
};
+&dvp_clk {
+ clock-frequency = <74250000>;
+};
+
&gmac0_rgmii_rxin {
clock-frequency = <125000000>;
};
@@ -54,6 +58,10 @@ &gmac1_rmii_refin {
clock-frequency = <50000000>;
};
+&hdmitx0_pixelclk {
+ clock-frequency = <297000000>;
+};
+
&i2srx_bclk_ext {
clock-frequency = <12288000>;
};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 30e1f34d5cf8..336ee2b0ffb5 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -164,6 +164,12 @@ core4 {
};
};
+ dvp_clk: dvp-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "dvp_clk";
+ #clock-cells = <0>;
+ };
+
gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
compatible = "fixed-clock";
clock-output-names = "gmac0_rgmii_rxin";
@@ -188,6 +194,12 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock {
#clock-cells = <0>;
};
+ hdmitx0_pixelclk: hdmitx0-pixel-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "hdmitx0_pixelclk";
+ #clock-cells = <0>;
+ };
+
i2srx_bclk_ext: i2srx-bclk-ext-clock {
compatible = "fixed-clock";
clock-output-names = "i2srx_bclk_ext";
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH v4 10/10] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes
2023-04-11 13:55 [PATCH v4 00/10] Add new partial clock and reset drivers for StarFive JH7110 Xingyu Wu
` (8 preceding siblings ...)
2023-04-11 13:55 ` [PATCH v4 09/10] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks Xingyu Wu
@ 2023-04-11 13:55 ` Xingyu Wu
9 siblings, 0 replies; 18+ messages in thread
From: Xingyu Wu @ 2023-04-11 13:55 UTC (permalink / raw)
To: linux-riscv, devicetree, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Philipp Zabel, Conor Dooley,
Emil Renner Berthing
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou, Hal Feng,
Xingyu Wu, linux-kernel, linux-clk
Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110
System-Top-Group, Image-Signal-Process and Video-Output
clock and reset drivers for the JH7110 RISC-V SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 55 ++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 336ee2b0ffb5..9acb5fb1716d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/power/starfive,jh7110-pmu.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>
/ {
@@ -365,6 +366,25 @@ i2c2: i2c@10050000 {
status = "disabled";
};
+ stgcrg: clock-controller@10230000 {
+ compatible = "starfive,jh7110-stgcrg";
+ reg = <0x0 0x10230000 0x0 0x10000>;
+ clocks = <&osc>,
+ <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_USB_125M>,
+ <&syscrg JH7110_SYSCLK_CPU_BUS>,
+ <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
+ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>;
+ clock-names = "osc", "hifi4_core",
+ "stg_axiahb", "usb_125m",
+ "cpu_bus", "hifi4_axi",
+ "nocstg_bus", "apb_bus";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -515,5 +535,40 @@ pwrc: power-controller@17030000 {
interrupts = <111>;
#power-domain-cells = <1>;
};
+
+ ispcrg: clock-controller@19810000 {
+ compatible = "starfive,jh7110-ispcrg";
+ reg = <0x0 0x19810000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
+ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
+ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
+ <&dvp_clk>;
+ clock-names = "isp_top_core", "isp_top_axi",
+ "noc_bus_isp_axi", "dvp_clk";
+ resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
+ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
+ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ power-domains = <&pwrc JH7110_PD_ISP>;
+ };
+
+ voutcrg: clock-controller@295c0000 {
+ compatible = "starfive,jh7110-voutcrg";
+ reg = <0x0 0x295c0000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
+ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
+ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
+ <&hdmitx0_pixelclk>;
+ clock-names = "vout_src", "vout_top_ahb",
+ "vout_top_axi", "vout_top_hdmitx0_mclk",
+ "i2stx0_bclk", "hdmitx0_pixelclk";
+ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ power-domains = <&pwrc JH7110_PD_VOUT>;
+ };
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread