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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f7011fc469sm7545748a12.7.2025.04.29.08.24.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 08:24:20 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Andrew Lunn Cc: Andre Przywara , robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, wens@csie.org, samuel@sholland.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] arm64: dts: allwinner: h6: Add OrangePi 3 LTS DTS Date: Tue, 29 Apr 2025 17:24:18 +0200 Message-ID: <4645060.LvFx2qVVIh@jernej-laptop> In-Reply-To: <6a056bf8-9f39-4204-9378-8cc39be60038@lunn.ch> References: <20250413134318.66681-1-jernej.skrabec@gmail.com> <5880182.DvuYhMxLoT@jernej-laptop> <6a056bf8-9f39-4204-9378-8cc39be60038@lunn.ch> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne torek, 29. april 2025 ob 17:09:22 Srednjeevropski poletni =C4=8Das je A= ndrew Lunn napisal(a): > On Tue, Apr 29, 2025 at 04:51:59PM +0200, Jernej =C5=A0krabec wrote: > > Dne ponedeljek, 28. april 2025 ob 14:37:48 Srednjeevropski poletni =C4= =8Das je Andrew Lunn napisal(a): > > > On Sat, Apr 26, 2025 at 08:00:49PM +0200, Jernej =C5=A0krabec wrote: > > > > Dne petek, 25. april 2025 ob 17:34:14 Srednjeevropski poletni =C4= =8Das je Andrew Lunn napisal(a): > > > > > > > +&emac { > > > > > > > + pinctrl-names =3D "default"; > > > > > > > + pinctrl-0 =3D <&ext_rgmii_pins>; > > > > > > > + phy-mode =3D "rgmii-rxid"; > > > > > >=20 > > > > > > So relating to what Andrew said earlier today, should this read= rgmii-id > > > > > > instead? Since the strap resistors just set some boot-up value,= but we > > > > > > want the PHY driver to enable both RX and TX delay programmatic= ally? > > > > >=20 > > > > > Yes. > > > > >=20 > > > > > There is a checkpatch.pl patch working its way through the system > > > > > which will add warning about any rgmii value other than rgmii-id.= Such > > > > > values need a comment that the PCB has extra long clock > > > > > lines. Hopefully that will make people actually stop and think ab= out > > > > > this, rather than just copy broken vendor code. > > > >=20 > > > > I spent quite some time working on ethernet support for this board.= Once > > > > I've found PHY datasheet, I confirmed that there is added delay. So= this > > > > particular board needs "rgmii-rxid" mode. > > >=20 > > > There have been numerous discussions about what these rgmii modes > > > mean, because DT developers frequently get them wrong. > > >=20 > > > Does the PCB have an extra long clock line in the TX direction? That > > > is what rgmii-rxid means, the PCB is providing the TX delay, the > > > MAC/PHY pair needs to add the RX delay. > >=20 > > While schematic is accessible, AFAIK PCB/gerbers are not, so I can't re= ally > > tell how long it is. But without this extra delay, ethernet doesn't wor= k. >=20 > You are not adding an extra delay, you are subtracting a > delay. 'rgmii-rxid' says the TX delay is implemented by the PCB, hence > the PHY does not need to add the delay. >=20 > What is normal is that the PCB adds no delays, and the PHY adds the > delay for both the RX and the TX. And you represent this with > 'rgmii-id'. ok, thanks for explanation. >=20 > So what you need to find out is, where does the TX delay come from? How to do that? Strapping show me this way and testing confirmed it. Not sure what more I can do? As a hobbyist, I don't have access to anything more than schematic. Best regards, Jernej