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Am Dienstag, 1. Juli 2025, 09:04:40 CEST schrieb Peng Fan: > i.MX94 BLK CTL LVDS CSR's LVDS_PHY_CLOCK_CONTRL register controls the clo= ck > gating logic of LVDS units. Display CSR's DISPLAY_ENGINES_CLOCK_CONTROL > register controls the selection of the clock feeding the display engine. >=20 > Add clock gate support for the two CSRs. >=20 > Signed-off-by: Peng Fan > --- > drivers/clk/imx/clk-imx95-blk-ctl.c | 50 +++++++++++++++++++++++++++++++= +++++- > 1 file changed, 49 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-im= x95-blk-ctl.c > index 828ee0a81ff62c6e4f61eef350b9073f19f5351f..5fe582b0d4a9a197f2c1a49dc= 18f15ca83ccb4a4 100644 > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c > @@ -1,8 +1,9 @@ > // SPDX-License-Identifier: GPL-2.0 > /* > - * Copyright 2024 NXP > + * Copyright 2024-2025 NXP > */ > =20 > +#include > #include > #include > #include > @@ -300,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_= ctl_dev_data =3D { > .clk_reg_offset =3D 0, > }; > =20 > +static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[]= =3D { > + [IMX94_CLK_DISPMIX_LVDS_CLK_GATE] =3D { > + .name =3D "lvds_clk_gate", > + .parent_names =3D (const char *[]){ "ldbpll", }, > + .num_parents =3D 1, > + .reg =3D 0, > + .bit_idx =3D 1, > + .bit_width =3D 1, > + .type =3D CLK_GATE, > + .flags =3D CLK_SET_RATE_PARENT, > + .flags2 =3D CLK_GATE_SET_TO_DISABLE, > + }, > +}; > + > +static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data =3D { > + .num_clks =3D ARRAY_SIZE(imx94_lvds_clk_dev_data), > + .clk_dev_data =3D imx94_lvds_clk_dev_data, > + .clk_reg_offset =3D 0, > + .rpm_enabled =3D true, > +}; > + > +static const char * const imx94_disp_engine_parents[] =3D { > + "disppix", "ldb_pll_div7" > +}; > + > +static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev= _data[] =3D { > + [IMX94_CLK_DISPMIX_CLK_SEL] =3D { > + .name =3D "disp_clk_sel", > + .parent_names =3D imx94_disp_engine_parents, > + .num_parents =3D ARRAY_SIZE(imx94_disp_engine_parents), > + .reg =3D 0, > + .bit_idx =3D 1, > + .bit_width =3D 1, > + .type =3D CLK_MUX, > + .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, > + }, > +}; > + > +static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = =3D { > + .num_clks =3D ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data), > + .clk_dev_data =3D imx94_dispmix_csr_clk_dev_data, > + .clk_reg_offset =3D 0, > + .rpm_enabled =3D true, > +}; > + > static int imx95_bc_probe(struct platform_device *pdev) > { > struct device *dev =3D &pdev->dev; > @@ -474,6 +520,8 @@ static const struct of_device_id imx95_bc_of_match[] = =3D { > { .compatible =3D "nxp,imx95-hsio-blk-ctl", .data =3D &hsio_blk_ctl_dev= _data }, > { .compatible =3D "nxp,imx95-vpu-csr", .data =3D &vpublk_dev_data }, > { .compatible =3D "nxp,imx95-netcmix-blk-ctrl", .data =3D &netcmix_dev_= data}, > + { .compatible =3D "nxp,imx94-lvds-csr", .data =3D &imx94_lvds_csr_dev_d= ata }, > + { .compatible =3D "nxp,imx94-display-csr", .data =3D &imx94_dispmix_csr= _dev_data }, Similar to patch 1, sort them properly. Best regards, Alexander > { /* Sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, imx95_bc_of_match); >=20 >=20 =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/