[PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes

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* [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes
@ 2022-07-15  7:02 Johan Hovold
  2022-07-15  7:02 ` [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: fix USB clock order and naming Johan Hovold
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Johan Hovold @ 2022-07-15  7:02 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Greg Kroah-Hartman, Andrew Halaney, Manivannan Sadhasivam,
	linux-arm-msm, devicetree, linux-kernel, Johan Hovold

This is the second half of the series which adds the missing binding for
SC8280XP and cleans up the current bindings somewhat:

	https://lore.kernel.org/all/20220713131340.29401-1-johan+linaro@kernel.org/

The binding updates have now been merged by Greg so that the qcom dts
fixes that depend on them can also be applied.

Johan


Changes in v2:
 - fix the pwr_event interrupt number for usb_1 (Andrew)
 - amend commit summary of first patch to mention also clock "naming"
   (Krzysztof)
 - add ack and review tags from Andrew and Krzysztof


Johan Hovold (4):
  arm64: dts: qcom: sc8280xp: fix USB clock order and naming
  arm64: dts: qcom: sc8280xp: fix USB interrupts
  arm64: dts: qcom: sc7280: reorder USB interrupts
  arm64: dts: qcom: reorder USB interrupts

 arch/arm/boot/dts/qcom-sdx65.dtsi      | 10 +++++----
 arch/arm64/boot/dts/qcom/sc7280.dtsi   | 15 +++++++------
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 30 +++++++++++++++-----------
 arch/arm64/boot/dts/qcom/sm8250.dtsi   | 20 ++++++++++-------
 arch/arm64/boot/dts/qcom/sm8350.dtsi   | 20 ++++++++++-------
 5 files changed, 55 insertions(+), 40 deletions(-)

-- 
2.35.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: fix USB clock order and naming
  2022-07-15  7:02 [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Johan Hovold
@ 2022-07-15  7:02 ` Johan Hovold
  2022-07-15  9:25   ` Krzysztof Kozlowski
  2022-07-15  7:02 ` [PATCH v2 2/4] arm64: dts: qcom: sc8280xp: fix USB interrupts Johan Hovold
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 7+ messages in thread
From: Johan Hovold @ 2022-07-15  7:02 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Greg Kroah-Hartman, Andrew Halaney, Manivannan Sadhasivam,
	linux-arm-msm, devicetree, linux-kernel, Johan Hovold

Fix the USB controller clock order and naming so that they match the
devicetree binding.

Note that the driver currently simply enables all clocks in the order
that they are specified in the devicetree. Reordering the clocks as per
the binding means that the only explicit ordering constraint found in
the vendor driver, that cfg_noc should be enabled before the core_clk,
is now honoured.

Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 285a9828c250..45cc7d714fd2 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1855,16 +1855,16 @@ usb_0: usb@a6f8800 {
 			#size-cells = <2>;
 			ranges;
 
-			clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
-				 <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
 				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
-				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
 				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
-			clock-names = "core", "iface", "bus_aggr", "utmi", "sleep",
+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
 				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
 
 			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
@@ -1905,16 +1905,16 @@ usb_1: usb@a8f8800 {
 			#size-cells = <2>;
 			ranges;
 
-			clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
-				 <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
 				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
-				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
 				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
 				 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
 				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
-			clock-names = "core", "iface", "bus_aggr", "utmi", "sleep",
+			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
 				      "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
 
 			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: fix USB clock order and naming
  2022-07-15  7:02 ` [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: fix USB clock order and naming Johan Hovold
@ 2022-07-15  9:25   ` Krzysztof Kozlowski
  0 siblings, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-15  9:25 UTC (permalink / raw)
  To: Johan Hovold, Bjorn Andersson
  Cc: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Greg Kroah-Hartman, Andrew Halaney, Manivannan Sadhasivam,
	linux-arm-msm, devicetree, linux-kernel

On 15/07/2022 09:02, Johan Hovold wrote:
> Fix the USB controller clock order and naming so that they match the
> devicetree binding.
> 
> Note that the driver currently simply enables all clocks in the order
> that they are specified in the devicetree. Reordering the clocks as per
> the binding means that the only explicit ordering constraint found in
> the vendor driver, that cfg_noc should be enabled before the core_clk,
> is now honoured.


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH v2 2/4] arm64: dts: qcom: sc8280xp: fix USB interrupts
  2022-07-15  7:02 [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Johan Hovold
  2022-07-15  7:02 ` [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: fix USB clock order and naming Johan Hovold
@ 2022-07-15  7:02 ` Johan Hovold
  2022-07-15  7:02 ` [PATCH v2 3/4] arm64: dts: qcom: sc7280: reorder " Johan Hovold
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Johan Hovold @ 2022-07-15  7:02 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Greg Kroah-Hartman, Andrew Halaney, Manivannan Sadhasivam,
	linux-arm-msm, devicetree, linux-kernel, Johan Hovold,
	Krzysztof Kozlowski

The two single-port SC8280XP USB controllers do not have an hs_phy_irq
interrupt. Instead they have a pwr_event interrupt which is distinct
from the former and not yet supported by the driver.

Fix the USB node interrupt names so that they match the devicetree
binding.

Also fix the pwr_event interrupt of the second controller which should
be 811 as noticed by Andrew Halaney.

Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 45cc7d714fd2..f002a63d8507 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1875,8 +1875,10 @@ usb_0: usb@a6f8800 {
 					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-					  "dm_hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
 
 			power-domains = <&gcc USB30_PRIM_GDSC>;
 
@@ -1921,12 +1923,14 @@ usb_1: usb@a8f8800 {
 					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
 			assigned-clock-rates = <19200000>, <200000000>;
 
-			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-					  "dm_hs_phy_irq", "ss_phy_irq";
+			interrupt-names = "pwr_event",
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq",
+					  "ss_phy_irq";
 
 			power-domains = <&gcc USB30_SEC_GDSC>;
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH v2 3/4] arm64: dts: qcom: sc7280: reorder USB interrupts
  2022-07-15  7:02 [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Johan Hovold
  2022-07-15  7:02 ` [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: fix USB clock order and naming Johan Hovold
  2022-07-15  7:02 ` [PATCH v2 2/4] arm64: dts: qcom: sc8280xp: fix USB interrupts Johan Hovold
@ 2022-07-15  7:02 ` Johan Hovold
  2022-07-15  7:02 ` [PATCH v2 4/4] arm64: dts: qcom: " Johan Hovold
  2022-07-17  3:08 ` (subset) [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Bjorn Andersson
  4 siblings, 0 replies; 7+ messages in thread
From: Johan Hovold @ 2022-07-15  7:02 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Greg Kroah-Hartman, Andrew Halaney, Manivannan Sadhasivam,
	linux-arm-msm, devicetree, linux-kernel, Johan Hovold,
	Krzysztof Kozlowski

Only one of the USB controllers supports SuperSpeed and have an SS PHY
wakeup interrupt.

Reorder the interrupts so that they match the updated binding which
specifically has the optional interrupt last.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ef431c954ab5..1e739ba1923d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3174,10 +3174,11 @@ usb_2: usb@8cf8800 {
 			assigned-clock-rates = <19200000>, <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pdc 13 IRQ_TYPE_EDGE_RISING>,
-				     <&pdc 12 IRQ_TYPE_EDGE_RISING>;
+					      <&pdc 12 IRQ_TYPE_EDGE_RISING>,
+					      <&pdc 13 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "hs_phy_irq",
-					  "dm_hs_phy_irq", "dp_hs_phy_irq";
+					  "dp_hs_phy_irq",
+					  "dm_hs_phy_irq";
 
 			power-domains = <&gcc GCC_USB30_SEC_GDSC>;
 
@@ -3357,13 +3358,13 @@ usb_1: usb@a6f8800 {
 			assigned-clock-rates = <19200000>, <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-					      <&pdc 17 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
-					      <&pdc 14 IRQ_TYPE_LEVEL_HIGH>;
+					      <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
 			interrupt-names = "hs_phy_irq",
-					  "ss_phy_irq",
+					  "dp_hs_phy_irq",
 					  "dm_hs_phy_irq",
-					  "dp_hs_phy_irq";
+					  "ss_phy_irq";
 
 			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH v2 4/4] arm64: dts: qcom: reorder USB interrupts
  2022-07-15  7:02 [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Johan Hovold
                   ` (2 preceding siblings ...)
  2022-07-15  7:02 ` [PATCH v2 3/4] arm64: dts: qcom: sc7280: reorder " Johan Hovold
@ 2022-07-15  7:02 ` Johan Hovold
  2022-07-17  3:08 ` (subset) [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Bjorn Andersson
  4 siblings, 0 replies; 7+ messages in thread
From: Johan Hovold @ 2022-07-15  7:02 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Greg Kroah-Hartman, Andrew Halaney, Manivannan Sadhasivam,
	linux-arm-msm, devicetree, linux-kernel, Johan Hovold,
	Krzysztof Kozlowski

Three SoCs did not follow the interrupt order specified by the USB
controller binding.

While keeping the non-SuperSpeed interrupts together seems natural,
reorder the interrupts to match the binding.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi    | 10 ++++++----
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++--------
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++--------
 3 files changed, 30 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 7a193678b4f5..8daefd50217a 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -372,11 +372,13 @@ usb: usb@a6f8800 {
 			assigned-clock-rates = <19200000>, <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-					      <&pdc 19 IRQ_TYPE_EDGE_BOTH>,
 					      <&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
-					      <&pdc 18 IRQ_TYPE_EDGE_BOTH>;
-			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-					  "ss_phy_irq", "dm_hs_phy_irq";
+					      <&pdc 18 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 19 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "hs_phy_irq",
+					  "ss_phy_irq",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
 
 			power-domains = <&gcc USB30_GDSC>;
 
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 7ac8aa110f81..65be7f3ec74c 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3026,11 +3026,13 @@ usb_1: usb@a6f8800 {
 			assigned-clock-rates = <19200000>, <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
-					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-					  "dm_hs_phy_irq", "ss_phy_irq";
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "hs_phy_irq",
+					  "ss_phy_irq",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
 
 			power-domains = <&gcc USB30_PRIM_GDSC>;
 
@@ -3081,11 +3083,13 @@ usb_2: usb@a8f8800 {
 			assigned-clock-rates = <19200000>, <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
-					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-					  "dm_hs_phy_irq", "ss_phy_irq";
+					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "hs_phy_irq",
+					  "ss_phy_irq",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
 
 			power-domains = <&gcc USB30_SEC_GDSC>;
 
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 65c7fe54613d..e72a04411888 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2461,11 +2461,13 @@ usb_1: usb@a6f8800 {
 			assigned-clock-rates = <19200000>, <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
-					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
-					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-					  "dm_hs_phy_irq", "ss_phy_irq";
+					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "hs_phy_irq",
+					  "ss_phy_irq",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
 
 			power-domains = <&gcc USB30_PRIM_GDSC>;
 
@@ -2509,11 +2511,13 @@ usb_2: usb@a8f8800 {
 			assigned-clock-rates = <19200000>, <200000000>;
 
 			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
-					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
 					      <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
-					      <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
-					  "dm_hs_phy_irq", "ss_phy_irq";
+					      <&pdc 12 IRQ_TYPE_EDGE_BOTH>;
+			interrupt-names = "hs_phy_irq",
+					  "ss_phy_irq",
+					  "dm_hs_phy_irq",
+					  "dp_hs_phy_irq";
 
 			power-domains = <&gcc USB30_SEC_GDSC>;
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: (subset) [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes
  2022-07-15  7:02 [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Johan Hovold
                   ` (3 preceding siblings ...)
  2022-07-15  7:02 ` [PATCH v2 4/4] arm64: dts: qcom: " Johan Hovold
@ 2022-07-17  3:08 ` Bjorn Andersson
  4 siblings, 0 replies; 7+ messages in thread
From: Bjorn Andersson @ 2022-07-17  3:08 UTC (permalink / raw)
  To: Johan Hovold
  Cc: Krzysztof Kozlowski, linux-arm-msm, Konrad Dybcio,
	Manivannan Sadhasivam, Andrew Halaney, Andy Gross, linux-kernel,
	Greg Kroah-Hartman, Rob Herring, devicetree

On Fri, 15 Jul 2022 09:02:44 +0200, Johan Hovold wrote:
> This is the second half of the series which adds the missing binding for
> SC8280XP and cleans up the current bindings somewhat:
> 
> 	https://lore.kernel.org/all/20220713131340.29401-1-johan+linaro@kernel.org/
> 
> The binding updates have now been merged by Greg so that the qcom dts
> fixes that depend on them can also be applied.
> 
> [...]

Applied, thanks!

[4/4] arm64: dts: qcom: reorder USB interrupts
      commit: 079926b5a22ac92c4ac1e15e6cfb20a431802cb5

Best regards,
-- 
Bjorn Andersson <bjorn.andersson@linaro.org>

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2022-07-17  3:08 UTC | newest]

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2022-07-15  7:02 [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Johan Hovold
2022-07-15  7:02 ` [PATCH v2 1/4] arm64: dts: qcom: sc8280xp: fix USB clock order and naming Johan Hovold
2022-07-15  9:25   ` Krzysztof Kozlowski
2022-07-15  7:02 ` [PATCH v2 2/4] arm64: dts: qcom: sc8280xp: fix USB interrupts Johan Hovold
2022-07-15  7:02 ` [PATCH v2 3/4] arm64: dts: qcom: sc7280: reorder " Johan Hovold
2022-07-15  7:02 ` [PATCH v2 4/4] arm64: dts: qcom: " Johan Hovold
2022-07-17  3:08 ` (subset) [PATCH v2 0/4] arm64: dts: qcom: USB clock and interrupt fixes Bjorn Andersson

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