From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
To: Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Jagadeesh Kona <quic_jkona@quicinc.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Ajit Pandey <quic_ajipan@quicinc.com>,
Imran Shaik <quic_imrashai@quicinc.com>,
Taniya Das <quic_tdas@quicinc.com>,
Satya Priya Kakitapalli <quic_skakitap@quicinc.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Subject: Re: [PATCH v2 0/8] clk: qcom: Add support to attach multiple power domains in cc probe
Date: Tue, 11 Mar 2025 12:12:16 +0200 [thread overview]
Message-ID: <46d4f090-3e31-414f-abfc-3d1018913c56@linaro.org> (raw)
In-Reply-To: <5a45fd25-74ed-46e3-b0e3-5adf92b5e9f7@linaro.org>
On 3/11/25 11:52, Bryan O'Donoghue wrote:
> On 06/03/2025 08:55, Jagadeesh Kona wrote:
>> In some of the recent chipsets, PLLs require more than one power domain
>> to be kept ON to configure the PLL. But the current code doesn't enable
>> all the required power domains while configuring the PLLs, this leads
>> to functional issues due to suboptimal settings of PLLs.
>>
>> To address this, add support for handling runtime power management,
>> configuring plls and enabling critical clocks from qcom_cc_really_probe.
>> The clock controller can specify PLLs, critical clocks, and runtime PM
>> requirements in the descriptor data. The code in qcom_cc_really_probe()
>> ensures all necessary power domains are enabled before configuring PLLs
>> or critical clocks.
>>
>> This series updates SM8450 & SM8550 videocc drivers to handle rpm,
>> configure PLLs and enable critical clocks from within qcom_cc_really_probe()
>> using above support, so video PLLs are configured properly.
>>
>> This series fixes the below warning reported in SM8550 venus testing due
>> to video_cc_pll0 not properly getting configured during videocc probe
>>
>> [ 46.535132] Lucid PLL latch failed. Output may be unstable!
>>
>> The patch adding support to configure the PLLs from common code is
>> picked from below series and updated it.
>> https://lore.kernel.org/all/20250113-support-pll-reconfigure-v1-0-1fae6bc1062d@quicinc.com/
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
>> ---
>> Changes in v2:
>> - Added support to handle rpm, PLL configuration and enable critical
>> clocks from qcom_cc_really_probe() in common code as per v1 commments
>> from Bryan, Konrad and Dmitry
>> - Added patches to configure PLLs from common code
>> - Updated the SM8450, SM8550 videocc patches to use the newly
>> added support to handle rpm, configure PLLs from common code
>> - Split the DT change for each target separately as per
>> Dmitry comments
>> - Added R-By and A-By tags received on v1
>> - Link to v1: https://lore.kernel.org/r/20250218-videocc-pll-multi-pd-voting-v1-0-cfe6289ea29b@quicinc.com
>>
>> ---
>> Jagadeesh Kona (7):
>> dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
>> clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe
>> clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe
>> clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe
>> arm64: dts: qcom: Add MXC power domain to videocc node on SM8450
>> arm64: dts: qcom: Add MXC power domain to videocc node on SM8550
>> arm64: dts: qcom: Add MXC power domain to videocc node on SM8650
>>
> This list looks sparse.
>
> - camcc is missing
> - x1e is missing
> - sm8650 and sm8750 and both also missing
>
Since there are concerns about DT bindings ABI change of CAMCC given by
Krzysztof, likely CAMCC changes shall not be inserted into this series.
--
Best wishes,
Vladimir
next prev parent reply other threads:[~2025-03-11 10:12 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CMTYKKilQJYeHUYYKvlqnwv4Q2P-58Ic1v1ndS9HQ8Yhq2xpHuNThibFDjXDEQ1PyNbx__f9BVBr0peoTUdvPg==@protonmail.internalid>
2025-03-06 8:55 ` [PATCH v2 0/8] clk: qcom: Add support to attach multiple power domains in cc probe Jagadeesh Kona
2025-03-06 8:55 ` [PATCH v2 1/8] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain Jagadeesh Kona
2025-03-06 10:10 ` Dmitry Baryshkov
2025-03-11 8:47 ` Jagadeesh Kona
2025-03-11 9:49 ` Bryan O'Donoghue
2025-03-11 10:21 ` Konrad Dybcio
2025-03-12 7:14 ` Jagadeesh Kona
2025-03-06 8:55 ` [PATCH v2 2/8] clk: qcom: common: Add support to configure PLL Jagadeesh Kona
2025-03-06 12:22 ` Konrad Dybcio
2025-03-11 8:56 ` Jagadeesh Kona
2025-03-13 22:39 ` Bjorn Andersson
2025-03-20 16:29 ` Jagadeesh Kona
2025-03-06 8:55 ` [PATCH v2 3/8] clk: qcom: common: Manage rpm, configure PLLs & AON clks in really probe Jagadeesh Kona
2025-03-06 12:45 ` Konrad Dybcio
2025-03-11 8:48 ` Jagadeesh Kona
2025-03-07 8:47 ` Dmitry Baryshkov
2025-03-11 8:48 ` Jagadeesh Kona
2025-03-06 8:55 ` [PATCH v2 4/8] clk: qcom: videocc-sm8450: Move PLL & clk configuration to " Jagadeesh Kona
2025-03-11 9:54 ` Bryan O'Donoghue
2025-03-06 8:55 ` [PATCH v2 5/8] clk: qcom: videocc-sm8550: " Jagadeesh Kona
2025-03-06 8:55 ` [PATCH v2 6/8] arm64: dts: qcom: Add MXC power domain to videocc node on SM8450 Jagadeesh Kona
2025-03-06 8:55 ` [PATCH v2 7/8] arm64: dts: qcom: Add MXC power domain to videocc node on SM8550 Jagadeesh Kona
2025-03-06 8:55 ` [PATCH v2 8/8] arm64: dts: qcom: Add MXC power domain to videocc node on SM8650 Jagadeesh Kona
2025-03-11 9:52 ` [PATCH v2 0/8] clk: qcom: Add support to attach multiple power domains in cc probe Bryan O'Donoghue
2025-03-11 10:12 ` Vladimir Zapolskiy [this message]
2025-03-11 12:10 ` Bryan O'Donoghue
2025-03-11 17:55 ` Vladimir Zapolskiy
2025-03-11 18:11 ` Bryan O'Donoghue
2025-03-12 7:11 ` Jagadeesh Kona
2025-03-12 7:13 ` Jagadeesh Kona
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=46d4f090-3e31-414f-abfc-3d1018913c56@linaro.org \
--to=vladimir.zapolskiy@linaro.org \
--cc=andersson@kernel.org \
--cc=bryan.odonoghue@linaro.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=quic_ajipan@quicinc.com \
--cc=quic_imrashai@quicinc.com \
--cc=quic_jkona@quicinc.com \
--cc=quic_skakitap@quicinc.com \
--cc=quic_tdas@quicinc.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).