Re: [PATCH 4/4] arm64: dts: qcom: sm8250: camss: Add CCI definitions

[Bryan O'Donoghue <bryan.odonoghue@linaro.org>]

On 12/04/2022 03:06, Bjorn Andersson wrote:
> On Sat 09 Apr 11:45 CDT 2022, Bryan O'Donoghue wrote:
> 
>> sm8250 has two CCI busses with two I2C busses apiece.
>>
>> Co-developed-by: Julian Grahsl <jgrahsl@snap.com>
>> Signed-off-by: Julian Grahsl <jgrahsl@snap.com>
>> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 82 ++++++++++++++++++++++++++++
>>   1 file changed, 82 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index 91ed079edbf7..98e96527702b 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -3150,6 +3150,88 @@ videocc: clock-controller@abf0000 {
>>   			#power-domain-cells = <1>;
>>   		};
>>   
>> +		cci0: cci@ac4f000 {
>> +			compatible = "qcom,sm8250-cci";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			reg = <0 0x0ac4f000 0 0x1000>;
>> +			interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
>> +			power-domains = <&camcc TITAN_TOP_GDSC>;
>> +
>> +			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
>> +				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
>> +				 <&camcc CAM_CC_CPAS_AHB_CLK>,
>> +				 <&camcc CAM_CC_CCI_0_CLK>,
>> +				 <&camcc CAM_CC_CCI_0_CLK_SRC>;
>> +			clock-names = "camnoc_axi",
>> +				      "slow_ahb_src",
>> +				      "cpas_ahb",
>> +				      "cci",
>> +				      "cci_src";
>> +
>> +			pinctrl-names = "default", "sleep";
>> +			pinctrl-0 = <&cci0_default &cci1_default>;
>> +			pinctrl-1 = <&cci0_sleep &cci1_sleep>;
> 
> I would prefer that you include these in the same patch.

You mean CAMSS and CCI in the one patch ?
Sure.

> 
>> +
>> +			status = "disabled";
>> +
>> +			cci_i2c0: i2c-bus@0 {
>> +				reg = <0>;
>> +				clock-frequency = <1000000>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +
>> +			cci_i2c1: i2c-bus@1 {
>> +				reg = <1>;
>> +				clock-frequency = <1000000>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +			};
>> +		};
>> +
>> +		cci1: cci@ac50000 {
>> +			compatible = "qcom,sm8250-cci";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +
>> +			reg = <0 0x0ac50000 0 0x1000>;
>> +			interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
>> +			power-domains = <&camcc TITAN_TOP_GDSC>;
>> +
>> +			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
>> +				 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
>> +				 <&camcc CAM_CC_CPAS_AHB_CLK>,
>> +				 <&camcc CAM_CC_CCI_1_CLK>,
>> +				 <&camcc CAM_CC_CCI_1_CLK_SRC>;
>> +			clock-names = "camnoc_axi",
>> +				      "slow_ahb_src",
>> +				      "cpas_ahb",
>> +				      "cci",
>> +				      "cci_src";
>> +
>> +			pinctrl-names = "default", "sleep";
>> +			pinctrl-0 = <&cci2_default &cci3_default>;
>> +			pinctrl-1 = <&cci2_sleep &cci3_sleep>;
>> +
>> +			status = "disabled";
>> +
>> +			cci_i2c2: i2c-bus@0 {
> 
> Are these names (the label) used somewhere in the schematics? How about
> cci0_i2c0 and cci1_i2c0 instead (unless these names are defined by some
> documentation)?

Schematic just says cci_i2c_sda0, cci_i2c_sda3 and so on.

I'll rename.

---
bod