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[185.69.38.8]) by smtp.gmail.com with ESMTPSA id u13-20020a05651220cd00b004a91d1b3070sm628423lfr.308.2022.12.10.00.39.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Dec 2022 00:39:09 -0800 (PST) Message-ID: <46e1321e-ff27-7b95-6f93-975d08802626@gmail.com> Date: Sat, 10 Dec 2022 10:49:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Content-Language: en-US To: Vignesh Raghavendra , Vinod Koul , Rob Herring , Krzysztof Kozlowski Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221206043554.1521522-1-vigneshr@ti.com> <20221206043554.1521522-6-vigneshr@ti.com> From: =?UTF-8?Q?P=c3=a9ter_Ujfalusi?= Subject: Re: [PATCH 5/5] dmaengine: ti: k3-udma: Add support for BCDMA CSI RX In-Reply-To: <20221206043554.1521522-6-vigneshr@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 12/6/22 06:35, Vignesh Raghavendra wrote: > BCDMA CSI RX present on AM62Ax SoC is a dedicated DMA for servicing > Camera Serial Interface (CSI) IP. Add support for the same. > > Signed-off-by: Vignesh Raghavendra > --- > drivers/dma/ti/k3-udma.c | 37 ++++++++++++++++++++++++++++++++----- > 1 file changed, 32 insertions(+), 5 deletions(-) > > diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c > index 19fce52a9b53..a8b497ed3f30 100644 > --- a/drivers/dma/ti/k3-udma.c > +++ b/drivers/dma/ti/k3-udma.c > @@ -135,6 +135,7 @@ struct udma_match_data { > u32 flags; > u32 statictr_z_mask; > u8 burst_size[3]; > + struct udma_soc_data *soc_data; > }; > > struct udma_soc_data { > @@ -4295,6 +4296,25 @@ static struct udma_match_data j721e_mcu_data = { > }, > }; > > +static struct udma_soc_data am62a_dmss_csi_soc_data = { > + .oes = { > + .bcdma_rchan_data = 0xe00, > + .bcdma_rchan_ring = 0x1000, > + }, > +}; > + > +static struct udma_match_data am62a_bcdma_csirx_data = { > + .type = DMA_TYPE_BCDMA, > + .psil_base = 0x3100, > + .enable_memcpy_support = false, > + .burst_size = { > + TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */ > + 0, /* No H Channels */ > + 0, /* No UH Channels */ > + }, > + .soc_data = &am62a_dmss_csi_soc_data, > +}; > + > static struct udma_match_data am64_bcdma_data = { > .type = DMA_TYPE_BCDMA, > .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */ > @@ -4344,6 +4364,10 @@ static const struct of_device_id udma_of_match[] = { > .compatible = "ti,am64-dmss-pktdma", > .data = &am64_pktdma_data, > }, > + { > + .compatible = "ti,am62a-dmss-bcdma-csirx", > + .data = &am62a_bcdma_csirx_data, > + }, > { /* Sentinel */ }, > }; > > @@ -5272,12 +5296,15 @@ static int udma_probe(struct platform_device *pdev) > } > ud->match_data = match->data; > > - soc = soc_device_match(k3_soc_devices); > - if (!soc) { > - dev_err(dev, "No compatible SoC found\n"); > - return -ENODEV; > + ud->soc_data = ud->match_data->soc_data; > + if (!ud->soc_data) { > + soc = soc_device_match(k3_soc_devices); > + if (!soc) { > + dev_err(dev, "No compatible SoC found\n"); > + return -ENODEV; > + } > + ud->soc_data = soc->data; > } > - ud->soc_data = soc->data; Right, the original design was based on the promise that a DMSS will contain maximum 1 BCDMA and/or 1 PKTDMA, looks like now a DMSS have 2 BCDMAs? The only possible issue I can see is that if in future SoCs the Output Event Offsets got shuffled for the BCDMAs, but then a new compatible for each SoC might just work. Nice solution with minimal change! ;) > > ret = udma_get_mmrs(pdev, ud); > if (ret) -- Péter