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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id fx24-20020a170906b75800b006fec63e564bsm7616985ejb.30.2022.06.29.04.32.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Jun 2022 04:32:03 -0700 (PDT) Message-ID: <479a021a-36eb-7b44-9e14-51e16d1b64fb@linaro.org> Date: Wed, 29 Jun 2022 13:32:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v5 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON Content-Language: en-US To: Rajendra Nayak , Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thara Gopinath References: <20220629075250.17610-1-krzysztof.kozlowski@linaro.org> <20220629075250.17610-5-krzysztof.kozlowski@linaro.org> <87b83a0c-0ea2-6839-1d90-8f1145ed9ed2@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <87b83a0c-0ea2-6839-1d90-8f1145ed9ed2@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 29/06/2022 13:22, Rajendra Nayak wrote: > > > On 6/29/2022 1:22 PM, Krzysztof Kozlowski wrote: >> Add device node for CPU-memory BWMON device (bandwidth monitoring) on >> SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level >> Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth >> votes from cpufreq (CPU nodes) thus achieve high memory throughput even >> with lower CPU frequencies. >> >> Co-developed-by: Thara Gopinath >> Signed-off-by: Thara Gopinath >> Signed-off-by: Krzysztof Kozlowski >> --- >> arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++ >> 1 file changed, 38 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi >> index 83e8b63f0910..e0f088996390 100644 >> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >> @@ -2026,6 +2026,44 @@ llcc: system-cache-controller@1100000 { >> interrupts = ; >> }; >> >> + pmu@1436400 { >> + compatible = "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon"; >> + reg = <0 0x01436400 0 0x600>; >> + interrupts = ; >> + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; >> + >> + operating-points-v2 = <&cpu_bwmon_opp_table>; >> + >> + cpu_bwmon_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + /* >> + * The interconnect paths bandwidths taken from >> + * cpu4_opp_table bandwidth. >> + * They also match different tables from >> + * msm-4.9 downstream kernel: >> + * - the OSM L3 from bandwidth table of >> + * qcom,cpu4-l3lat-mon (qcom,core-dev-table); >> + * bus width: 16 bytes; >> + */ > > Maybe the comment needs an update? Yes, a bit. Best regards, Krzysztof