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[109.252.137.194]) by smtp.googlemail.com with ESMTPSA id w9-20020a05651203c900b0044399c17e58sm163232lfp.224.2022.02.25.02.26.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Feb 2022 02:26:15 -0800 (PST) Message-ID: <47ddcaf3-4544-2b7c-a2f6-1f6346907f33@gmail.com> Date: Fri, 25 Feb 2022 13:26:14 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v7 10/24] drm/rockchip: dw_hdmi: Add support for hclk Content-Language: en-US To: Sascha Hauer , dri-devel@lists.freedesktop.org Cc: devicetree@vger.kernel.org, Benjamin Gaignard , Peter Geis , Sandy Huang , linux-rockchip@lists.infradead.org, Michael Riesch , kernel@pengutronix.de, Andy Yan , linux-arm-kernel@lists.infradead.org References: <20220225075150.2729401-1-s.hauer@pengutronix.de> <20220225075150.2729401-11-s.hauer@pengutronix.de> From: Dmitry Osipenko In-Reply-To: <20220225075150.2729401-11-s.hauer@pengutronix.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 25.02.2022 10:51, Sascha Hauer пишет: > The rk3568 HDMI has an additional clock that needs to be enabled for the > HDMI controller to work. The purpose of that clock is not clear. It is > named "hclk" in the downstream driver, so use the same name. > > Signed-off-by: Sascha Hauer > --- > > Notes: > Changes since v5: > - Use devm_clk_get_optional rather than devm_clk_get > > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > index fe4f9556239ac..c6c00e8779ab5 100644 > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > @@ -76,6 +76,7 @@ struct rockchip_hdmi { > const struct rockchip_hdmi_chip_data *chip_data; > struct clk *ref_clk; > struct clk *grf_clk; > + struct clk *hclk_clk; > struct dw_hdmi *hdmi; > struct regulator *avdd_0v9; > struct regulator *avdd_1v8; > @@ -229,6 +230,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) > return PTR_ERR(hdmi->grf_clk); > } > > + hdmi->hclk_clk = devm_clk_get_optional(hdmi->dev, "hclk"); > + if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) { Have you tried to investigate the hclk? I'm still thinking that's not only HDMI that needs this clock and then the hardware description doesn't look correct.