From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matt Sealey Subject: Re: GPIO - marking individual pins (not) available in device tree Date: Fri, 24 Oct 2008 17:14:26 -0500 Message-ID: <490248C2.9020104@genesi-usa.com> References: <4900ED81.3040202@genesi-usa.com> <4900F90B.80703@firmworks.com> <4901032F.3090805@genesi-usa.com> <49011C42.2020101@firmworks.com> <20081024032944.GE4267@yookeroo.seuss> <49014C69.8020408@firmworks.com> <20081024044511.GI4267@yookeroo.seuss> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20081024044511.GI4267@yookeroo.seuss> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linuxppc-dev-bounces+glppd-linuxppc64-dev=m.gmane.org@ozlabs.org Errors-To: linuxppc-dev-bounces+glppd-linuxppc64-dev=m.gmane.org@ozlabs.org To: Mitch Bradley , Matt Sealey , linuxppc-dev list , devicetree-discuss list List-Id: devicetree@vger.kernel.org David Gibson wrote: > Don't be patronising. > > There is an existing address space defined by the gpio binding. > Defining another one is pointless redundancy. This is standard good > ideas in computer science, no further argument necessary. The existing address space, and the patches Anton etc. just submitted which I started this discussion to address, don't fulfil certain needs. You could do better than call it insane, by describing how you would define a gpio bank that used 3 seperate pins which are NOT together in a register, using a base address (reg) and base property (offset of first pin) with the current system? -- Matt Sealey Genesi, Manager, Developer Relations