[PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.

Board features:
- JH7110S SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable 64GiB eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI

VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html

Changes since v1:
- Drop patch 1 because it is applied.
- Rename jh7110.dtsi to jh711x.dtsi.
- Move the content of jh7110-common.dtsi to the new file
  jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
patch 4:
- Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
patch 5:
- Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-2-lite.dtsi.

Changes since RFC:
- Add jh7110s compatible to the generic cpufreq driver.
- Fix the dtbs_check error by adding the missing "enable-gpios" property
  in jh7110 pcie dt-bindings.
- Rebase on the latest mainline.
- Add VisionFive 2 Lite eMMC board device tree and add a common board dtsi
  for VisionFive 2 Lite variants.
- Add usb switch pin configuration (GPIO62).
- Improve the commit messages.

History:
v1: https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfivetech.com/
RFC: https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivetech.com/

Hal Feng (8):
  dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
  dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
    board
  riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
  riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to
    it
  riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110
    common dtsi
  riscv: dts: starfive: Add common board dtsi for JH7110s and VisionFive
    2 Lite variants
  riscv: dts: starfive: Add VisionFive 2 Lite board device tree
  riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree

 .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
 .../devicetree/bindings/riscv/starfive.yaml   |   6 +
 arch/riscv/boot/dts/starfive/Makefile         |   3 +
 .../boot/dts/starfive/jh7110-common.dtsi      | 653 +----------------
 .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
 ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
 .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
 .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
 .../boot/dts/starfive/jh711x-common.dtsi      | 656 ++++++++++++++++++
 .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
 10 files changed, 879 insertions(+), 654 deletions(-)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
 rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} (99%)


base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c
-- 
2.43.2

[PATCH v2 1/8] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property

[Hal Feng]

Add enable-gpios property for controlling the PCI bus device power.
This property had been supported in the driver but not added in the
dt-bindings.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Fixes: 22fe32239770 ("dt-bindings: PCI: Add StarFive JH7110 PCIe controller")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../devicetree/bindings/pci/starfive,jh7110-pcie.yaml         | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
index 33c80626e8ec..1e36f92ec852 100644
--- a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
@@ -59,6 +59,10 @@ properties:
     description:
       The phandle to System Register Controller syscon node.
 
+  enable-gpios:
+    description: GPIO used to enable the PCI bus device power
+    maxItems: 1
+
   perst-gpios:
     description: GPIO controlled connection to PERST# signal
     maxItems: 1
-- 
2.43.2

[PATCH v2 2/8] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[Hal Feng]

Add device tree bindings for the StarFive JH7110S SoC
and the VisionFive 2 Lite board equipped with it.

JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade
and up to 1.25GHz. Its CPU cores and peripherals are the same as
those of the JH7110 SoC.

VisionFive 2 Lite boards have SD card version (default) and eMMC version,
which are called "VisionFive 2 Lite" and "VisionFive 2 Lite eMMC"
respectively.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 04510341a71e..797d9956b949 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -35,6 +35,12 @@ properties:
               - starfive,visionfive-2-v1.3b
           - const: starfive,jh7110
 
+      - items:
+          - enum:
+              - starfive,visionfive-2-lite
+              - starfive,visionfive-2-lite-emmc
+          - const: starfive,jh7110s
+
 additionalProperties: true
 
 ...
-- 
2.43.2

[PATCH v2 3/8] riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi

[Hal Feng]

JH7110S uses the same devices as JH7110. Rename jh7110.dtsi to jh711x.dtsi
for preparing to add JH7110S based board device trees.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi           | 2 +-
 arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} (100%)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 083ec80b4e44..809274625615 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -5,7 +5,7 @@
  */
 
 /dts-v1/;
-#include "jh7110.dtsi"
+#include "jh711x.dtsi"
 #include "jh7110-pinfunc.h"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh711x.dtsi
similarity index 100%
rename from arch/riscv/boot/dts/starfive/jh7110.dtsi
rename to arch/riscv/boot/dts/starfive/jh711x.dtsi
-- 
2.43.2

Re: [PATCH v2 3/8] riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi

[E Shattow]

On 11/7/25 01:55, Hal Feng wrote:
> JH7110S uses the same devices as JH7110. Rename jh7110.dtsi to jh711x.dtsi
> for preparing to add JH7110S based board device trees.
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/jh7110-common.dtsi           | 2 +-
>  arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} | 0
>  2 files changed, 1 insertion(+), 1 deletion(-)
>  rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} (100%)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index 083ec80b4e44..809274625615 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -5,7 +5,7 @@
>   */
>  
>  /dts-v1/;
> -#include "jh7110.dtsi"
> +#include "jh711x.dtsi"
>  #include "jh7110-pinfunc.h"
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/leds/common.h>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh711x.dtsi
> similarity index 100%
> rename from arch/riscv/boot/dts/starfive/jh7110.dtsi
> rename to arch/riscv/boot/dts/starfive/jh711x.dtsi

Reviewed-by: E Shattow <e@freeshell.de>

[PATCH v2 4/8] riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to it

[Hal Feng]

Preparing to add JH7110S based board device trees, move the content of
jh7110-common.dtsi to the new file jh711x-common.dtsi and move opp table
to jh7110-common.dtsi.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../boot/dts/starfive/jh7110-common.dtsi      | 665 +-----------------
 .../boot/dts/starfive/jh711x-common.dtsi      | 664 +++++++++++++++++
 arch/riscv/boot/dts/starfive/jh711x.dtsi      |  16 -
 3 files changed, 678 insertions(+), 667 deletions(-)
 create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 809274625615..dd5805ef70a1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -5,660 +5,23 @@
  */
 
 /dts-v1/;
-#include "jh711x.dtsi"
-#include "jh7110-pinfunc.h"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
+#include "jh711x-common.dtsi"
 
-/ {
-	aliases {
-		ethernet0 = &gmac0;
-		i2c0 = &i2c0;
-		i2c2 = &i2c2;
-		i2c5 = &i2c5;
-		i2c6 = &i2c6;
-		mmc0 = &mmc0;
-		mmc1 = &mmc1;
-		serial0 = &uart0;
+&cpu_opp {
+	opp-375000000 {
+		opp-hz = /bits/ 64 <375000000>;
+		opp-microvolt = <800000>;
 	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0x1 0x0>;
-		bootph-pre-ram;
-	};
-
-	gpio-restart {
-		compatible = "gpio-restart";
-		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
-		priority = <224>;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led_status_power: led-0 {
-			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	pwmdac_codec: audio-codec {
-		compatible = "linux,spdif-dit";
-		#sound-dai-cells = <0>;
-	};
-
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		simple-audio-card,dai-link@0 {
-			reg = <0>;
-			format = "left_j";
-			bitclock-master = <&sndcpu0>;
-			frame-master = <&sndcpu0>;
-
-			sndcpu0: cpu {
-				sound-dai = <&pwmdac>;
-			};
-
-			codec {
-				sound-dai = <&pwmdac_codec>;
-			};
-		};
-	};
-};
-
-&cpus {
-	timebase-frequency = <4000000>;
-};
-
-&dvp_clk {
-	clock-frequency = <74250000>;
-};
-
-&gmac0_rgmii_rxin {
-	clock-frequency = <125000000>;
-};
-
-&gmac0_rmii_refin {
-	clock-frequency = <50000000>;
-};
-
-&gmac1_rgmii_rxin {
-	clock-frequency = <125000000>;
-};
-
-&gmac1_rmii_refin {
-	clock-frequency = <50000000>;
-};
-
-&hdmitx0_pixelclk {
-	clock-frequency = <297000000>;
-};
-
-&i2srx_bclk_ext {
-	clock-frequency = <12288000>;
-};
-
-&i2srx_lrck_ext {
-	clock-frequency = <192000>;
-};
-
-&i2stx_bclk_ext {
-	clock-frequency = <12288000>;
-};
-
-&i2stx_lrck_ext {
-	clock-frequency = <192000>;
-};
-
-&mclk_ext {
-	clock-frequency = <12288000>;
-};
-
-&osc {
-	clock-frequency = <24000000>;
-};
-
-&rtc_osc {
-	clock-frequency = <32768>;
-};
-
-&tdm_ext {
-	clock-frequency = <49152000>;
-};
-
-&camss {
-	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
-			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
-	assigned-clock-rates = <49500000>, <198000000>;
-
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-		};
-
-		port@1 {
-			reg = <1>;
-
-			camss_from_csi2rx: endpoint {
-				remote-endpoint = <&csi2rx_to_camss>;
-			};
-		};
+	opp-500000000 {
+		opp-hz = /bits/ 64 <500000000>;
+		opp-microvolt = <800000>;
 	};
-};
-
-&csi2rx {
-	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
-	assigned-clock-rates = <297000000>;
-
-	ports {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		port@0 {
-			reg = <0>;
-
-			/* remote MIPI sensor endpoint */
-		};
-
-		port@1 {
-			reg = <1>;
-
-			csi2rx_to_camss: endpoint {
-				remote-endpoint = <&camss_from_csi2rx>;
-			};
-		};
+	opp-750000000 {
+		opp-hz = /bits/ 64 <750000000>;
+		opp-microvolt = <800000>;
 	};
-};
-
-&gmac0 {
-	phy-handle = <&phy0>;
-	phy-mode = "rgmii-id";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "snps,dwmac-mdio";
-
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-		};
+	opp-1500000000 {
+		opp-hz = /bits/ 64 <1500000000>;
+		opp-microvolt = <1040000>;
 	};
 };
-
-&i2c0 {
-	clock-frequency = <100000>;
-	i2c-sda-hold-time-ns = <300>;
-	i2c-sda-falling-time-ns = <510>;
-	i2c-scl-falling-time-ns = <510>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c0_pins>;
-};
-
-&i2c2 {
-	clock-frequency = <100000>;
-	i2c-sda-hold-time-ns = <300>;
-	i2c-sda-falling-time-ns = <510>;
-	i2c-scl-falling-time-ns = <510>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c2_pins>;
-	status = "okay";
-};
-
-&i2c5 {
-	clock-frequency = <100000>;
-	i2c-sda-hold-time-ns = <300>;
-	i2c-sda-falling-time-ns = <510>;
-	i2c-scl-falling-time-ns = <510>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c5_pins>;
-	status = "okay";
-
-	axp15060: pmic@36 {
-		compatible = "x-powers,axp15060";
-		reg = <0x36>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-
-		regulators {
-			vcc_3v3: dcdc1 {
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc_3v3";
-			};
-
-			vdd_cpu: dcdc2 {
-				regulator-always-on;
-				regulator-min-microvolt = <500000>;
-				regulator-max-microvolt = <1540000>;
-				regulator-name = "vdd_cpu";
-			};
-
-			emmc_vdd: aldo4 {
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "emmc_vdd";
-			};
-		};
-	};
-
-	eeprom@50 {
-		compatible = "atmel,24c04";
-		reg = <0x50>;
-		bootph-pre-ram;
-		pagesize = <16>;
-	};
-};
-
-&i2c6 {
-	clock-frequency = <100000>;
-	i2c-sda-hold-time-ns = <300>;
-	i2c-sda-falling-time-ns = <510>;
-	i2c-scl-falling-time-ns = <510>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c6_pins>;
-	status = "okay";
-};
-
-&mmc0 {
-	max-frequency = <100000000>;
-	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
-	assigned-clock-rates = <50000000>;
-	bus-width = <8>;
-	bootph-pre-ram;
-	cap-mmc-highspeed;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	cap-mmc-hw-reset;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc0_pins>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&emmc_vdd>;
-	status = "okay";
-};
-
-&mmc1 {
-	max-frequency = <100000000>;
-	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
-	assigned-clock-rates = <50000000>;
-	bus-width = <4>;
-	bootph-pre-ram;
-	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
-	disable-wp;
-	cap-sd-highspeed;
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc1_pins>;
-	status = "okay";
-};
-
-&pcie0 {
-	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
-	phys = <&pciephy0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie0_pins>;
-};
-
-&pcie1 {
-	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
-	phys = <&pciephy1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie1_pins>;
-};
-
-&pwmdac {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwmdac_pins>;
-};
-
-&qspi {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	nor_flash: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		bootph-pre-ram;
-		cdns,read-delay = <2>;
-		spi-max-frequency = <100000000>;
-		cdns,tshsl-ns = <1>;
-		cdns,tsd2d-ns = <1>;
-		cdns,tchsh-ns = <1>;
-		cdns,tslch-ns = <1>;
-
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			spl@0 {
-				reg = <0x0 0xf0000>;
-			};
-			uboot-env@f0000 {
-				reg = <0xf0000 0x10000>;
-			};
-			uboot@100000 {
-				reg = <0x100000 0xf00000>;
-			};
-		};
-	};
-};
-
-&pwm {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pwm_pins>;
-};
-
-&spi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0_pins>;
-};
-
-&syscrg {
-	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
-			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
-			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
-			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
-			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
-			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
-	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
-				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
-				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
-				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
-	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
-};
-
-&sysgpio {
-	i2c0_pins: i2c0-0 {
-		i2c-pins {
-			pinmux = <GPIOMUX(57, GPOUT_LOW,
-					      GPOEN_SYS_I2C0_CLK,
-					      GPI_SYS_I2C0_CLK)>,
-				 <GPIOMUX(58, GPOUT_LOW,
-					      GPOEN_SYS_I2C0_DATA,
-					      GPI_SYS_I2C0_DATA)>;
-			bias-disable; /* external pull-up */
-			input-enable;
-			input-schmitt-enable;
-		};
-	};
-
-	i2c2_pins: i2c2-0 {
-		i2c-pins {
-			pinmux = <GPIOMUX(3, GPOUT_LOW,
-					     GPOEN_SYS_I2C2_CLK,
-					     GPI_SYS_I2C2_CLK)>,
-				 <GPIOMUX(2, GPOUT_LOW,
-					     GPOEN_SYS_I2C2_DATA,
-					     GPI_SYS_I2C2_DATA)>;
-			bias-disable; /* external pull-up */
-			input-enable;
-			input-schmitt-enable;
-		};
-	};
-
-	i2c5_pins: i2c5-0 {
-		bootph-pre-ram;
-
-		i2c-pins {
-			pinmux = <GPIOMUX(19, GPOUT_LOW,
-					      GPOEN_SYS_I2C5_CLK,
-					      GPI_SYS_I2C5_CLK)>,
-				 <GPIOMUX(20, GPOUT_LOW,
-					      GPOEN_SYS_I2C5_DATA,
-					      GPI_SYS_I2C5_DATA)>;
-			bias-disable; /* external pull-up */
-			bootph-pre-ram;
-			input-enable;
-			input-schmitt-enable;
-		};
-	};
-
-	i2c6_pins: i2c6-0 {
-		i2c-pins {
-			pinmux = <GPIOMUX(16, GPOUT_LOW,
-					      GPOEN_SYS_I2C6_CLK,
-					      GPI_SYS_I2C6_CLK)>,
-				 <GPIOMUX(17, GPOUT_LOW,
-					      GPOEN_SYS_I2C6_DATA,
-					      GPI_SYS_I2C6_DATA)>;
-			bias-disable; /* external pull-up */
-			input-enable;
-			input-schmitt-enable;
-		};
-	};
-
-	mmc0_pins: mmc0-0 {
-		mmc-pins {
-			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
-				 <PINMUX(PAD_SD0_CMD, 0)>,
-				 <PINMUX(PAD_SD0_DATA0, 0)>,
-				 <PINMUX(PAD_SD0_DATA1, 0)>,
-				 <PINMUX(PAD_SD0_DATA2, 0)>,
-				 <PINMUX(PAD_SD0_DATA3, 0)>,
-				 <PINMUX(PAD_SD0_DATA4, 0)>,
-				 <PINMUX(PAD_SD0_DATA5, 0)>,
-				 <PINMUX(PAD_SD0_DATA6, 0)>,
-				 <PINMUX(PAD_SD0_DATA7, 0)>;
-			bias-pull-up;
-			drive-strength = <12>;
-			input-enable;
-		};
-	};
-
-	mmc1_pins: mmc1-0 {
-		clk-pins {
-			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
-					      GPOEN_ENABLE,
-					      GPI_NONE)>;
-			bias-pull-up;
-			drive-strength = <12>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
-		mmc-pins {
-			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
-					     GPOEN_SYS_SDIO1_CMD,
-					     GPI_SYS_SDIO1_CMD)>,
-				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
-					      GPOEN_SYS_SDIO1_DATA0,
-					      GPI_SYS_SDIO1_DATA0)>,
-				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
-					      GPOEN_SYS_SDIO1_DATA1,
-					      GPI_SYS_SDIO1_DATA1)>,
-				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
-					     GPOEN_SYS_SDIO1_DATA2,
-					     GPI_SYS_SDIO1_DATA2)>,
-				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
-					     GPOEN_SYS_SDIO1_DATA3,
-					     GPI_SYS_SDIO1_DATA3)>;
-			bias-pull-up;
-			drive-strength = <12>;
-			input-enable;
-			input-schmitt-enable;
-			slew-rate = <0>;
-		};
-	};
-
-	pcie0_pins: pcie0-0 {
-		clkreq-pins {
-			pinmux = <GPIOMUX(27, GPOUT_LOW,
-					      GPOEN_DISABLE,
-					      GPI_NONE)>;
-			bias-pull-down;
-			drive-strength = <2>;
-			input-enable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
-		wake-pins {
-			pinmux = <GPIOMUX(32, GPOUT_LOW,
-					      GPOEN_DISABLE,
-					      GPI_NONE)>;
-			bias-pull-up;
-			drive-strength = <2>;
-			input-enable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-	};
-
-	pcie1_pins: pcie1-0 {
-		clkreq-pins {
-			pinmux = <GPIOMUX(29, GPOUT_LOW,
-					      GPOEN_DISABLE,
-					      GPI_NONE)>;
-			bias-pull-down;
-			drive-strength = <2>;
-			input-enable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
-		wake-pins {
-			pinmux = <GPIOMUX(21, GPOUT_LOW,
-				      GPOEN_DISABLE,
-					      GPI_NONE)>;
-			bias-pull-up;
-			drive-strength = <2>;
-			input-enable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-	};
-
-	pwmdac_pins: pwmdac-0 {
-		pwmdac-pins {
-			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
-					      GPOEN_ENABLE,
-					      GPI_NONE)>,
-				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
-					      GPOEN_ENABLE,
-					      GPI_NONE)>;
-			bias-disable;
-			drive-strength = <2>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-	};
-
-	pwm_pins: pwm-0 {
-		pwm-pins {
-			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
-					      GPOEN_SYS_PWM0_CHANNEL0,
-					      GPI_NONE)>,
-				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
-					      GPOEN_SYS_PWM0_CHANNEL1,
-					      GPI_NONE)>;
-			bias-disable;
-			drive-strength = <12>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-	};
-
-	spi0_pins: spi0-0 {
-		mosi-pins {
-			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
-					      GPOEN_ENABLE,
-					      GPI_NONE)>;
-			bias-disable;
-			input-disable;
-			input-schmitt-disable;
-		};
-
-		miso-pins {
-			pinmux = <GPIOMUX(53, GPOUT_LOW,
-					      GPOEN_DISABLE,
-					      GPI_SYS_SPI0_RXD)>;
-			bias-pull-up;
-			input-enable;
-			input-schmitt-enable;
-		};
-
-		sck-pins {
-			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
-					      GPOEN_ENABLE,
-					      GPI_SYS_SPI0_CLK)>;
-			bias-disable;
-			input-disable;
-			input-schmitt-disable;
-		};
-
-		ss-pins {
-			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
-					      GPOEN_ENABLE,
-					      GPI_SYS_SPI0_FSS)>;
-			bias-disable;
-			input-disable;
-			input-schmitt-disable;
-		};
-	};
-
-	uart0_pins: uart0-0 {
-		tx-pins {
-			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
-					     GPOEN_ENABLE,
-					     GPI_NONE)>;
-			bias-disable;
-			drive-strength = <12>;
-			input-disable;
-			input-schmitt-disable;
-			slew-rate = <0>;
-		};
-
-		rx-pins {
-			pinmux = <GPIOMUX(6, GPOUT_LOW,
-					     GPOEN_DISABLE,
-					     GPI_SYS_UART0_RX)>;
-			bias-disable; /* external pull-up */
-			drive-strength = <2>;
-			input-enable;
-			input-schmitt-enable;
-			slew-rate = <0>;
-		};
-	};
-};
-
-&uart0 {
-	bootph-pre-ram;
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
-	status = "okay";
-};
-
-&U74_1 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&U74_2 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&U74_3 {
-	cpu-supply = <&vdd_cpu>;
-};
-
-&U74_4 {
-	cpu-supply = <&vdd_cpu>;
-};
diff --git a/arch/riscv/boot/dts/starfive/jh711x-common.dtsi b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
new file mode 100644
index 000000000000..809274625615
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
@@ -0,0 +1,664 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh711x.dtsi"
+#include "jh7110-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
+
+/ {
+	aliases {
+		ethernet0 = &gmac0;
+		i2c0 = &i2c0;
+		i2c2 = &i2c2;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		mmc0 = &mmc0;
+		mmc1 = &mmc1;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x1 0x0>;
+		bootph-pre-ram;
+	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+		priority = <224>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status_power: led-0 {
+			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pwmdac_codec: audio-codec {
+		compatible = "linux,spdif-dit";
+		#sound-dai-cells = <0>;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		simple-audio-card,dai-link@0 {
+			reg = <0>;
+			format = "left_j";
+			bitclock-master = <&sndcpu0>;
+			frame-master = <&sndcpu0>;
+
+			sndcpu0: cpu {
+				sound-dai = <&pwmdac>;
+			};
+
+			codec {
+				sound-dai = <&pwmdac_codec>;
+			};
+		};
+	};
+};
+
+&cpus {
+	timebase-frequency = <4000000>;
+};
+
+&dvp_clk {
+	clock-frequency = <74250000>;
+};
+
+&gmac0_rgmii_rxin {
+	clock-frequency = <125000000>;
+};
+
+&gmac0_rmii_refin {
+	clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+	clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+	clock-frequency = <50000000>;
+};
+
+&hdmitx0_pixelclk {
+	clock-frequency = <297000000>;
+};
+
+&i2srx_bclk_ext {
+	clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+	clock-frequency = <192000>;
+};
+
+&i2stx_bclk_ext {
+	clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+	clock-frequency = <192000>;
+};
+
+&mclk_ext {
+	clock-frequency = <12288000>;
+};
+
+&osc {
+	clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+	clock-frequency = <32768>;
+};
+
+&tdm_ext {
+	clock-frequency = <49152000>;
+};
+
+&camss {
+	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
+			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
+	assigned-clock-rates = <49500000>, <198000000>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+		};
+
+		port@1 {
+			reg = <1>;
+
+			camss_from_csi2rx: endpoint {
+				remote-endpoint = <&csi2rx_to_camss>;
+			};
+		};
+	};
+};
+
+&csi2rx {
+	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
+	assigned-clock-rates = <297000000>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			/* remote MIPI sensor endpoint */
+		};
+
+		port@1 {
+			reg = <1>;
+
+			csi2rx_to_camss: endpoint {
+				remote-endpoint = <&camss_from_csi2rx>;
+			};
+		};
+	};
+};
+
+&gmac0 {
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-id";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <100000>;
+	i2c-sda-hold-time-ns = <300>;
+	i2c-sda-falling-time-ns = <510>;
+	i2c-scl-falling-time-ns = <510>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	i2c-sda-hold-time-ns = <300>;
+	i2c-sda-falling-time-ns = <510>;
+	i2c-scl-falling-time-ns = <510>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	status = "okay";
+};
+
+&i2c5 {
+	clock-frequency = <100000>;
+	i2c-sda-hold-time-ns = <300>;
+	i2c-sda-falling-time-ns = <510>;
+	i2c-scl-falling-time-ns = <510>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5_pins>;
+	status = "okay";
+
+	axp15060: pmic@36 {
+		compatible = "x-powers,axp15060";
+		reg = <0x36>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		regulators {
+			vcc_3v3: dcdc1 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc_3v3";
+			};
+
+			vdd_cpu: dcdc2 {
+				regulator-always-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1540000>;
+				regulator-name = "vdd_cpu";
+			};
+
+			emmc_vdd: aldo4 {
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "emmc_vdd";
+			};
+		};
+	};
+
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		bootph-pre-ram;
+		pagesize = <16>;
+	};
+};
+
+&i2c6 {
+	clock-frequency = <100000>;
+	i2c-sda-hold-time-ns = <300>;
+	i2c-sda-falling-time-ns = <510>;
+	i2c-scl-falling-time-ns = <510>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6_pins>;
+	status = "okay";
+};
+
+&mmc0 {
+	max-frequency = <100000000>;
+	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+	assigned-clock-rates = <50000000>;
+	bus-width = <8>;
+	bootph-pre-ram;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	cap-mmc-hw-reset;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+	status = "okay";
+};
+
+&mmc1 {
+	max-frequency = <100000000>;
+	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+	assigned-clock-rates = <50000000>;
+	bus-width = <4>;
+	bootph-pre-ram;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	cap-sd-highspeed;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	status = "okay";
+};
+
+&pcie0 {
+	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+	phys = <&pciephy0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_pins>;
+};
+
+&pcie1 {
+	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+	phys = <&pciephy1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie1_pins>;
+};
+
+&pwmdac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwmdac_pins>;
+};
+
+&qspi {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	nor_flash: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		bootph-pre-ram;
+		cdns,read-delay = <2>;
+		spi-max-frequency = <100000000>;
+		cdns,tshsl-ns = <1>;
+		cdns,tsd2d-ns = <1>;
+		cdns,tchsh-ns = <1>;
+		cdns,tslch-ns = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			spl@0 {
+				reg = <0x0 0xf0000>;
+			};
+			uboot-env@f0000 {
+				reg = <0xf0000 0x10000>;
+			};
+			uboot@100000 {
+				reg = <0x100000 0xf00000>;
+			};
+		};
+	};
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+};
+
+&syscrg {
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
+			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
+			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
+};
+
+&sysgpio {
+	i2c0_pins: i2c0-0 {
+		i2c-pins {
+			pinmux = <GPIOMUX(57, GPOUT_LOW,
+					      GPOEN_SYS_I2C0_CLK,
+					      GPI_SYS_I2C0_CLK)>,
+				 <GPIOMUX(58, GPOUT_LOW,
+					      GPOEN_SYS_I2C0_DATA,
+					      GPI_SYS_I2C0_DATA)>;
+			bias-disable; /* external pull-up */
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	i2c2_pins: i2c2-0 {
+		i2c-pins {
+			pinmux = <GPIOMUX(3, GPOUT_LOW,
+					     GPOEN_SYS_I2C2_CLK,
+					     GPI_SYS_I2C2_CLK)>,
+				 <GPIOMUX(2, GPOUT_LOW,
+					     GPOEN_SYS_I2C2_DATA,
+					     GPI_SYS_I2C2_DATA)>;
+			bias-disable; /* external pull-up */
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	i2c5_pins: i2c5-0 {
+		bootph-pre-ram;
+
+		i2c-pins {
+			pinmux = <GPIOMUX(19, GPOUT_LOW,
+					      GPOEN_SYS_I2C5_CLK,
+					      GPI_SYS_I2C5_CLK)>,
+				 <GPIOMUX(20, GPOUT_LOW,
+					      GPOEN_SYS_I2C5_DATA,
+					      GPI_SYS_I2C5_DATA)>;
+			bias-disable; /* external pull-up */
+			bootph-pre-ram;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	i2c6_pins: i2c6-0 {
+		i2c-pins {
+			pinmux = <GPIOMUX(16, GPOUT_LOW,
+					      GPOEN_SYS_I2C6_CLK,
+					      GPI_SYS_I2C6_CLK)>,
+				 <GPIOMUX(17, GPOUT_LOW,
+					      GPOEN_SYS_I2C6_DATA,
+					      GPI_SYS_I2C6_DATA)>;
+			bias-disable; /* external pull-up */
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	mmc0_pins: mmc0-0 {
+		mmc-pins {
+			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
+				 <PINMUX(PAD_SD0_CMD, 0)>,
+				 <PINMUX(PAD_SD0_DATA0, 0)>,
+				 <PINMUX(PAD_SD0_DATA1, 0)>,
+				 <PINMUX(PAD_SD0_DATA2, 0)>,
+				 <PINMUX(PAD_SD0_DATA3, 0)>,
+				 <PINMUX(PAD_SD0_DATA4, 0)>,
+				 <PINMUX(PAD_SD0_DATA5, 0)>,
+				 <PINMUX(PAD_SD0_DATA6, 0)>,
+				 <PINMUX(PAD_SD0_DATA7, 0)>;
+			bias-pull-up;
+			drive-strength = <12>;
+			input-enable;
+		};
+	};
+
+	mmc1_pins: mmc1-0 {
+		clk-pins {
+			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-pull-up;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		mmc-pins {
+			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+					     GPOEN_SYS_SDIO1_CMD,
+					     GPI_SYS_SDIO1_CMD)>,
+				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+					      GPOEN_SYS_SDIO1_DATA0,
+					      GPI_SYS_SDIO1_DATA0)>,
+				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+					      GPOEN_SYS_SDIO1_DATA1,
+					      GPI_SYS_SDIO1_DATA1)>,
+				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+					     GPOEN_SYS_SDIO1_DATA2,
+					     GPI_SYS_SDIO1_DATA2)>,
+				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+					     GPOEN_SYS_SDIO1_DATA3,
+					     GPI_SYS_SDIO1_DATA3)>;
+			bias-pull-up;
+			drive-strength = <12>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie0_pins: pcie0-0 {
+		clkreq-pins {
+			pinmux = <GPIOMUX(27, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_NONE)>;
+			bias-pull-down;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		wake-pins {
+			pinmux = <GPIOMUX(32, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_NONE)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_pins: pcie1-0 {
+		clkreq-pins {
+			pinmux = <GPIOMUX(29, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_NONE)>;
+			bias-pull-down;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		wake-pins {
+			pinmux = <GPIOMUX(21, GPOUT_LOW,
+				      GPOEN_DISABLE,
+					      GPI_NONE)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pwmdac_pins: pwmdac-0 {
+		pwmdac-pins {
+			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>,
+				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pwm_pins: pwm-0 {
+		pwm-pins {
+			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+					      GPOEN_SYS_PWM0_CHANNEL0,
+					      GPI_NONE)>,
+				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+					      GPOEN_SYS_PWM0_CHANNEL1,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	spi0_pins: spi0-0 {
+		mosi-pins {
+			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+
+		miso-pins {
+			pinmux = <GPIOMUX(53, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_SPI0_RXD)>;
+			bias-pull-up;
+			input-enable;
+			input-schmitt-enable;
+		};
+
+		sck-pins {
+			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
+					      GPOEN_ENABLE,
+					      GPI_SYS_SPI0_CLK)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+
+		ss-pins {
+			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
+					      GPOEN_ENABLE,
+					      GPI_SYS_SPI0_FSS)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+	};
+
+	uart0_pins: uart0-0 {
+		tx-pins {
+			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+					     GPOEN_ENABLE,
+					     GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		rx-pins {
+			pinmux = <GPIOMUX(6, GPOUT_LOW,
+					     GPOEN_DISABLE,
+					     GPI_SYS_UART0_RX)>;
+			bias-disable; /* external pull-up */
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+	};
+};
+
+&uart0 {
+	bootph-pre-ram;
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&U74_1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+	cpu-supply = <&vdd_cpu>;
+};
diff --git a/arch/riscv/boot/dts/starfive/jh711x.dtsi b/arch/riscv/boot/dts/starfive/jh711x.dtsi
index 6e56e9d20bb0..a380d3dabedd 100644
--- a/arch/riscv/boot/dts/starfive/jh711x.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh711x.dtsi
@@ -205,22 +205,6 @@ core4 {
 	cpu_opp: opp-table-0 {
 			compatible = "operating-points-v2";
 			opp-shared;
-			opp-375000000 {
-					opp-hz = /bits/ 64 <375000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-500000000 {
-					opp-hz = /bits/ 64 <500000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-750000000 {
-					opp-hz = /bits/ 64 <750000000>;
-					opp-microvolt = <800000>;
-			};
-			opp-1500000000 {
-					opp-hz = /bits/ 64 <1500000000>;
-					opp-microvolt = <1040000>;
-			};
 	};
 
 	thermal-zones {
-- 
2.43.2

Re: [PATCH v2 4/8] riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to it

[E Shattow]

On 11/7/25 01:55, Hal Feng wrote:
> Preparing to add JH7110S based board device trees, move the content of
> jh7110-common.dtsi to the new file jh711x-common.dtsi and move opp table
> to jh7110-common.dtsi.
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  .../boot/dts/starfive/jh7110-common.dtsi      | 665 +-----------------
>  .../boot/dts/starfive/jh711x-common.dtsi      | 664 +++++++++++++++++
>  arch/riscv/boot/dts/starfive/jh711x.dtsi      |  16 -
>  3 files changed, 678 insertions(+), 667 deletions(-)
>  create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index 809274625615..dd5805ef70a1 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -5,660 +5,23 @@
>   */
>  
>  /dts-v1/;
> -#include "jh711x.dtsi"
> -#include "jh7110-pinfunc.h"
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/leds/common.h>
> -#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
> +#include "jh711x-common.dtsi"
>  
> -/ {
> -	aliases {
> -		ethernet0 = &gmac0;
> -		i2c0 = &i2c0;
> -		i2c2 = &i2c2;
> -		i2c5 = &i2c5;
> -		i2c6 = &i2c6;
> -		mmc0 = &mmc0;
> -		mmc1 = &mmc1;
> -		serial0 = &uart0;
> +&cpu_opp {
> +	opp-375000000 {
> +		opp-hz = /bits/ 64 <375000000>;
> +		opp-microvolt = <800000>;
>  	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
> -	memory@40000000 {
> -		device_type = "memory";
> -		reg = <0x0 0x40000000 0x1 0x0>;
> -		bootph-pre-ram;
> -	};
> -
> -	gpio-restart {
> -		compatible = "gpio-restart";
> -		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> -		priority = <224>;
> -	};
> -
> -	leds {
> -		compatible = "gpio-leds";
> -
> -		led_status_power: led-0 {
> -			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
> -		};
> -	};
> -
> -	pwmdac_codec: audio-codec {
> -		compatible = "linux,spdif-dit";
> -		#sound-dai-cells = <0>;
> -	};
> -
> -	sound {
> -		compatible = "simple-audio-card";
> -		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		simple-audio-card,dai-link@0 {
> -			reg = <0>;
> -			format = "left_j";
> -			bitclock-master = <&sndcpu0>;
> -			frame-master = <&sndcpu0>;
> -
> -			sndcpu0: cpu {
> -				sound-dai = <&pwmdac>;
> -			};
> -
> -			codec {
> -				sound-dai = <&pwmdac_codec>;
> -			};
> -		};
> -	};
> -};
> -
> -&cpus {
> -	timebase-frequency = <4000000>;
> -};
> -
> -&dvp_clk {
> -	clock-frequency = <74250000>;
> -};
> -
> -&gmac0_rgmii_rxin {
> -	clock-frequency = <125000000>;
> -};
> -
> -&gmac0_rmii_refin {
> -	clock-frequency = <50000000>;
> -};
> -
> -&gmac1_rgmii_rxin {
> -	clock-frequency = <125000000>;
> -};
> -
> -&gmac1_rmii_refin {
> -	clock-frequency = <50000000>;
> -};
> -
> -&hdmitx0_pixelclk {
> -	clock-frequency = <297000000>;
> -};
> -
> -&i2srx_bclk_ext {
> -	clock-frequency = <12288000>;
> -};
> -
> -&i2srx_lrck_ext {
> -	clock-frequency = <192000>;
> -};
> -
> -&i2stx_bclk_ext {
> -	clock-frequency = <12288000>;
> -};
> -
> -&i2stx_lrck_ext {
> -	clock-frequency = <192000>;
> -};
> -
> -&mclk_ext {
> -	clock-frequency = <12288000>;
> -};
> -
> -&osc {
> -	clock-frequency = <24000000>;
> -};
> -
> -&rtc_osc {
> -	clock-frequency = <32768>;
> -};
> -
> -&tdm_ext {
> -	clock-frequency = <49152000>;
> -};
> -
> -&camss {
> -	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
> -			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
> -	assigned-clock-rates = <49500000>, <198000000>;
> -
> -	ports {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		port@0 {
> -			reg = <0>;
> -		};
> -
> -		port@1 {
> -			reg = <1>;
> -
> -			camss_from_csi2rx: endpoint {
> -				remote-endpoint = <&csi2rx_to_camss>;
> -			};
> -		};
> +	opp-500000000 {
> +		opp-hz = /bits/ 64 <500000000>;
> +		opp-microvolt = <800000>;
>  	};
> -};
> -
> -&csi2rx {
> -	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
> -	assigned-clock-rates = <297000000>;
> -
> -	ports {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		port@0 {
> -			reg = <0>;
> -
> -			/* remote MIPI sensor endpoint */
> -		};
> -
> -		port@1 {
> -			reg = <1>;
> -
> -			csi2rx_to_camss: endpoint {
> -				remote-endpoint = <&camss_from_csi2rx>;
> -			};
> -		};
> +	opp-750000000 {
> +		opp-hz = /bits/ 64 <750000000>;
> +		opp-microvolt = <800000>;
>  	};
> -};
> -
> -&gmac0 {
> -	phy-handle = <&phy0>;
> -	phy-mode = "rgmii-id";
> -
> -	mdio {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		compatible = "snps,dwmac-mdio";
> -
> -		phy0: ethernet-phy@0 {
> -			reg = <0>;
> -		};
> +	opp-1500000000 {
> +		opp-hz = /bits/ 64 <1500000000>;
> +		opp-microvolt = <1040000>;
>  	};
>  };
> -
> -&i2c0 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c0_pins>;
> -};
> -
> -&i2c2 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c2_pins>;
> -	status = "okay";
> -};
> -
> -&i2c5 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c5_pins>;
> -	status = "okay";
> -
> -	axp15060: pmic@36 {
> -		compatible = "x-powers,axp15060";
> -		reg = <0x36>;
> -		interrupt-controller;
> -		#interrupt-cells = <1>;
> -
> -		regulators {
> -			vcc_3v3: dcdc1 {
> -				regulator-boot-on;
> -				regulator-always-on;
> -				regulator-min-microvolt = <3300000>;
> -				regulator-max-microvolt = <3300000>;
> -				regulator-name = "vcc_3v3";
> -			};
> -
> -			vdd_cpu: dcdc2 {
> -				regulator-always-on;
> -				regulator-min-microvolt = <500000>;
> -				regulator-max-microvolt = <1540000>;
> -				regulator-name = "vdd_cpu";
> -			};
> -
> -			emmc_vdd: aldo4 {
> -				regulator-boot-on;
> -				regulator-always-on;
> -				regulator-min-microvolt = <1800000>;
> -				regulator-max-microvolt = <3300000>;
> -				regulator-name = "emmc_vdd";
> -			};
> -		};
> -	};
> -
> -	eeprom@50 {
> -		compatible = "atmel,24c04";
> -		reg = <0x50>;
> -		bootph-pre-ram;
> -		pagesize = <16>;
> -	};
> -};
> -
> -&i2c6 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c6_pins>;
> -	status = "okay";
> -};
> -
> -&mmc0 {
> -	max-frequency = <100000000>;
> -	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> -	assigned-clock-rates = <50000000>;
> -	bus-width = <8>;
> -	bootph-pre-ram;
> -	cap-mmc-highspeed;
> -	mmc-ddr-1_8v;
> -	mmc-hs200-1_8v;
> -	cap-mmc-hw-reset;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc0_pins>;
> -	vmmc-supply = <&vcc_3v3>;
> -	vqmmc-supply = <&emmc_vdd>;
> -	status = "okay";
> -};
> -
> -&mmc1 {
> -	max-frequency = <100000000>;
> -	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> -	assigned-clock-rates = <50000000>;
> -	bus-width = <4>;
> -	bootph-pre-ram;
> -	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> -	disable-wp;
> -	cap-sd-highspeed;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc1_pins>;
> -	status = "okay";
> -};
> -
> -&pcie0 {
> -	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> -	phys = <&pciephy0>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pcie0_pins>;
> -};
> -
> -&pcie1 {
> -	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> -	phys = <&pciephy1>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pcie1_pins>;
> -};
> -
> -&pwmdac {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pwmdac_pins>;
> -};
> -
> -&qspi {
> -	#address-cells = <1>;
> -	#size-cells = <0>;
> -	status = "okay";
> -
> -	nor_flash: flash@0 {
> -		compatible = "jedec,spi-nor";
> -		reg = <0>;
> -		bootph-pre-ram;
> -		cdns,read-delay = <2>;
> -		spi-max-frequency = <100000000>;
> -		cdns,tshsl-ns = <1>;
> -		cdns,tsd2d-ns = <1>;
> -		cdns,tchsh-ns = <1>;
> -		cdns,tslch-ns = <1>;
> -
> -		partitions {
> -			compatible = "fixed-partitions";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -
> -			spl@0 {
> -				reg = <0x0 0xf0000>;
> -			};
> -			uboot-env@f0000 {
> -				reg = <0xf0000 0x10000>;
> -			};
> -			uboot@100000 {
> -				reg = <0x100000 0xf00000>;
> -			};
> -		};
> -	};
> -};
> -
> -&pwm {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pwm_pins>;
> -};
> -
> -&spi0 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&spi0_pins>;
> -};
> -
> -&syscrg {
> -	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> -			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> -			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> -			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
> -			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
> -			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
> -	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> -				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> -				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> -				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> -	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
> -};
> -
> -&sysgpio {
> -	i2c0_pins: i2c0-0 {
> -		i2c-pins {
> -			pinmux = <GPIOMUX(57, GPOUT_LOW,
> -					      GPOEN_SYS_I2C0_CLK,
> -					      GPI_SYS_I2C0_CLK)>,
> -				 <GPIOMUX(58, GPOUT_LOW,
> -					      GPOEN_SYS_I2C0_DATA,
> -					      GPI_SYS_I2C0_DATA)>;
> -			bias-disable; /* external pull-up */
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	i2c2_pins: i2c2-0 {
> -		i2c-pins {
> -			pinmux = <GPIOMUX(3, GPOUT_LOW,
> -					     GPOEN_SYS_I2C2_CLK,
> -					     GPI_SYS_I2C2_CLK)>,
> -				 <GPIOMUX(2, GPOUT_LOW,
> -					     GPOEN_SYS_I2C2_DATA,
> -					     GPI_SYS_I2C2_DATA)>;
> -			bias-disable; /* external pull-up */
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	i2c5_pins: i2c5-0 {
> -		bootph-pre-ram;
> -
> -		i2c-pins {
> -			pinmux = <GPIOMUX(19, GPOUT_LOW,
> -					      GPOEN_SYS_I2C5_CLK,
> -					      GPI_SYS_I2C5_CLK)>,
> -				 <GPIOMUX(20, GPOUT_LOW,
> -					      GPOEN_SYS_I2C5_DATA,
> -					      GPI_SYS_I2C5_DATA)>;
> -			bias-disable; /* external pull-up */
> -			bootph-pre-ram;
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	i2c6_pins: i2c6-0 {
> -		i2c-pins {
> -			pinmux = <GPIOMUX(16, GPOUT_LOW,
> -					      GPOEN_SYS_I2C6_CLK,
> -					      GPI_SYS_I2C6_CLK)>,
> -				 <GPIOMUX(17, GPOUT_LOW,
> -					      GPOEN_SYS_I2C6_DATA,
> -					      GPI_SYS_I2C6_DATA)>;
> -			bias-disable; /* external pull-up */
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	mmc0_pins: mmc0-0 {
> -		mmc-pins {
> -			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
> -				 <PINMUX(PAD_SD0_CMD, 0)>,
> -				 <PINMUX(PAD_SD0_DATA0, 0)>,
> -				 <PINMUX(PAD_SD0_DATA1, 0)>,
> -				 <PINMUX(PAD_SD0_DATA2, 0)>,
> -				 <PINMUX(PAD_SD0_DATA3, 0)>,
> -				 <PINMUX(PAD_SD0_DATA4, 0)>,
> -				 <PINMUX(PAD_SD0_DATA5, 0)>,
> -				 <PINMUX(PAD_SD0_DATA6, 0)>,
> -				 <PINMUX(PAD_SD0_DATA7, 0)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-enable;
> -		};
> -	};
> -
> -	mmc1_pins: mmc1-0 {
> -		clk-pins {
> -			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		mmc-pins {
> -			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
> -					     GPOEN_SYS_SDIO1_CMD,
> -					     GPI_SYS_SDIO1_CMD)>,
> -				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
> -					      GPOEN_SYS_SDIO1_DATA0,
> -					      GPI_SYS_SDIO1_DATA0)>,
> -				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
> -					      GPOEN_SYS_SDIO1_DATA1,
> -					      GPI_SYS_SDIO1_DATA1)>,
> -				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
> -					     GPOEN_SYS_SDIO1_DATA2,
> -					     GPI_SYS_SDIO1_DATA2)>,
> -				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
> -					     GPOEN_SYS_SDIO1_DATA3,
> -					     GPI_SYS_SDIO1_DATA3)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-enable;
> -			input-schmitt-enable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pcie0_pins: pcie0-0 {
> -		clkreq-pins {
> -			pinmux = <GPIOMUX(27, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-down;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		wake-pins {
> -			pinmux = <GPIOMUX(32, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pcie1_pins: pcie1-0 {
> -		clkreq-pins {
> -			pinmux = <GPIOMUX(29, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-down;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		wake-pins {
> -			pinmux = <GPIOMUX(21, GPOUT_LOW,
> -				      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pwmdac_pins: pwmdac-0 {
> -		pwmdac-pins {
> -			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>,
> -				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-disable;
> -			drive-strength = <2>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pwm_pins: pwm-0 {
> -		pwm-pins {
> -			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
> -					      GPOEN_SYS_PWM0_CHANNEL0,
> -					      GPI_NONE)>,
> -				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
> -					      GPOEN_SYS_PWM0_CHANNEL1,
> -					      GPI_NONE)>;
> -			bias-disable;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	spi0_pins: spi0-0 {
> -		mosi-pins {
> -			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-disable;
> -			input-disable;
> -			input-schmitt-disable;
> -		};
> -
> -		miso-pins {
> -			pinmux = <GPIOMUX(53, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_SYS_SPI0_RXD)>;
> -			bias-pull-up;
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -
> -		sck-pins {
> -			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
> -					      GPOEN_ENABLE,
> -					      GPI_SYS_SPI0_CLK)>;
> -			bias-disable;
> -			input-disable;
> -			input-schmitt-disable;
> -		};
> -
> -		ss-pins {
> -			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
> -					      GPOEN_ENABLE,
> -					      GPI_SYS_SPI0_FSS)>;
> -			bias-disable;
> -			input-disable;
> -			input-schmitt-disable;
> -		};
> -	};
> -
> -	uart0_pins: uart0-0 {
> -		tx-pins {
> -			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> -					     GPOEN_ENABLE,
> -					     GPI_NONE)>;
> -			bias-disable;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		rx-pins {
> -			pinmux = <GPIOMUX(6, GPOUT_LOW,
> -					     GPOEN_DISABLE,
> -					     GPI_SYS_UART0_RX)>;
> -			bias-disable; /* external pull-up */
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-enable;
> -			slew-rate = <0>;
> -		};
> -	};
> -};
> -
> -&uart0 {
> -	bootph-pre-ram;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&uart0_pins>;
> -	status = "okay";
> -};
> -
> -&U74_1 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_2 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_3 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_4 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> diff --git a/arch/riscv/boot/dts/starfive/jh711x-common.dtsi b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> new file mode 100644
> index 000000000000..809274625615
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> @@ -0,0 +1,664 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh711x.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
> +
> +/ {
> +	aliases {
> +		ethernet0 = &gmac0;
> +		i2c0 = &i2c0;
> +		i2c2 = &i2c2;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		mmc0 = &mmc0;
> +		mmc1 = &mmc1;
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0x1 0x0>;
> +		bootph-pre-ram;
> +	};
> +
> +	gpio-restart {
> +		compatible = "gpio-restart";
> +		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> +		priority = <224>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led_status_power: led-0 {
> +			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	pwmdac_codec: audio-codec {
> +		compatible = "linux,spdif-dit";
> +		#sound-dai-cells = <0>;
> +	};
> +
> +	sound {
> +		compatible = "simple-audio-card";
> +		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		simple-audio-card,dai-link@0 {
> +			reg = <0>;
> +			format = "left_j";
> +			bitclock-master = <&sndcpu0>;
> +			frame-master = <&sndcpu0>;
> +
> +			sndcpu0: cpu {
> +				sound-dai = <&pwmdac>;
> +			};
> +
> +			codec {
> +				sound-dai = <&pwmdac_codec>;
> +			};
> +		};
> +	};
> +};
> +
> +&cpus {
> +	timebase-frequency = <4000000>;
> +};
> +
> +&dvp_clk {
> +	clock-frequency = <74250000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> +	clock-frequency = <125000000>;
> +};
> +
> +&gmac0_rmii_refin {
> +	clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> +	clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> +	clock-frequency = <50000000>;
> +};
> +
> +&hdmitx0_pixelclk {
> +	clock-frequency = <297000000>;
> +};
> +
> +&i2srx_bclk_ext {
> +	clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> +	clock-frequency = <192000>;
> +};
> +
> +&i2stx_bclk_ext {
> +	clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> +	clock-frequency = <192000>;
> +};
> +
> +&mclk_ext {
> +	clock-frequency = <12288000>;
> +};
> +
> +&osc {
> +	clock-frequency = <24000000>;
> +};
> +
> +&rtc_osc {
> +	clock-frequency = <32768>;
> +};
> +
> +&tdm_ext {
> +	clock-frequency = <49152000>;
> +};
> +
> +&camss {
> +	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
> +			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
> +	assigned-clock-rates = <49500000>, <198000000>;
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port@0 {
> +			reg = <0>;
> +		};
> +
> +		port@1 {
> +			reg = <1>;
> +
> +			camss_from_csi2rx: endpoint {
> +				remote-endpoint = <&csi2rx_to_camss>;
> +			};
> +		};
> +	};
> +};
> +
> +&csi2rx {
> +	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
> +	assigned-clock-rates = <297000000>;
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port@0 {
> +			reg = <0>;
> +
> +			/* remote MIPI sensor endpoint */
> +		};
> +
> +		port@1 {
> +			reg = <1>;
> +
> +			csi2rx_to_camss: endpoint {
> +				remote-endpoint = <&camss_from_csi2rx>;
> +			};
> +		};
> +	};
> +};
> +
> +&gmac0 {
> +	phy-handle = <&phy0>;
> +	phy-mode = "rgmii-id";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";
> +
> +		phy0: ethernet-phy@0 {
> +			reg = <0>;
> +		};
> +	};
> +};
> +
> +&i2c0 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c0_pins>;
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c2_pins>;
> +	status = "okay";
> +};
> +
> +&i2c5 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c5_pins>;
> +	status = "okay";
> +
> +	axp15060: pmic@36 {
> +		compatible = "x-powers,axp15060";
> +		reg = <0x36>;
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +
> +		regulators {
> +			vcc_3v3: dcdc1 {
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-name = "vcc_3v3";
> +			};
> +
> +			vdd_cpu: dcdc2 {
> +				regulator-always-on;
> +				regulator-min-microvolt = <500000>;
> +				regulator-max-microvolt = <1540000>;
> +				regulator-name = "vdd_cpu";
> +			};
> +
> +			emmc_vdd: aldo4 {
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-name = "emmc_vdd";
> +			};
> +		};
> +	};
> +
> +	eeprom@50 {
> +		compatible = "atmel,24c04";
> +		reg = <0x50>;
> +		bootph-pre-ram;
> +		pagesize = <16>;
> +	};
> +};
> +
> +&i2c6 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c6_pins>;
> +	status = "okay";
> +};
> +
> +&mmc0 {
> +	max-frequency = <100000000>;
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> +	assigned-clock-rates = <50000000>;
> +	bus-width = <8>;
> +	bootph-pre-ram;
> +	cap-mmc-highspeed;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	cap-mmc-hw-reset;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc0_pins>;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
> +	status = "okay";
> +};
> +
> +&mmc1 {
> +	max-frequency = <100000000>;
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> +	assigned-clock-rates = <50000000>;
> +	bus-width = <4>;
> +	bootph-pre-ram;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	cap-sd-highspeed;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc1_pins>;
> +	status = "okay";
> +};
> +
> +&pcie0 {
> +	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> +	phys = <&pciephy0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie0_pins>;
> +};
> +
> +&pcie1 {
> +	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> +	phys = <&pciephy1>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie1_pins>;
> +};
> +
> +&pwmdac {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pwmdac_pins>;
> +};
> +
> +&qspi {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	nor_flash: flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		bootph-pre-ram;
> +		cdns,read-delay = <2>;
> +		spi-max-frequency = <100000000>;
> +		cdns,tshsl-ns = <1>;
> +		cdns,tsd2d-ns = <1>;
> +		cdns,tchsh-ns = <1>;
> +		cdns,tslch-ns = <1>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			spl@0 {
> +				reg = <0x0 0xf0000>;
> +			};
> +			uboot-env@f0000 {
> +				reg = <0xf0000 0x10000>;
> +			};
> +			uboot@100000 {
> +				reg = <0x100000 0xf00000>;
> +			};
> +		};
> +	};
> +};
> +
> +&pwm {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pwm_pins>;
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi0_pins>;
> +};
> +
> +&syscrg {
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
> +			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
> +			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
> +	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> +				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
> +};
> +
> +&sysgpio {
> +	i2c0_pins: i2c0-0 {
> +		i2c-pins {
> +			pinmux = <GPIOMUX(57, GPOUT_LOW,
> +					      GPOEN_SYS_I2C0_CLK,
> +					      GPI_SYS_I2C0_CLK)>,
> +				 <GPIOMUX(58, GPOUT_LOW,
> +					      GPOEN_SYS_I2C0_DATA,
> +					      GPI_SYS_I2C0_DATA)>;
> +			bias-disable; /* external pull-up */
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	i2c2_pins: i2c2-0 {
> +		i2c-pins {
> +			pinmux = <GPIOMUX(3, GPOUT_LOW,
> +					     GPOEN_SYS_I2C2_CLK,
> +					     GPI_SYS_I2C2_CLK)>,
> +				 <GPIOMUX(2, GPOUT_LOW,
> +					     GPOEN_SYS_I2C2_DATA,
> +					     GPI_SYS_I2C2_DATA)>;
> +			bias-disable; /* external pull-up */
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	i2c5_pins: i2c5-0 {
> +		bootph-pre-ram;
> +
> +		i2c-pins {
> +			pinmux = <GPIOMUX(19, GPOUT_LOW,
> +					      GPOEN_SYS_I2C5_CLK,
> +					      GPI_SYS_I2C5_CLK)>,
> +				 <GPIOMUX(20, GPOUT_LOW,
> +					      GPOEN_SYS_I2C5_DATA,
> +					      GPI_SYS_I2C5_DATA)>;
> +			bias-disable; /* external pull-up */
> +			bootph-pre-ram;
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	i2c6_pins: i2c6-0 {
> +		i2c-pins {
> +			pinmux = <GPIOMUX(16, GPOUT_LOW,
> +					      GPOEN_SYS_I2C6_CLK,
> +					      GPI_SYS_I2C6_CLK)>,
> +				 <GPIOMUX(17, GPOUT_LOW,
> +					      GPOEN_SYS_I2C6_DATA,
> +					      GPI_SYS_I2C6_DATA)>;
> +			bias-disable; /* external pull-up */
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	mmc0_pins: mmc0-0 {
> +		mmc-pins {
> +			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
> +				 <PINMUX(PAD_SD0_CMD, 0)>,
> +				 <PINMUX(PAD_SD0_DATA0, 0)>,
> +				 <PINMUX(PAD_SD0_DATA1, 0)>,
> +				 <PINMUX(PAD_SD0_DATA2, 0)>,
> +				 <PINMUX(PAD_SD0_DATA3, 0)>,
> +				 <PINMUX(PAD_SD0_DATA4, 0)>,
> +				 <PINMUX(PAD_SD0_DATA5, 0)>,
> +				 <PINMUX(PAD_SD0_DATA6, 0)>,
> +				 <PINMUX(PAD_SD0_DATA7, 0)>;
> +			bias-pull-up;
> +			drive-strength = <12>;
> +			input-enable;
> +		};
> +	};
> +
> +	mmc1_pins: mmc1-0 {
> +		clk-pins {
> +			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			bias-pull-up;
> +			drive-strength = <12>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		mmc-pins {
> +			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
> +					     GPOEN_SYS_SDIO1_CMD,
> +					     GPI_SYS_SDIO1_CMD)>,
> +				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
> +					      GPOEN_SYS_SDIO1_DATA0,
> +					      GPI_SYS_SDIO1_DATA0)>,
> +				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
> +					      GPOEN_SYS_SDIO1_DATA1,
> +					      GPI_SYS_SDIO1_DATA1)>,
> +				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
> +					     GPOEN_SYS_SDIO1_DATA2,
> +					     GPI_SYS_SDIO1_DATA2)>,
> +				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
> +					     GPOEN_SYS_SDIO1_DATA3,
> +					     GPI_SYS_SDIO1_DATA3)>;
> +			bias-pull-up;
> +			drive-strength = <12>;
> +			input-enable;
> +			input-schmitt-enable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pcie0_pins: pcie0-0 {
> +		clkreq-pins {
> +			pinmux = <GPIOMUX(27, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-down;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		wake-pins {
> +			pinmux = <GPIOMUX(32, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-up;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pcie1_pins: pcie1-0 {
> +		clkreq-pins {
> +			pinmux = <GPIOMUX(29, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-down;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		wake-pins {
> +			pinmux = <GPIOMUX(21, GPOUT_LOW,
> +				      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-up;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pwmdac_pins: pwmdac-0 {
> +		pwmdac-pins {
> +			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>,
> +				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <2>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pwm_pins: pwm-0 {
> +		pwm-pins {
> +			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
> +					      GPOEN_SYS_PWM0_CHANNEL0,
> +					      GPI_NONE)>,
> +				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
> +					      GPOEN_SYS_PWM0_CHANNEL1,
> +					      GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <12>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	spi0_pins: spi0-0 {
> +		mosi-pins {
> +			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			bias-disable;
> +			input-disable;
> +			input-schmitt-disable;
> +		};
> +
> +		miso-pins {
> +			pinmux = <GPIOMUX(53, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_SYS_SPI0_RXD)>;
> +			bias-pull-up;
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +
> +		sck-pins {
> +			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
> +					      GPOEN_ENABLE,
> +					      GPI_SYS_SPI0_CLK)>;
> +			bias-disable;
> +			input-disable;
> +			input-schmitt-disable;
> +		};
> +
> +		ss-pins {
> +			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
> +					      GPOEN_ENABLE,
> +					      GPI_SYS_SPI0_FSS)>;
> +			bias-disable;
> +			input-disable;
> +			input-schmitt-disable;
> +		};
> +	};
> +
> +	uart0_pins: uart0-0 {
> +		tx-pins {
> +			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> +					     GPOEN_ENABLE,
> +					     GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <12>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		rx-pins {
> +			pinmux = <GPIOMUX(6, GPOUT_LOW,
> +					     GPOEN_DISABLE,
> +					     GPI_SYS_UART0_RX)>;
> +			bias-disable; /* external pull-up */
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-enable;
> +			slew-rate = <0>;
> +		};
> +	};
> +};
> +
> +&uart0 {
> +	bootph-pre-ram;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pins>;
> +	status = "okay";
> +};
> +
> +&U74_1 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_2 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_3 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_4 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh711x.dtsi b/arch/riscv/boot/dts/starfive/jh711x.dtsi
> index 6e56e9d20bb0..a380d3dabedd 100644
> --- a/arch/riscv/boot/dts/starfive/jh711x.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh711x.dtsi
> @@ -205,22 +205,6 @@ core4 {
>  	cpu_opp: opp-table-0 {
>  			compatible = "operating-points-v2";
>  			opp-shared;
> -			opp-375000000 {
> -					opp-hz = /bits/ 64 <375000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-500000000 {
> -					opp-hz = /bits/ 64 <500000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-750000000 {
> -					opp-hz = /bits/ 64 <750000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-1500000000 {
> -					opp-hz = /bits/ 64 <1500000000>;
> -					opp-microvolt = <1040000>;
> -			};
>  	};
>  
>  	thermal-zones {

Reviewed-by: E Shattow <e@freeshell.de>

Re: [PATCH v2 4/8] riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to it

[Heinrich Schuchardt]

On 11/7/25 10:55, Hal Feng wrote:
> Preparing to add JH7110S based board device trees, move the content of
> jh7110-common.dtsi to the new file jh711x-common.dtsi and move opp table
> to jh7110-common.dtsi.
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>   .../boot/dts/starfive/jh7110-common.dtsi      | 665 +-----------------
>   .../boot/dts/starfive/jh711x-common.dtsi      | 664 +++++++++++++++++
>   arch/riscv/boot/dts/starfive/jh711x.dtsi      |  16 -
>   3 files changed, 678 insertions(+), 667 deletions(-)
>   create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index 809274625615..dd5805ef70a1 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -5,660 +5,23 @@
>    */
>   
>   /dts-v1/;
> -#include "jh711x.dtsi"
> -#include "jh7110-pinfunc.h"
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/leds/common.h>
> -#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
> +#include "jh711x-common.dtsi"
>   
> -/ {
> -	aliases {
> -		ethernet0 = &gmac0;
> -		i2c0 = &i2c0;
> -		i2c2 = &i2c2;
> -		i2c5 = &i2c5;
> -		i2c6 = &i2c6;
> -		mmc0 = &mmc0;
> -		mmc1 = &mmc1;
> -		serial0 = &uart0;
> +&cpu_opp {
> +	opp-375000000 {
> +		opp-hz = /bits/ 64 <375000000>;
> +		opp-microvolt = <800000>;
>   	};
> -
> -	chosen {
> -		stdout-path = "serial0:115200n8";
> -	};
> -
> -	memory@40000000 {
> -		device_type = "memory";
> -		reg = <0x0 0x40000000 0x1 0x0>;
> -		bootph-pre-ram;
> -	};
> -
> -	gpio-restart {
> -		compatible = "gpio-restart";
> -		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> -		priority = <224>;
> -	};
> -
> -	leds {
> -		compatible = "gpio-leds";
> -
> -		led_status_power: led-0 {
> -			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
> -		};
> -	};
> -
> -	pwmdac_codec: audio-codec {
> -		compatible = "linux,spdif-dit";
> -		#sound-dai-cells = <0>;
> -	};
> -
> -	sound {
> -		compatible = "simple-audio-card";
> -		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		simple-audio-card,dai-link@0 {
> -			reg = <0>;
> -			format = "left_j";
> -			bitclock-master = <&sndcpu0>;
> -			frame-master = <&sndcpu0>;
> -
> -			sndcpu0: cpu {
> -				sound-dai = <&pwmdac>;
> -			};
> -
> -			codec {
> -				sound-dai = <&pwmdac_codec>;
> -			};
> -		};
> -	};
> -};
> -
> -&cpus {
> -	timebase-frequency = <4000000>;
> -};
> -
> -&dvp_clk {
> -	clock-frequency = <74250000>;
> -};
> -
> -&gmac0_rgmii_rxin {
> -	clock-frequency = <125000000>;
> -};
> -
> -&gmac0_rmii_refin {
> -	clock-frequency = <50000000>;
> -};
> -
> -&gmac1_rgmii_rxin {
> -	clock-frequency = <125000000>;
> -};
> -
> -&gmac1_rmii_refin {
> -	clock-frequency = <50000000>;
> -};
> -
> -&hdmitx0_pixelclk {
> -	clock-frequency = <297000000>;
> -};
> -
> -&i2srx_bclk_ext {
> -	clock-frequency = <12288000>;
> -};
> -
> -&i2srx_lrck_ext {
> -	clock-frequency = <192000>;
> -};
> -
> -&i2stx_bclk_ext {
> -	clock-frequency = <12288000>;
> -};
> -
> -&i2stx_lrck_ext {
> -	clock-frequency = <192000>;
> -};
> -
> -&mclk_ext {
> -	clock-frequency = <12288000>;
> -};
> -
> -&osc {
> -	clock-frequency = <24000000>;
> -};
> -
> -&rtc_osc {
> -	clock-frequency = <32768>;
> -};
> -
> -&tdm_ext {
> -	clock-frequency = <49152000>;
> -};
> -
> -&camss {
> -	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
> -			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
> -	assigned-clock-rates = <49500000>, <198000000>;
> -
> -	ports {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		port@0 {
> -			reg = <0>;
> -		};
> -
> -		port@1 {
> -			reg = <1>;
> -
> -			camss_from_csi2rx: endpoint {
> -				remote-endpoint = <&csi2rx_to_camss>;
> -			};
> -		};
> +	opp-500000000 {
> +		opp-hz = /bits/ 64 <500000000>;
> +		opp-microvolt = <800000>;
>   	};
> -};
> -
> -&csi2rx {
> -	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
> -	assigned-clock-rates = <297000000>;
> -
> -	ports {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -
> -		port@0 {
> -			reg = <0>;
> -
> -			/* remote MIPI sensor endpoint */
> -		};
> -
> -		port@1 {
> -			reg = <1>;
> -
> -			csi2rx_to_camss: endpoint {
> -				remote-endpoint = <&camss_from_csi2rx>;
> -			};
> -		};
> +	opp-750000000 {
> +		opp-hz = /bits/ 64 <750000000>;
> +		opp-microvolt = <800000>;
>   	};
> -};
> -
> -&gmac0 {
> -	phy-handle = <&phy0>;
> -	phy-mode = "rgmii-id";
> -
> -	mdio {
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		compatible = "snps,dwmac-mdio";
> -
> -		phy0: ethernet-phy@0 {
> -			reg = <0>;
> -		};
> +	opp-1500000000 {
> +		opp-hz = /bits/ 64 <1500000000>;
> +		opp-microvolt = <1040000>;
>   	};
>   };
> -
> -&i2c0 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c0_pins>;
> -};
> -
> -&i2c2 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c2_pins>;
> -	status = "okay";
> -};
> -
> -&i2c5 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c5_pins>;
> -	status = "okay";
> -
> -	axp15060: pmic@36 {
> -		compatible = "x-powers,axp15060";
> -		reg = <0x36>;
> -		interrupt-controller;
> -		#interrupt-cells = <1>;
> -
> -		regulators {
> -			vcc_3v3: dcdc1 {
> -				regulator-boot-on;
> -				regulator-always-on;
> -				regulator-min-microvolt = <3300000>;
> -				regulator-max-microvolt = <3300000>;
> -				regulator-name = "vcc_3v3";
> -			};
> -
> -			vdd_cpu: dcdc2 {
> -				regulator-always-on;
> -				regulator-min-microvolt = <500000>;
> -				regulator-max-microvolt = <1540000>;
> -				regulator-name = "vdd_cpu";
> -			};
> -
> -			emmc_vdd: aldo4 {
> -				regulator-boot-on;
> -				regulator-always-on;
> -				regulator-min-microvolt = <1800000>;
> -				regulator-max-microvolt = <3300000>;
> -				regulator-name = "emmc_vdd";
> -			};
> -		};
> -	};
> -
> -	eeprom@50 {
> -		compatible = "atmel,24c04";
> -		reg = <0x50>;
> -		bootph-pre-ram;
> -		pagesize = <16>;
> -	};
> -};
> -
> -&i2c6 {
> -	clock-frequency = <100000>;
> -	i2c-sda-hold-time-ns = <300>;
> -	i2c-sda-falling-time-ns = <510>;
> -	i2c-scl-falling-time-ns = <510>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&i2c6_pins>;
> -	status = "okay";
> -};
> -
> -&mmc0 {
> -	max-frequency = <100000000>;
> -	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> -	assigned-clock-rates = <50000000>;
> -	bus-width = <8>;
> -	bootph-pre-ram;
> -	cap-mmc-highspeed;
> -	mmc-ddr-1_8v;
> -	mmc-hs200-1_8v;
> -	cap-mmc-hw-reset;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc0_pins>;
> -	vmmc-supply = <&vcc_3v3>;
> -	vqmmc-supply = <&emmc_vdd>;
> -	status = "okay";
> -};
> -
> -&mmc1 {
> -	max-frequency = <100000000>;
> -	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> -	assigned-clock-rates = <50000000>;
> -	bus-width = <4>;
> -	bootph-pre-ram;
> -	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> -	disable-wp;
> -	cap-sd-highspeed;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc1_pins>;
> -	status = "okay";
> -};
> -
> -&pcie0 {
> -	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> -	phys = <&pciephy0>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pcie0_pins>;
> -};
> -
> -&pcie1 {
> -	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> -	phys = <&pciephy1>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pcie1_pins>;
> -};
> -
> -&pwmdac {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pwmdac_pins>;
> -};
> -
> -&qspi {
> -	#address-cells = <1>;
> -	#size-cells = <0>;
> -	status = "okay";
> -
> -	nor_flash: flash@0 {
> -		compatible = "jedec,spi-nor";
> -		reg = <0>;
> -		bootph-pre-ram;
> -		cdns,read-delay = <2>;
> -		spi-max-frequency = <100000000>;
> -		cdns,tshsl-ns = <1>;
> -		cdns,tsd2d-ns = <1>;
> -		cdns,tchsh-ns = <1>;
> -		cdns,tslch-ns = <1>;
> -
> -		partitions {
> -			compatible = "fixed-partitions";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -
> -			spl@0 {
> -				reg = <0x0 0xf0000>;
> -			};
> -			uboot-env@f0000 {
> -				reg = <0xf0000 0x10000>;
> -			};
> -			uboot@100000 {
> -				reg = <0x100000 0xf00000>;
> -			};
> -		};
> -	};
> -};
> -
> -&pwm {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pwm_pins>;
> -};
> -
> -&spi0 {
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&spi0_pins>;
> -};
> -
> -&syscrg {
> -	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> -			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> -			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> -			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
> -			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
> -			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
> -	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> -				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> -				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> -				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> -	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
> -};
> -
> -&sysgpio {
> -	i2c0_pins: i2c0-0 {
> -		i2c-pins {
> -			pinmux = <GPIOMUX(57, GPOUT_LOW,
> -					      GPOEN_SYS_I2C0_CLK,
> -					      GPI_SYS_I2C0_CLK)>,
> -				 <GPIOMUX(58, GPOUT_LOW,
> -					      GPOEN_SYS_I2C0_DATA,
> -					      GPI_SYS_I2C0_DATA)>;
> -			bias-disable; /* external pull-up */
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	i2c2_pins: i2c2-0 {
> -		i2c-pins {
> -			pinmux = <GPIOMUX(3, GPOUT_LOW,
> -					     GPOEN_SYS_I2C2_CLK,
> -					     GPI_SYS_I2C2_CLK)>,
> -				 <GPIOMUX(2, GPOUT_LOW,
> -					     GPOEN_SYS_I2C2_DATA,
> -					     GPI_SYS_I2C2_DATA)>;
> -			bias-disable; /* external pull-up */
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	i2c5_pins: i2c5-0 {
> -		bootph-pre-ram;
> -
> -		i2c-pins {
> -			pinmux = <GPIOMUX(19, GPOUT_LOW,
> -					      GPOEN_SYS_I2C5_CLK,
> -					      GPI_SYS_I2C5_CLK)>,
> -				 <GPIOMUX(20, GPOUT_LOW,
> -					      GPOEN_SYS_I2C5_DATA,
> -					      GPI_SYS_I2C5_DATA)>;
> -			bias-disable; /* external pull-up */
> -			bootph-pre-ram;
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	i2c6_pins: i2c6-0 {
> -		i2c-pins {
> -			pinmux = <GPIOMUX(16, GPOUT_LOW,
> -					      GPOEN_SYS_I2C6_CLK,
> -					      GPI_SYS_I2C6_CLK)>,
> -				 <GPIOMUX(17, GPOUT_LOW,
> -					      GPOEN_SYS_I2C6_DATA,
> -					      GPI_SYS_I2C6_DATA)>;
> -			bias-disable; /* external pull-up */
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -	};
> -
> -	mmc0_pins: mmc0-0 {
> -		mmc-pins {
> -			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
> -				 <PINMUX(PAD_SD0_CMD, 0)>,
> -				 <PINMUX(PAD_SD0_DATA0, 0)>,
> -				 <PINMUX(PAD_SD0_DATA1, 0)>,
> -				 <PINMUX(PAD_SD0_DATA2, 0)>,
> -				 <PINMUX(PAD_SD0_DATA3, 0)>,
> -				 <PINMUX(PAD_SD0_DATA4, 0)>,
> -				 <PINMUX(PAD_SD0_DATA5, 0)>,
> -				 <PINMUX(PAD_SD0_DATA6, 0)>,
> -				 <PINMUX(PAD_SD0_DATA7, 0)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-enable;
> -		};
> -	};
> -
> -	mmc1_pins: mmc1-0 {
> -		clk-pins {
> -			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		mmc-pins {
> -			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
> -					     GPOEN_SYS_SDIO1_CMD,
> -					     GPI_SYS_SDIO1_CMD)>,
> -				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
> -					      GPOEN_SYS_SDIO1_DATA0,
> -					      GPI_SYS_SDIO1_DATA0)>,
> -				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
> -					      GPOEN_SYS_SDIO1_DATA1,
> -					      GPI_SYS_SDIO1_DATA1)>,
> -				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
> -					     GPOEN_SYS_SDIO1_DATA2,
> -					     GPI_SYS_SDIO1_DATA2)>,
> -				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
> -					     GPOEN_SYS_SDIO1_DATA3,
> -					     GPI_SYS_SDIO1_DATA3)>;
> -			bias-pull-up;
> -			drive-strength = <12>;
> -			input-enable;
> -			input-schmitt-enable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pcie0_pins: pcie0-0 {
> -		clkreq-pins {
> -			pinmux = <GPIOMUX(27, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-down;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		wake-pins {
> -			pinmux = <GPIOMUX(32, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pcie1_pins: pcie1-0 {
> -		clkreq-pins {
> -			pinmux = <GPIOMUX(29, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-down;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		wake-pins {
> -			pinmux = <GPIOMUX(21, GPOUT_LOW,
> -				      GPOEN_DISABLE,
> -					      GPI_NONE)>;
> -			bias-pull-up;
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pwmdac_pins: pwmdac-0 {
> -		pwmdac-pins {
> -			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>,
> -				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-disable;
> -			drive-strength = <2>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	pwm_pins: pwm-0 {
> -		pwm-pins {
> -			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
> -					      GPOEN_SYS_PWM0_CHANNEL0,
> -					      GPI_NONE)>,
> -				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
> -					      GPOEN_SYS_PWM0_CHANNEL1,
> -					      GPI_NONE)>;
> -			bias-disable;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -	};
> -
> -	spi0_pins: spi0-0 {
> -		mosi-pins {
> -			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> -					      GPOEN_ENABLE,
> -					      GPI_NONE)>;
> -			bias-disable;
> -			input-disable;
> -			input-schmitt-disable;
> -		};
> -
> -		miso-pins {
> -			pinmux = <GPIOMUX(53, GPOUT_LOW,
> -					      GPOEN_DISABLE,
> -					      GPI_SYS_SPI0_RXD)>;
> -			bias-pull-up;
> -			input-enable;
> -			input-schmitt-enable;
> -		};
> -
> -		sck-pins {
> -			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
> -					      GPOEN_ENABLE,
> -					      GPI_SYS_SPI0_CLK)>;
> -			bias-disable;
> -			input-disable;
> -			input-schmitt-disable;
> -		};
> -
> -		ss-pins {
> -			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
> -					      GPOEN_ENABLE,
> -					      GPI_SYS_SPI0_FSS)>;
> -			bias-disable;
> -			input-disable;
> -			input-schmitt-disable;
> -		};
> -	};
> -
> -	uart0_pins: uart0-0 {
> -		tx-pins {
> -			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> -					     GPOEN_ENABLE,
> -					     GPI_NONE)>;
> -			bias-disable;
> -			drive-strength = <12>;
> -			input-disable;
> -			input-schmitt-disable;
> -			slew-rate = <0>;
> -		};
> -
> -		rx-pins {
> -			pinmux = <GPIOMUX(6, GPOUT_LOW,
> -					     GPOEN_DISABLE,
> -					     GPI_SYS_UART0_RX)>;
> -			bias-disable; /* external pull-up */
> -			drive-strength = <2>;
> -			input-enable;
> -			input-schmitt-enable;
> -			slew-rate = <0>;
> -		};
> -	};
> -};
> -
> -&uart0 {
> -	bootph-pre-ram;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&uart0_pins>;
> -	status = "okay";
> -};
> -
> -&U74_1 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_2 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_3 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> -
> -&U74_4 {
> -	cpu-supply = <&vdd_cpu>;
> -};
> diff --git a/arch/riscv/boot/dts/starfive/jh711x-common.dtsi b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> new file mode 100644
> index 000000000000..809274625615
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> @@ -0,0 +1,664 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh711x.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
> +
> +/ {
> +	aliases {
> +		ethernet0 = &gmac0;
> +		i2c0 = &i2c0;
> +		i2c2 = &i2c2;
> +		i2c5 = &i2c5;
> +		i2c6 = &i2c6;
> +		mmc0 = &mmc0;
> +		mmc1 = &mmc1;
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x40000000 0x1 0x0>;
> +		bootph-pre-ram;
> +	};
> +
> +	gpio-restart {
> +		compatible = "gpio-restart";
> +		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> +		priority = <224>;
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led_status_power: led-0 {
> +			gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	pwmdac_codec: audio-codec {
> +		compatible = "linux,spdif-dit";
> +		#sound-dai-cells = <0>;
> +	};
> +
> +	sound {
> +		compatible = "simple-audio-card";
> +		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		simple-audio-card,dai-link@0 {
> +			reg = <0>;
> +			format = "left_j";
> +			bitclock-master = <&sndcpu0>;
> +			frame-master = <&sndcpu0>;
> +
> +			sndcpu0: cpu {
> +				sound-dai = <&pwmdac>;
> +			};
> +
> +			codec {
> +				sound-dai = <&pwmdac_codec>;
> +			};
> +		};
> +	};
> +};
> +
> +&cpus {
> +	timebase-frequency = <4000000>;
> +};
> +
> +&dvp_clk {
> +	clock-frequency = <74250000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> +	clock-frequency = <125000000>;
> +};
> +
> +&gmac0_rmii_refin {
> +	clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> +	clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> +	clock-frequency = <50000000>;
> +};
> +
> +&hdmitx0_pixelclk {
> +	clock-frequency = <297000000>;
> +};
> +
> +&i2srx_bclk_ext {
> +	clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> +	clock-frequency = <192000>;
> +};
> +
> +&i2stx_bclk_ext {
> +	clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> +	clock-frequency = <192000>;
> +};
> +
> +&mclk_ext {
> +	clock-frequency = <12288000>;
> +};
> +
> +&osc {
> +	clock-frequency = <24000000>;
> +};
> +
> +&rtc_osc {
> +	clock-frequency = <32768>;
> +};
> +
> +&tdm_ext {
> +	clock-frequency = <49152000>;
> +};
> +
> +&camss {
> +	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
> +			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
> +	assigned-clock-rates = <49500000>, <198000000>;
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port@0 {
> +			reg = <0>;
> +		};
> +
> +		port@1 {
> +			reg = <1>;
> +
> +			camss_from_csi2rx: endpoint {
> +				remote-endpoint = <&csi2rx_to_camss>;
> +			};
> +		};
> +	};
> +};
> +
> +&csi2rx {
> +	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
> +	assigned-clock-rates = <297000000>;
> +
> +	ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		port@0 {
> +			reg = <0>;
> +
> +			/* remote MIPI sensor endpoint */
> +		};
> +
> +		port@1 {
> +			reg = <1>;
> +
> +			csi2rx_to_camss: endpoint {
> +				remote-endpoint = <&camss_from_csi2rx>;
> +			};
> +		};
> +	};
> +};
> +
> +&gmac0 {
> +	phy-handle = <&phy0>;
> +	phy-mode = "rgmii-id";
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "snps,dwmac-mdio";
> +
> +		phy0: ethernet-phy@0 {
> +			reg = <0>;
> +		};
> +	};
> +};
> +
> +&i2c0 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c0_pins>;
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c2_pins>;
> +	status = "okay";
> +};
> +
> +&i2c5 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c5_pins>;
> +	status = "okay";
> +
> +	axp15060: pmic@36 {
> +		compatible = "x-powers,axp15060";
> +		reg = <0x36>;
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +
> +		regulators {
> +			vcc_3v3: dcdc1 {
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-name = "vcc_3v3";
> +			};
> +
> +			vdd_cpu: dcdc2 {
> +				regulator-always-on;
> +				regulator-min-microvolt = <500000>;
> +				regulator-max-microvolt = <1540000>;
> +				regulator-name = "vdd_cpu";
> +			};
> +
> +			emmc_vdd: aldo4 {
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-name = "emmc_vdd";
> +			};
> +		};
> +	};
> +
> +	eeprom@50 {
> +		compatible = "atmel,24c04";
> +		reg = <0x50>;
> +		bootph-pre-ram;
> +		pagesize = <16>;
> +	};
> +};
> +
> +&i2c6 {
> +	clock-frequency = <100000>;
> +	i2c-sda-hold-time-ns = <300>;
> +	i2c-sda-falling-time-ns = <510>;
> +	i2c-scl-falling-time-ns = <510>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&i2c6_pins>;
> +	status = "okay";
> +};
> +
> +&mmc0 {
> +	max-frequency = <100000000>;
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
> +	assigned-clock-rates = <50000000>;
> +	bus-width = <8>;
> +	bootph-pre-ram;
> +	cap-mmc-highspeed;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	cap-mmc-hw-reset;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc0_pins>;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
> +	status = "okay";
> +};
> +
> +&mmc1 {
> +	max-frequency = <100000000>;
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
> +	assigned-clock-rates = <50000000>;
> +	bus-width = <4>;
> +	bootph-pre-ram;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	cap-sd-highspeed;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mmc1_pins>;
> +	status = "okay";
> +};
> +
> +&pcie0 {
> +	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
> +	phys = <&pciephy0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie0_pins>;
> +};
> +
> +&pcie1 {
> +	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
> +	phys = <&pciephy1>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie1_pins>;
> +};
> +
> +&pwmdac {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pwmdac_pins>;
> +};
> +
> +&qspi {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	status = "okay";
> +
> +	nor_flash: flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +		bootph-pre-ram;
> +		cdns,read-delay = <2>;
> +		spi-max-frequency = <100000000>;
> +		cdns,tshsl-ns = <1>;
> +		cdns,tsd2d-ns = <1>;
> +		cdns,tchsh-ns = <1>;
> +		cdns,tslch-ns = <1>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			spl@0 {
> +				reg = <0x0 0xf0000>;
> +			};
> +			uboot-env@f0000 {
> +				reg = <0xf0000 0x10000>;
> +			};
> +			uboot@100000 {
> +				reg = <0x100000 0xf00000>;
> +			};
> +		};
> +	};
> +};
> +
> +&pwm {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pwm_pins>;
> +};
> +
> +&spi0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&spi0_pins>;
> +};
> +
> +&syscrg {
> +	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> +			  <&syscrg JH7110_SYSCLK_QSPI_REF>,
> +			  <&syscrg JH7110_SYSCLK_CPU_CORE>,
> +			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
> +	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> +				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> +	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1500000000>;
> +};
> +
> +&sysgpio {
> +	i2c0_pins: i2c0-0 {
> +		i2c-pins {
> +			pinmux = <GPIOMUX(57, GPOUT_LOW,
> +					      GPOEN_SYS_I2C0_CLK,
> +					      GPI_SYS_I2C0_CLK)>,
> +				 <GPIOMUX(58, GPOUT_LOW,
> +					      GPOEN_SYS_I2C0_DATA,
> +					      GPI_SYS_I2C0_DATA)>;
> +			bias-disable; /* external pull-up */
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	i2c2_pins: i2c2-0 {
> +		i2c-pins {
> +			pinmux = <GPIOMUX(3, GPOUT_LOW,
> +					     GPOEN_SYS_I2C2_CLK,
> +					     GPI_SYS_I2C2_CLK)>,
> +				 <GPIOMUX(2, GPOUT_LOW,
> +					     GPOEN_SYS_I2C2_DATA,
> +					     GPI_SYS_I2C2_DATA)>;
> +			bias-disable; /* external pull-up */
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	i2c5_pins: i2c5-0 {
> +		bootph-pre-ram;
> +
> +		i2c-pins {
> +			pinmux = <GPIOMUX(19, GPOUT_LOW,
> +					      GPOEN_SYS_I2C5_CLK,
> +					      GPI_SYS_I2C5_CLK)>,
> +				 <GPIOMUX(20, GPOUT_LOW,
> +					      GPOEN_SYS_I2C5_DATA,
> +					      GPI_SYS_I2C5_DATA)>;
> +			bias-disable; /* external pull-up */
> +			bootph-pre-ram;
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	i2c6_pins: i2c6-0 {
> +		i2c-pins {
> +			pinmux = <GPIOMUX(16, GPOUT_LOW,
> +					      GPOEN_SYS_I2C6_CLK,
> +					      GPI_SYS_I2C6_CLK)>,
> +				 <GPIOMUX(17, GPOUT_LOW,
> +					      GPOEN_SYS_I2C6_DATA,
> +					      GPI_SYS_I2C6_DATA)>;
> +			bias-disable; /* external pull-up */
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +	};
> +
> +	mmc0_pins: mmc0-0 {
> +		mmc-pins {
> +			pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
> +				 <PINMUX(PAD_SD0_CMD, 0)>,
> +				 <PINMUX(PAD_SD0_DATA0, 0)>,
> +				 <PINMUX(PAD_SD0_DATA1, 0)>,
> +				 <PINMUX(PAD_SD0_DATA2, 0)>,
> +				 <PINMUX(PAD_SD0_DATA3, 0)>,
> +				 <PINMUX(PAD_SD0_DATA4, 0)>,
> +				 <PINMUX(PAD_SD0_DATA5, 0)>,
> +				 <PINMUX(PAD_SD0_DATA6, 0)>,
> +				 <PINMUX(PAD_SD0_DATA7, 0)>;
> +			bias-pull-up;
> +			drive-strength = <12>;
> +			input-enable;
> +		};
> +	};
> +
> +	mmc1_pins: mmc1-0 {
> +		clk-pins {
> +			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			bias-pull-up;
> +			drive-strength = <12>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;

Please, add

			bootph-pre-ram;

to allow U-Boot to boot from SD-card. Maybe in a separate patch.

Best regards

Heinrich

> +		};
> +
> +		mmc-pins {
> +			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
> +					     GPOEN_SYS_SDIO1_CMD,
> +					     GPI_SYS_SDIO1_CMD)>,
> +				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
> +					      GPOEN_SYS_SDIO1_DATA0,
> +					      GPI_SYS_SDIO1_DATA0)>,
> +				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
> +					      GPOEN_SYS_SDIO1_DATA1,
> +					      GPI_SYS_SDIO1_DATA1)>,
> +				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
> +					     GPOEN_SYS_SDIO1_DATA2,
> +					     GPI_SYS_SDIO1_DATA2)>,
> +				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
> +					     GPOEN_SYS_SDIO1_DATA3,
> +					     GPI_SYS_SDIO1_DATA3)>;
> +			bias-pull-up;
> +			drive-strength = <12>;
> +			input-enable;
> +			input-schmitt-enable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pcie0_pins: pcie0-0 {
> +		clkreq-pins {
> +			pinmux = <GPIOMUX(27, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-down;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		wake-pins {
> +			pinmux = <GPIOMUX(32, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-up;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pcie1_pins: pcie1-0 {
> +		clkreq-pins {
> +			pinmux = <GPIOMUX(29, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-down;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		wake-pins {
> +			pinmux = <GPIOMUX(21, GPOUT_LOW,
> +				      GPOEN_DISABLE,
> +					      GPI_NONE)>;
> +			bias-pull-up;
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pwmdac_pins: pwmdac-0 {
> +		pwmdac-pins {
> +			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>,
> +				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <2>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pwm_pins: pwm-0 {
> +		pwm-pins {
> +			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
> +					      GPOEN_SYS_PWM0_CHANNEL0,
> +					      GPI_NONE)>,
> +				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
> +					      GPOEN_SYS_PWM0_CHANNEL1,
> +					      GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <12>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	spi0_pins: spi0-0 {
> +		mosi-pins {
> +			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> +					      GPOEN_ENABLE,
> +					      GPI_NONE)>;
> +			bias-disable;
> +			input-disable;
> +			input-schmitt-disable;
> +		};
> +
> +		miso-pins {
> +			pinmux = <GPIOMUX(53, GPOUT_LOW,
> +					      GPOEN_DISABLE,
> +					      GPI_SYS_SPI0_RXD)>;
> +			bias-pull-up;
> +			input-enable;
> +			input-schmitt-enable;
> +		};
> +
> +		sck-pins {
> +			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
> +					      GPOEN_ENABLE,
> +					      GPI_SYS_SPI0_CLK)>;
> +			bias-disable;
> +			input-disable;
> +			input-schmitt-disable;
> +		};
> +
> +		ss-pins {
> +			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
> +					      GPOEN_ENABLE,
> +					      GPI_SYS_SPI0_FSS)>;
> +			bias-disable;
> +			input-disable;
> +			input-schmitt-disable;
> +		};
> +	};
> +
> +	uart0_pins: uart0-0 {
> +		tx-pins {
> +			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> +					     GPOEN_ENABLE,
> +					     GPI_NONE)>;
> +			bias-disable;
> +			drive-strength = <12>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +
> +		rx-pins {
> +			pinmux = <GPIOMUX(6, GPOUT_LOW,
> +					     GPOEN_DISABLE,
> +					     GPI_SYS_UART0_RX)>;
> +			bias-disable; /* external pull-up */
> +			drive-strength = <2>;
> +			input-enable;
> +			input-schmitt-enable;
> +			slew-rate = <0>;
> +		};
> +	};
> +};
> +
> +&uart0 {
> +	bootph-pre-ram;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pins>;
> +	status = "okay";
> +};
> +
> +&U74_1 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_2 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_3 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_4 {
> +	cpu-supply = <&vdd_cpu>;
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh711x.dtsi b/arch/riscv/boot/dts/starfive/jh711x.dtsi
> index 6e56e9d20bb0..a380d3dabedd 100644
> --- a/arch/riscv/boot/dts/starfive/jh711x.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh711x.dtsi
> @@ -205,22 +205,6 @@ core4 {
>   	cpu_opp: opp-table-0 {
>   			compatible = "operating-points-v2";
>   			opp-shared;
> -			opp-375000000 {
> -					opp-hz = /bits/ 64 <375000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-500000000 {
> -					opp-hz = /bits/ 64 <500000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-750000000 {
> -					opp-hz = /bits/ 64 <750000000>;
> -					opp-microvolt = <800000>;
> -			};
> -			opp-1500000000 {
> -					opp-hz = /bits/ 64 <1500000000>;
> -					opp-microvolt = <1040000>;
> -			};
>   	};
>   
>   	thermal-zones {

[PATCH v2 5/8] riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110 common dtsi

[Hal Feng]

Some nodes in this file are not used by the upcoming VisionFive 2 Lite
board. Move them to the jh7110 common dtsi to prepare for adding the
new VisionFive 2 Lite device tree.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 14 ++++++++++++++
 arch/riscv/boot/dts/starfive/jh711x-common.dtsi |  8 --------
 2 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index dd5805ef70a1..cdc362b8d58b 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -25,3 +25,17 @@ opp-1500000000 {
 		opp-microvolt = <1040000>;
 	};
 };
+
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
+&mmc1 {
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
diff --git a/arch/riscv/boot/dts/starfive/jh711x-common.dtsi b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
index 809274625615..42b8f60725fb 100644
--- a/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
@@ -281,14 +281,8 @@ &mmc0 {
 	assigned-clock-rates = <50000000>;
 	bus-width = <8>;
 	bootph-pre-ram;
-	cap-mmc-highspeed;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	cap-mmc-hw-reset;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&emmc_vdd>;
 	status = "okay";
 };
 
@@ -298,8 +292,6 @@ &mmc1 {
 	assigned-clock-rates = <50000000>;
 	bus-width = <4>;
 	bootph-pre-ram;
-	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
-	disable-wp;
 	cap-sd-highspeed;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-- 
2.43.2

Re: [PATCH v2 5/8] riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110 common dtsi

[E Shattow]

On 11/7/25 01:55, Hal Feng wrote:
> Some nodes in this file are not used by the upcoming VisionFive 2 Lite
> board. Move them to the jh7110 common dtsi to prepare for adding the
> new VisionFive 2 Lite device tree.
> 
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 14 ++++++++++++++
>  arch/riscv/boot/dts/starfive/jh711x-common.dtsi |  8 --------
>  2 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index dd5805ef70a1..cdc362b8d58b 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -25,3 +25,17 @@ opp-1500000000 {
>  		opp-microvolt = <1040000>;
>  	};
>  };
> +
> +&mmc0 {
> +	cap-mmc-highspeed;
> +	cap-mmc-hw-reset;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
> +};
> +
> +&mmc1 {
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh711x-common.dtsi b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> index 809274625615..42b8f60725fb 100644
> --- a/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> @@ -281,14 +281,8 @@ &mmc0 {
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <8>;
>  	bootph-pre-ram;
> -	cap-mmc-highspeed;
> -	mmc-ddr-1_8v;
> -	mmc-hs200-1_8v;
> -	cap-mmc-hw-reset;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&mmc0_pins>;
> -	vmmc-supply = <&vcc_3v3>;
> -	vqmmc-supply = <&emmc_vdd>;
>  	status = "okay";
>  };
>  
> @@ -298,8 +292,6 @@ &mmc1 {
>  	assigned-clock-rates = <50000000>;
>  	bus-width = <4>;
>  	bootph-pre-ram;
> -	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> -	disable-wp;
>  	cap-sd-highspeed;
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&mmc1_pins>;

Reviewed-by: E Shattow <e@freeshell.de>

[PATCH v2 6/8] riscv: dts: starfive: Add common board dtsi for JH7110s and VisionFive 2 Lite variants

[Hal Feng]

Add common board dtsi for use by JH7110s based boards and
VisionFive 2 Lite variants.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../boot/dts/starfive/jh7110s-common.dtsi     |  27 ++++
 .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++++++++++++++++
 2 files changed, 153 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110s-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
new file mode 100644
index 000000000000..ad0d54d44123
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh711x-common.dtsi"
+
+&cpu_opp {
+	opp-312500000 {
+		opp-hz = /bits/ 64 <312500000>;
+		opp-microvolt = <800000>;
+	};
+	opp-417000000 {
+		opp-hz = /bits/ 64 <417000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-625000000 {
+		opp-hz = /bits/ 64 <625000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1250000000 {
+		opp-hz = /bits/ 64 <1250000000>;
+		opp-microvolt = <1000000>;
+	};
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
new file mode 100644
index 000000000000..747fb806034d
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110s-common.dtsi"
+
+&gmac0 {
+	starfive,tx-use-rgmii-clk;
+	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&mmc1 {
+	max-frequency = <50000000>;
+	keep-power-in-suspend;
+	non-removable;
+};
+
+&pcie1 {
+	enable-gpios = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&phy0 {
+	motorcomm,tx-clk-adj-enabled;
+	motorcomm,tx-clk-100-inverted;
+	motorcomm,tx-clk-1000-inverted;
+	motorcomm,rx-clk-drv-microamp = <3970>;
+	motorcomm,rx-data-drv-microamp = <2910>;
+	rx-internal-delay-ps = <1500>;
+	tx-internal-delay-ps = <1500>;
+};
+
+&pwm {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&syscrg {
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
+};
+
+&sysgpio {
+	uart1_pins: uart1-0 {
+		tx-pins {
+			pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		rx-pins {
+			pinmux = <GPIOMUX(23, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_RX)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+
+		cts-pins {
+			pinmux = <GPIOMUX(24, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_CTS)>;
+			input-enable;
+		};
+
+		rts-pins {
+			pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-enable;
+		};
+	};
+
+	usb0_pins: usb0-0 {
+		power-pins {
+			pinmux = <GPIOMUX(26, GPOUT_HIGH,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-disable;
+		};
+
+		switch-pins {
+			pinmux = <GPIOMUX(62, GPOUT_LOW,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-disable;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
+	status = "okay";
+};
+
+&usb_cdns3 {
+	phys = <&usbphy0>, <&pciephy0>;
+	phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
+};
-- 
2.43.2

[PATCH v2 7/8] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[Hal Feng]

VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.

Board features:
- JH7110S SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable 64GiB eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI

VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/Makefile         |  2 ++
 .../jh7110s-starfive-visionfive-2-lite.dts    | 20 +++++++++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 62b659f89ba7..f53109253d41 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -15,3 +15,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
+
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
new file mode 100644
index 000000000000..ac5e66027bad
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110s-starfive-visionfive-2-lite.dtsi"
+
+/ {
+	model = "StarFive VisionFive 2 Lite";
+	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
+};
+
+&mmc0 {
+	bus-width = <4>;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
+	disable-wp;
+	cap-sd-highspeed;
+};
-- 
2.43.2

[PATCH v2 8/8] riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree

[Hal Feng]

VisionFive 2 Lite eMMC board uses a non-removable onboard 64GiB eMMC
instead of the MicroSD slot.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/Makefile         |  1 +
 ...h7110s-starfive-visionfive-2-lite-emmc.dts | 22 +++++++++++++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index f53109253d41..a60244803829 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -17,3 +17,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
 
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite-emmc.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
new file mode 100644
index 000000000000..60ce2753f2d1
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110s-starfive-visionfive-2-lite.dtsi"
+
+/ {
+	model = "StarFive VisionFive 2 Lite eMMC";
+	compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s";
+};
+
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
-- 
2.43.2

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[E Shattow]

On 11/7/25 01:55, Hal Feng wrote:
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
> 
> Board features:
> - JH7110S SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
> 
> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
> 
> Changes since v1:
> - Drop patch 1 because it is applied.
> - Rename jh7110.dtsi to jh711x.dtsi.
> - Move the content of jh7110-common.dtsi to the new file
>   jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
> patch 4:
> - Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
> patch 5:
> - Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-2-lite.dtsi.
> 
> Changes since RFC:
> - Add jh7110s compatible to the generic cpufreq driver.
> - Fix the dtbs_check error by adding the missing "enable-gpios" property
>   in jh7110 pcie dt-bindings.
> - Rebase on the latest mainline.
> - Add VisionFive 2 Lite eMMC board device tree and add a common board dtsi
>   for VisionFive 2 Lite variants.
> - Add usb switch pin configuration (GPIO62).
> - Improve the commit messages.
> 
> History:
> v1: https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfivetech.com/
> RFC: https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivetech.com/
> 
> Hal Feng (8):
>   dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
>   dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
>     board
>   riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
>   riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to
>     it
>   riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110
>     common dtsi
>   riscv: dts: starfive: Add common board dtsi for JH7110s and VisionFive
>     2 Lite variants
>   riscv: dts: starfive: Add VisionFive 2 Lite board device tree
>   riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
> 
>  .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
>  .../devicetree/bindings/riscv/starfive.yaml   |   6 +
>  arch/riscv/boot/dts/starfive/Makefile         |   3 +
>  .../boot/dts/starfive/jh7110-common.dtsi      | 653 +----------------
>  .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
>  ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
>  .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
>  .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
>  .../boot/dts/starfive/jh711x-common.dtsi      | 656 ++++++++++++++++++
>  .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
>  10 files changed, 879 insertions(+), 654 deletions(-)
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
>  create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
>  rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} (99%)
> 
> 
> base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c

Small nit that "lite-emmc" is confusing together. In patches to U-Boot
dev mailing list the EEPROM product id is demonstrated to be with "SL"
suffix when compared to VisionFive 2 (JH7110) so I suggest avoid
confusion in upstream and use for VisionFive 2 Lite (JH7110S) these
compatible names:

starfive,visionfive-2sl-lite
starfive,visionfive-2sl-emmc

Also filenames:

jh7110s-starfive-visionfive-2sl-lite.dts
jh7110s-starfive-visionfive-2sl.dtsi
jh7110s-starfive-visionfive-2sl-emmc.dts

What do you think?

-E

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Heinrich Schuchardt]

On 11/7/25 12:11, E Shattow wrote:
> 
> 
> On 11/7/25 01:55, Hal Feng wrote:
>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
>> SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
>>
>> Board features:
>> - JH7110S SoC
>> - 4/8 GiB LPDDR4 DRAM
>> - AXP15060 PMIC
>> - 40 pin GPIO header
>> - 1x USB 3.0 host port
>> - 3x USB 2.0 host port
>> - 1x M.2 M-Key (size: 2242)
>> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
>> - 1x QSPI Flash
>> - 1x I2C EEPROM
>> - 1x 1Gbps Ethernet port
>> - SDIO-based Wi-Fi & UART-based Bluetooth
>> - 1x HDMI port
>> - 1x 2-lane DSI
>> - 1x 2-lane CSI
>>
>> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
>> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
>> More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
>>
>> Changes since v1:
>> - Drop patch 1 because it is applied.
>> - Rename jh7110.dtsi to jh711x.dtsi.
>> - Move the content of jh7110-common.dtsi to the new file
>>    jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
>> patch 4:
>> - Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
>> patch 5:
>> - Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-2-lite.dtsi.
>>
>> Changes since RFC:
>> - Add jh7110s compatible to the generic cpufreq driver.
>> - Fix the dtbs_check error by adding the missing "enable-gpios" property
>>    in jh7110 pcie dt-bindings.
>> - Rebase on the latest mainline.
>> - Add VisionFive 2 Lite eMMC board device tree and add a common board dtsi
>>    for VisionFive 2 Lite variants.
>> - Add usb switch pin configuration (GPIO62).
>> - Improve the commit messages.
>>
>> History:
>> v1: https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfivetech.com/
>> RFC: https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivetech.com/
>>
>> Hal Feng (8):
>>    dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
>>    dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
>>      board
>>    riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
>>    riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to
>>      it
>>    riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110
>>      common dtsi
>>    riscv: dts: starfive: Add common board dtsi for JH7110s and VisionFive
>>      2 Lite variants
>>    riscv: dts: starfive: Add VisionFive 2 Lite board device tree
>>    riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
>>
>>   .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
>>   .../devicetree/bindings/riscv/starfive.yaml   |   6 +
>>   arch/riscv/boot/dts/starfive/Makefile         |   3 +
>>   .../boot/dts/starfive/jh7110-common.dtsi      | 653 +----------------
>>   .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
>>   ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
>>   .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
>>   .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
>>   .../boot/dts/starfive/jh711x-common.dtsi      | 656 ++++++++++++++++++
>>   .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
>>   10 files changed, 879 insertions(+), 654 deletions(-)
>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
>>   create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
>>   rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} (99%)
>>
>>
>> base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c
> 
> Small nit that "lite-emmc" is confusing together. In patches to U-Boot
> dev mailing list the EEPROM product id is demonstrated to be with "SL"
> suffix when compared to VisionFive 2 (JH7110) so I suggest avoid
> confusion in upstream and use for VisionFive 2 Lite (JH7110S) these
> compatible names:
> 
> starfive,visionfive-2sl-lite
> starfive,visionfive-2sl-emmc
> 
> Also filenames:
> 
> jh7110s-starfive-visionfive-2sl-lite.dts
> jh7110s-starfive-visionfive-2sl.dtsi
> jh7110s-starfive-visionfive-2sl-emmc.dts
> 
> What do you think?
> 

This is a serial number for the Lite board:
VF7110SL-2310-D002E000-xxxxxxxx

Here E000 encodes that we have no eMMC.

The S is part of 7110S which we already have in 'jh7110s'. And the L is 
already decoded as 'lite' in this patch series. Duplicating this 
information as 'sl' as you suggested provides no benefit.

Let's just stick with Hal's suggestion.

Best regards

Heinrich

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[E Shattow]

On 11/7/25 03:21, Heinrich Schuchardt wrote:
> On 11/7/25 12:11, E Shattow wrote:
>>
>>
>> On 11/7/25 01:55, Hal Feng wrote:
>>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
>>> SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
>>>
>>> Board features:
>>> - JH7110S SoC
>>> - 4/8 GiB LPDDR4 DRAM
>>> - AXP15060 PMIC
>>> - 40 pin GPIO header
>>> - 1x USB 3.0 host port
>>> - 3x USB 2.0 host port
>>> - 1x M.2 M-Key (size: 2242)
>>> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
>>> - 1x QSPI Flash
>>> - 1x I2C EEPROM
>>> - 1x 1Gbps Ethernet port
>>> - SDIO-based Wi-Fi & UART-based Bluetooth
>>> - 1x HDMI port
>>> - 1x 2-lane DSI
>>> - 1x 2-lane CSI
>>>
>>> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/
>>> VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
>>> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/
>>> VisionFive2Lite/VisionFive2LiteQSG/index.html
>>> More documents: https://doc-en.rvspace.org/Doc_Center/
>>> visionfive_2_lite.html
>>>
>>> Changes since v1:
>>> - Drop patch 1 because it is applied.
>>> - Rename jh7110.dtsi to jh711x.dtsi.
>>> - Move the content of jh7110-common.dtsi to the new file
>>>    jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
>>> patch 4:
>>> - Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
>>> patch 5:
>>> - Add jh7110s-common.dtsi and include it in jh7110s-starfive-
>>> visionfive-2-lite.dtsi.
>>>
>>> Changes since RFC:
>>> - Add jh7110s compatible to the generic cpufreq driver.
>>> - Fix the dtbs_check error by adding the missing "enable-gpios" property
>>>    in jh7110 pcie dt-bindings.
>>> - Rebase on the latest mainline.
>>> - Add VisionFive 2 Lite eMMC board device tree and add a common board
>>> dtsi
>>>    for VisionFive 2 Lite variants.
>>> - Add usb switch pin configuration (GPIO62).
>>> - Improve the commit messages.
>>>
>>> History:
>>> v1: https://lore.kernel.org/all/20251016080054.12484-1-
>>> hal.feng@starfivetech.com/
>>> RFC: https://lore.kernel.org/all/20250821100930.71404-1-
>>> hal.feng@starfivetech.com/
>>>
>>> Hal Feng (8):
>>>    dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
>>>    dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
>>>      board
>>>    riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
>>>    riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to
>>>      it
>>>    riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110
>>>      common dtsi
>>>    riscv: dts: starfive: Add common board dtsi for JH7110s and
>>> VisionFive
>>>      2 Lite variants
>>>    riscv: dts: starfive: Add VisionFive 2 Lite board device tree
>>>    riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
>>>
>>>   .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
>>>   .../devicetree/bindings/riscv/starfive.yaml   |   6 +
>>>   arch/riscv/boot/dts/starfive/Makefile         |   3 +
>>>   .../boot/dts/starfive/jh7110-common.dtsi      | 653 +----------------
>>>   .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
>>>   ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
>>>   .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
>>>   .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
>>>   .../boot/dts/starfive/jh711x-common.dtsi      | 656 ++++++++++++++++++
>>>   .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
>>>   10 files changed, 879 insertions(+), 654 deletions(-)
>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
>>> visionfive-2-lite-emmc.dts
>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
>>> visionfive-2-lite.dts
>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
>>> visionfive-2-lite.dtsi
>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
>>>   rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} (99%)
>>>
>>>
>>> base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c
>>
>> Small nit that "lite-emmc" is confusing together. In patches to U-Boot
>> dev mailing list the EEPROM product id is demonstrated to be with "SL"
>> suffix when compared to VisionFive 2 (JH7110) so I suggest avoid
>> confusion in upstream and use for VisionFive 2 Lite (JH7110S) these
>> compatible names:
>>
>> starfive,visionfive-2sl-lite
>> starfive,visionfive-2sl-emmc
>>
>> Also filenames:
>>
>> jh7110s-starfive-visionfive-2sl-lite.dts
>> jh7110s-starfive-visionfive-2sl.dtsi
>> jh7110s-starfive-visionfive-2sl-emmc.dts
>>
>> What do you think?
>>
> 
> This is a serial number for the Lite board:
> VF7110SL-2310-D002E000-xxxxxxxx
> 
> Here E000 encodes that we have no eMMC.
> 
> The S is part of 7110S which we already have in 'jh7110s'. And the L is
> already decoded as 'lite' in this patch series. Duplicating this
> information as 'sl' as you suggested provides no benefit.

The convention in dts file names is CPU model first so that will be
redundant or not redundant depending on the name of the product anyway;
whether it is redundant or not is not the driver of whether it is
confusing to have contradictory terminology in the product name and
compatible names and dts filenames.

> 
> Let's just stick with Hal's suggestion.
> 
> Best regards
> 
> Heinrich

The "lite" product name in similar products refers to non-populated emmc
replaced by sd card, so there is benefit to choose a more concise name
that is not confusing.

I did consider suggesting:

jh7110s-starfive-visionfive-2-lite.dts
jh7110s-starfive-visionfive-2.dtsi
jh7110s-starfive-visionfive-2-emmc.dts

but this is a loss of information and does not help readability. By
extension we're not duplicating information to be more descriptive with
the product name. Sure I'd go along with:

jh7110s-starfive-visionfive-2-lite-card.dts
jh7110s-starfive-visionfive-2-lite.dtsi
jh7110s-starfive-visionfive-2-lite-emmc.dts

But my suggestion remains:

jh7110s-starfive-visionfive-2sl-lite.dts
jh7110s-starfive-visionfive-2sl.dtsi
jh7110s-starfive-visionfive-2sl-emmc.dts

for the reason that it's very clearly not the "non-emmc" version of the
VisionFive 2. You can't mistake it if done the way I am suggesting.

-E

RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

> On 07.11.25 20:02, E Shattow wrote:
> On 11/7/25 03:21, Heinrich Schuchardt wrote:
> > On 11/7/25 12:11, E Shattow wrote:
> >>
> >>
> >> On 11/7/25 01:55, Hal Feng wrote:
> >>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
> >>> industrial SoC which can run at -40~85 degrees centigrade and up to
> 1.25GHz.
> >>>
> >>> Board features:
> >>> - JH7110S SoC
> >>> - 4/8 GiB LPDDR4 DRAM
> >>> - AXP15060 PMIC
> >>> - 40 pin GPIO header
> >>> - 1x USB 3.0 host port
> >>> - 3x USB 2.0 host port
> >>> - 1x M.2 M-Key (size: 2242)
> >>> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> >>> - 1x QSPI Flash
> >>> - 1x I2C EEPROM
> >>> - 1x 1Gbps Ethernet port
> >>> - SDIO-based Wi-Fi & UART-based Bluetooth
> >>> - 1x HDMI port
> >>> - 1x 2-lane DSI
> >>> - 1x 2-lane CSI
> >>>
> >>> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/
> >>> VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> >>> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/
> >>> VisionFive2Lite/VisionFive2LiteQSG/index.html
> >>> More documents: https://doc-en.rvspace.org/Doc_Center/
> >>> visionfive_2_lite.html
> >>>
> >>> Changes since v1:
> >>> - Drop patch 1 because it is applied.
> >>> - Rename jh7110.dtsi to jh711x.dtsi.
> >>> - Move the content of jh7110-common.dtsi to the new file
> >>>    jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
> >>> patch 4:
> >>> - Move the uncommon nodes to jh7110-common.dtsi instead of board
> dts.
> >>> patch 5:
> >>> - Add jh7110s-common.dtsi and include it in jh7110s-starfive-
> >>> visionfive-2-lite.dtsi.
> >>>
> >>> Changes since RFC:
> >>> - Add jh7110s compatible to the generic cpufreq driver.
> >>> - Fix the dtbs_check error by adding the missing "enable-gpios"
> >>> property
> >>>    in jh7110 pcie dt-bindings.
> >>> - Rebase on the latest mainline.
> >>> - Add VisionFive 2 Lite eMMC board device tree and add a common
> >>> board dtsi
> >>>    for VisionFive 2 Lite variants.
> >>> - Add usb switch pin configuration (GPIO62).
> >>> - Improve the commit messages.
> >>>
> >>> History:
> >>> v1: https://lore.kernel.org/all/20251016080054.12484-1-
> >>> hal.feng@starfivetech.com/
> >>> RFC: https://lore.kernel.org/all/20250821100930.71404-1-
> >>> hal.feng@starfivetech.com/
> >>>
> >>> Hal Feng (8):
> >>>    dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
> >>>    dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2
> >>> Lite
> >>>      board
> >>>    riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
> >>>    riscv: dts: starfive: Split jh7110-common.dtsi and move opp table
> >>> to
> >>>      it
> >>>    riscv: dts: starfive: jh711x-common: Move out some nodes to
> >>> jh7110
> >>>      common dtsi
> >>>    riscv: dts: starfive: Add common board dtsi for JH7110s and
> >>> VisionFive
> >>>      2 Lite variants
> >>>    riscv: dts: starfive: Add VisionFive 2 Lite board device tree
> >>>    riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device
> >>> tree
> >>>
> >>>   .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
> >>>   .../devicetree/bindings/riscv/starfive.yaml   |   6 +
> >>>   arch/riscv/boot/dts/starfive/Makefile         |   3 +
> >>>   .../boot/dts/starfive/jh7110-common.dtsi      | 653
> >>> +----------------
> >>>   .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
> >>>   ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
> >>>   .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
> >>>   .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
> >>>   .../boot/dts/starfive/jh711x-common.dtsi      | 656
> >>> ++++++++++++++++++
> >>>   .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
> >>>   10 files changed, 879 insertions(+), 654 deletions(-)
> >>>   create mode 100644
> >>> arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
> >>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
> >>> visionfive-2-lite-emmc.dts
> >>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
> >>> visionfive-2-lite.dts
> >>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
> >>> visionfive-2-lite.dtsi
> >>>   create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> >>>   rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi}
> >>> (99%)
> >>>
> >>>
> >>> base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c
> >>
> >> Small nit that "lite-emmc" is confusing together. In patches to
> >> U-Boot dev mailing list the EEPROM product id is demonstrated to be with
> "SL"
> >> suffix when compared to VisionFive 2 (JH7110) so I suggest avoid
> >> confusion in upstream and use for VisionFive 2 Lite (JH7110S) these
> >> compatible names:
> >>
> >> starfive,visionfive-2sl-lite
> >> starfive,visionfive-2sl-emmc
> >>
> >> Also filenames:
> >>
> >> jh7110s-starfive-visionfive-2sl-lite.dts
> >> jh7110s-starfive-visionfive-2sl.dtsi
> >> jh7110s-starfive-visionfive-2sl-emmc.dts
> >>
> >> What do you think?
> >>
> >
> > This is a serial number for the Lite board:
> > VF7110SL-2310-D002E000-xxxxxxxx
> >
> > Here E000 encodes that we have no eMMC.
> >
> > The S is part of 7110S which we already have in 'jh7110s'. And the L
> > is already decoded as 'lite' in this patch series. Duplicating this
> > information as 'sl' as you suggested provides no benefit.
> 
> The convention in dts file names is CPU model first so that will be redundant
> or not redundant depending on the name of the product anyway; whether it
> is redundant or not is not the driver of whether it is confusing to have
> contradictory terminology in the product name and compatible names and dts
> filenames.
> 
> >
> > Let's just stick with Hal's suggestion.
> >
> > Best regards
> >
> > Heinrich
> 
> The "lite" product name in similar products refers to non-populated emmc
> replaced by sd card, so there is benefit to choose a more concise name that is
> not confusing.
> 
> I did consider suggesting:
> 
> jh7110s-starfive-visionfive-2-lite.dts
> jh7110s-starfive-visionfive-2.dtsi
> jh7110s-starfive-visionfive-2-emmc.dts
> 
> but this is a loss of information and does not help readability. By extension
> we're not duplicating information to be more descriptive with the product
> name. Sure I'd go along with:
> 
> jh7110s-starfive-visionfive-2-lite-card.dts
> jh7110s-starfive-visionfive-2-lite.dtsi
> jh7110s-starfive-visionfive-2-lite-emmc.dts
> 
> But my suggestion remains:
> 
> jh7110s-starfive-visionfive-2sl-lite.dts
> jh7110s-starfive-visionfive-2sl.dtsi
> jh7110s-starfive-visionfive-2sl-emmc.dts
> 
> for the reason that it's very clearly not the "non-emmc" version of the
> VisionFive 2. You can't mistake it if done the way I am suggesting.

VisionFive 2 Lite is not the "non-emmc" version of the VisionFive 2. "Lite" here means the
light version and smaller size. I think we can't apply the name definition of another product
to here. VisionFive 2 Lite is the official name of this product and the name we call in our
official documents.

Best regards,
Hal

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[E Shattow]

On 11/11/25 23:24, Hal Feng wrote:
>> On 07.11.25 20:02, E Shattow wrote:
>> On 11/7/25 03:21, Heinrich Schuchardt wrote:
>>> On 11/7/25 12:11, E Shattow wrote:
>>>>
>>>>
>>>> On 11/7/25 01:55, Hal Feng wrote:
>>>>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
>>>>> industrial SoC which can run at -40~85 degrees centigrade and up to
>> 1.25GHz.
>>>>>
>>>>> Board features:
>>>>> - JH7110S SoC
>>>>> - 4/8 GiB LPDDR4 DRAM
>>>>> - AXP15060 PMIC
>>>>> - 40 pin GPIO header
>>>>> - 1x USB 3.0 host port
>>>>> - 3x USB 2.0 host port
>>>>> - 1x M.2 M-Key (size: 2242)
>>>>> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
>>>>> - 1x QSPI Flash
>>>>> - 1x I2C EEPROM
>>>>> - 1x 1Gbps Ethernet port
>>>>> - SDIO-based Wi-Fi & UART-based Bluetooth
>>>>> - 1x HDMI port
>>>>> - 1x 2-lane DSI
>>>>> - 1x 2-lane CSI
>>>>>
>>>>> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/
>>>>> VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
>>>>> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/
>>>>> VisionFive2Lite/VisionFive2LiteQSG/index.html
>>>>> More documents: https://doc-en.rvspace.org/Doc_Center/
>>>>> visionfive_2_lite.html
>>>>>
>>>>> Changes since v1:
>>>>> - Drop patch 1 because it is applied.
>>>>> - Rename jh7110.dtsi to jh711x.dtsi.
>>>>> - Move the content of jh7110-common.dtsi to the new file
>>>>>    jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
>>>>> patch 4:
>>>>> - Move the uncommon nodes to jh7110-common.dtsi instead of board
>> dts.
>>>>> patch 5:
>>>>> - Add jh7110s-common.dtsi and include it in jh7110s-starfive-
>>>>> visionfive-2-lite.dtsi.
>>>>>
>>>>> Changes since RFC:
>>>>> - Add jh7110s compatible to the generic cpufreq driver.
>>>>> - Fix the dtbs_check error by adding the missing "enable-gpios"
>>>>> property
>>>>>    in jh7110 pcie dt-bindings.
>>>>> - Rebase on the latest mainline.
>>>>> - Add VisionFive 2 Lite eMMC board device tree and add a common
>>>>> board dtsi
>>>>>    for VisionFive 2 Lite variants.
>>>>> - Add usb switch pin configuration (GPIO62).
>>>>> - Improve the commit messages.
>>>>>
>>>>> History:
>>>>> v1: https://lore.kernel.org/all/20251016080054.12484-1-
>>>>> hal.feng@starfivetech.com/
>>>>> RFC: https://lore.kernel.org/all/20250821100930.71404-1-
>>>>> hal.feng@starfivetech.com/
>>>>>
>>>>> Hal Feng (8):
>>>>>    dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
>>>>>    dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2
>>>>> Lite
>>>>>      board
>>>>>    riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
>>>>>    riscv: dts: starfive: Split jh7110-common.dtsi and move opp table
>>>>> to
>>>>>      it
>>>>>    riscv: dts: starfive: jh711x-common: Move out some nodes to
>>>>> jh7110
>>>>>      common dtsi
>>>>>    riscv: dts: starfive: Add common board dtsi for JH7110s and
>>>>> VisionFive
>>>>>      2 Lite variants
>>>>>    riscv: dts: starfive: Add VisionFive 2 Lite board device tree
>>>>>    riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device
>>>>> tree
>>>>>
>>>>>   .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
>>>>>   .../devicetree/bindings/riscv/starfive.yaml   |   6 +
>>>>>   arch/riscv/boot/dts/starfive/Makefile         |   3 +
>>>>>   .../boot/dts/starfive/jh7110-common.dtsi      | 653
>>>>> +----------------
>>>>>   .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
>>>>>   ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
>>>>>   .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
>>>>>   .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
>>>>>   .../boot/dts/starfive/jh711x-common.dtsi      | 656
>>>>> ++++++++++++++++++
>>>>>   .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
>>>>>   10 files changed, 879 insertions(+), 654 deletions(-)
>>>>>   create mode 100644
>>>>> arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
>>>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
>>>>> visionfive-2-lite-emmc.dts
>>>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
>>>>> visionfive-2-lite.dts
>>>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
>>>>> visionfive-2-lite.dtsi
>>>>>   create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
>>>>>   rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi}
>>>>> (99%)
>>>>>
>>>>>
>>>>> base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c
>>>>
>>>> Small nit that "lite-emmc" is confusing together. In patches to
>>>> U-Boot dev mailing list the EEPROM product id is demonstrated to be with
>> "SL"
>>>> suffix when compared to VisionFive 2 (JH7110) so I suggest avoid
>>>> confusion in upstream and use for VisionFive 2 Lite (JH7110S) these
>>>> compatible names:
>>>>
>>>> starfive,visionfive-2sl-lite
>>>> starfive,visionfive-2sl-emmc
>>>>
>>>> Also filenames:
>>>>
>>>> jh7110s-starfive-visionfive-2sl-lite.dts
>>>> jh7110s-starfive-visionfive-2sl.dtsi
>>>> jh7110s-starfive-visionfive-2sl-emmc.dts
>>>>
>>>> What do you think?
>>>>
>>>
>>> This is a serial number for the Lite board:
>>> VF7110SL-2310-D002E000-xxxxxxxx
>>>
>>> Here E000 encodes that we have no eMMC.
>>>
>>> The S is part of 7110S which we already have in 'jh7110s'. And the L
>>> is already decoded as 'lite' in this patch series. Duplicating this
>>> information as 'sl' as you suggested provides no benefit.
>>
>> The convention in dts file names is CPU model first so that will be redundant
>> or not redundant depending on the name of the product anyway; whether it
>> is redundant or not is not the driver of whether it is confusing to have
>> contradictory terminology in the product name and compatible names and dts
>> filenames.
>>
>>>
>>> Let's just stick with Hal's suggestion.
>>>
>>> Best regards
>>>
>>> Heinrich
>>
>> The "lite" product name in similar products refers to non-populated emmc
>> replaced by sd card, so there is benefit to choose a more concise name that is
>> not confusing.
>>
>> I did consider suggesting:
>>
>> jh7110s-starfive-visionfive-2-lite.dts
>> jh7110s-starfive-visionfive-2.dtsi
>> jh7110s-starfive-visionfive-2-emmc.dts
>>
>> but this is a loss of information and does not help readability. By extension
>> we're not duplicating information to be more descriptive with the product
>> name. Sure I'd go along with:
>>
>> jh7110s-starfive-visionfive-2-lite-card.dts
>> jh7110s-starfive-visionfive-2-lite.dtsi
>> jh7110s-starfive-visionfive-2-lite-emmc.dts
>>
>> But my suggestion remains:
>>
>> jh7110s-starfive-visionfive-2sl-lite.dts
>> jh7110s-starfive-visionfive-2sl.dtsi
>> jh7110s-starfive-visionfive-2sl-emmc.dts
>>
>> for the reason that it's very clearly not the "non-emmc" version of the
>> VisionFive 2. You can't mistake it if done the way I am suggesting.
> 
> VisionFive 2 Lite is not the "non-emmc" version of the VisionFive 2. "Lite" here means the
> light version and smaller size. I think we can't apply the name definition of another product
> to here. VisionFive 2 Lite is the official name of this product and the name we call in our
> official documents.
> 
> Best regards,
> Hal

Okay then LGTM, for the series,

Reviewed-by: E Shattow <e@freeshell.de>

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Conor Dooley]

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On Fri, Nov 07, 2025 at 12:21:46PM +0100, Heinrich Schuchardt wrote:
> On 11/7/25 12:11, E Shattow wrote:
> > 
> > 
> > On 11/7/25 01:55, Hal Feng wrote:
> > > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> > > SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
> > > 
> > > Board features:
> > > - JH7110S SoC
> > > - 4/8 GiB LPDDR4 DRAM
> > > - AXP15060 PMIC
> > > - 40 pin GPIO header
> > > - 1x USB 3.0 host port
> > > - 3x USB 2.0 host port
> > > - 1x M.2 M-Key (size: 2242)
> > > - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> > > - 1x QSPI Flash
> > > - 1x I2C EEPROM
> > > - 1x 1Gbps Ethernet port
> > > - SDIO-based Wi-Fi & UART-based Bluetooth
> > > - 1x HDMI port
> > > - 1x 2-lane DSI
> > > - 1x 2-lane CSI
> > > 
> > > VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> > > VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> > > More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
> > > 
> > > Changes since v1:
> > > - Drop patch 1 because it is applied.
> > > - Rename jh7110.dtsi to jh711x.dtsi.
> > > - Move the content of jh7110-common.dtsi to the new file
> > >    jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
> > > patch 4:
> > > - Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
> > > patch 5:
> > > - Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-2-lite.dtsi.
> > > 
> > > Changes since RFC:
> > > - Add jh7110s compatible to the generic cpufreq driver.
> > > - Fix the dtbs_check error by adding the missing "enable-gpios" property
> > >    in jh7110 pcie dt-bindings.
> > > - Rebase on the latest mainline.
> > > - Add VisionFive 2 Lite eMMC board device tree and add a common board dtsi
> > >    for VisionFive 2 Lite variants.
> > > - Add usb switch pin configuration (GPIO62).
> > > - Improve the commit messages.
> > > 
> > > History:
> > > v1: https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfivetech.com/
> > > RFC: https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivetech.com/
> > > 
> > > Hal Feng (8):
> > >    dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
> > >    dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
> > >      board
> > >    riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
> > >    riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to
> > >      it
> > >    riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110
> > >      common dtsi
> > >    riscv: dts: starfive: Add common board dtsi for JH7110s and VisionFive
> > >      2 Lite variants
> > >    riscv: dts: starfive: Add VisionFive 2 Lite board device tree
> > >    riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
> > > 
> > >   .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
> > >   .../devicetree/bindings/riscv/starfive.yaml   |   6 +
> > >   arch/riscv/boot/dts/starfive/Makefile         |   3 +
> > >   .../boot/dts/starfive/jh7110-common.dtsi      | 653 +----------------
> > >   .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
> > >   ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
> > >   .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
> > >   .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
> > >   .../boot/dts/starfive/jh711x-common.dtsi      | 656 ++++++++++++++++++
> > >   .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
> > >   10 files changed, 879 insertions(+), 654 deletions(-)
> > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-common.dtsi
> > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
> > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
> > >   create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> > >   rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi} (99%)
> > > 
> > > 
> > > base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c
> > 
> > Small nit that "lite-emmc" is confusing together. In patches to U-Boot
> > dev mailing list the EEPROM product id is demonstrated to be with "SL"
> > suffix when compared to VisionFive 2 (JH7110) so I suggest avoid
> > confusion in upstream and use for VisionFive 2 Lite (JH7110S) these
> > compatible names:
> > 
> > starfive,visionfive-2sl-lite
> > starfive,visionfive-2sl-emmc
> > 
> > Also filenames:
> > 
> > jh7110s-starfive-visionfive-2sl-lite.dts
> > jh7110s-starfive-visionfive-2sl.dtsi
> > jh7110s-starfive-visionfive-2sl-emmc.dts
> > 
> > What do you think?
> > 
> 
> This is a serial number for the Lite board:
> VF7110SL-2310-D002E000-xxxxxxxx
> 
> Here E000 encodes that we have no eMMC.
> 
> The S is part of 7110S which we already have in 'jh7110s'. And the L is
> already decoded as 'lite' in this patch series. Duplicating this information
> as 'sl' as you suggested provides no benefit.
> 
> Let's just stick with Hal's suggestion.

The marketing materials etc call it the visionfive 2 lite, for example
on kickstarter: https://www.kickstarter.com/projects/starfive/visionfive-2-lite-unlock-risc-v-sbc-at-199
I'm happy enough with what Hal has here as a result.

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RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

> On 08.11.25 01:20, Conor Dooley wrote:
> On Fri, Nov 07, 2025 at 12:21:46PM +0100, Heinrich Schuchardt wrote:
> > On 11/7/25 12:11, E Shattow wrote:
> > >
> > >
> > > On 11/7/25 01:55, Hal Feng wrote:
> > > > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
> > > > industrial SoC which can run at -40~85 degrees centigrade and up to
> 1.25GHz.
> > > >
> > > > Board features:
> > > > - JH7110S SoC
> > > > - 4/8 GiB LPDDR4 DRAM
> > > > - AXP15060 PMIC
> > > > - 40 pin GPIO header
> > > > - 1x USB 3.0 host port
> > > > - 3x USB 2.0 host port
> > > > - 1x M.2 M-Key (size: 2242)
> > > > - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> > > > - 1x QSPI Flash
> > > > - 1x I2C EEPROM
> > > > - 1x 1Gbps Ethernet port
> > > > - SDIO-based Wi-Fi & UART-based Bluetooth
> > > > - 1x HDMI port
> > > > - 1x 2-lane DSI
> > > > - 1x 2-lane CSI
> > > >
> > > > VisionFive 2 Lite schematics:
> > > > https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_2
> > > > 0250818_SCH.pdf VisionFive 2 Lite Quick Start Guide:
> > > > https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/inde
> > > > x.html More documents:
> > > > https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
> > > >
> > > > Changes since v1:
> > > > - Drop patch 1 because it is applied.
> > > > - Rename jh7110.dtsi to jh711x.dtsi.
> > > > - Move the content of jh7110-common.dtsi to the new file
> > > >    jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
> > > > patch 4:
> > > > - Move the uncommon nodes to jh7110-common.dtsi instead of board
> dts.
> > > > patch 5:
> > > > - Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-
> 2-lite.dtsi.
> > > >
> > > > Changes since RFC:
> > > > - Add jh7110s compatible to the generic cpufreq driver.
> > > > - Fix the dtbs_check error by adding the missing "enable-gpios" property
> > > >    in jh7110 pcie dt-bindings.
> > > > - Rebase on the latest mainline.
> > > > - Add VisionFive 2 Lite eMMC board device tree and add a common
> board dtsi
> > > >    for VisionFive 2 Lite variants.
> > > > - Add usb switch pin configuration (GPIO62).
> > > > - Improve the commit messages.
> > > >
> > > > History:
> > > > v1:
> > > > https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfi
> > > > vetech.com/
> > > > RFC:
> > > > https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfi
> > > > vetech.com/
> > > >
> > > > Hal Feng (8):
> > > >    dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
> > > >    dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
> > > >      board
> > > >    riscv: dts: starfive: Rename jh7110.dtsi to jh711x.dtsi
> > > >    riscv: dts: starfive: Split jh7110-common.dtsi and move opp table to
> > > >      it
> > > >    riscv: dts: starfive: jh711x-common: Move out some nodes to jh7110
> > > >      common dtsi
> > > >    riscv: dts: starfive: Add common board dtsi for JH7110s and VisionFive
> > > >      2 Lite variants
> > > >    riscv: dts: starfive: Add VisionFive 2 Lite board device tree
> > > >    riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device
> > > > tree
> > > >
> > > >   .../bindings/pci/starfive,jh7110-pcie.yaml    |   4 +
> > > >   .../devicetree/bindings/riscv/starfive.yaml   |   6 +
> > > >   arch/riscv/boot/dts/starfive/Makefile         |   3 +
> > > >   .../boot/dts/starfive/jh7110-common.dtsi      | 653 +----------------
> > > >   .../boot/dts/starfive/jh7110s-common.dtsi     |  27 +
> > > >   ...h7110s-starfive-visionfive-2-lite-emmc.dts |  22 +
> > > >   .../jh7110s-starfive-visionfive-2-lite.dts    |  20 +
> > > >   .../jh7110s-starfive-visionfive-2-lite.dtsi   | 126 ++++
> > > >   .../boot/dts/starfive/jh711x-common.dtsi      | 656
> ++++++++++++++++++
> > > >   .../dts/starfive/{jh7110.dtsi => jh711x.dtsi} |  16 -
> > > >   10 files changed, 879 insertions(+), 654 deletions(-)
> > > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-
> common.dtsi
> > > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
> visionfive-2-lite-emmc.dts
> > > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
> visionfive-2-lite.dts
> > > >   create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-
> visionfive-2-lite.dtsi
> > > >   create mode 100644 arch/riscv/boot/dts/starfive/jh711x-common.dtsi
> > > >   rename arch/riscv/boot/dts/starfive/{jh7110.dtsi => jh711x.dtsi}
> > > > (99%)
> > > >
> > > >
> > > > base-commit: df5d79720b152e7ff058f11ed7e88d5b5c8d2a0c
> > >
> > > Small nit that "lite-emmc" is confusing together. In patches to
> > > U-Boot dev mailing list the EEPROM product id is demonstrated to be with
> "SL"
> > > suffix when compared to VisionFive 2 (JH7110) so I suggest avoid
> > > confusion in upstream and use for VisionFive 2 Lite (JH7110S) these
> > > compatible names:
> > >
> > > starfive,visionfive-2sl-lite
> > > starfive,visionfive-2sl-emmc
> > >
> > > Also filenames:
> > >
> > > jh7110s-starfive-visionfive-2sl-lite.dts
> > > jh7110s-starfive-visionfive-2sl.dtsi
> > > jh7110s-starfive-visionfive-2sl-emmc.dts
> > >
> > > What do you think?
> > >
> >
> > This is a serial number for the Lite board:
> > VF7110SL-2310-D002E000-xxxxxxxx
> >
> > Here E000 encodes that we have no eMMC.
> >
> > The S is part of 7110S which we already have in 'jh7110s'. And the L
> > is already decoded as 'lite' in this patch series. Duplicating this
> > information as 'sl' as you suggested provides no benefit.
> >
> > Let's just stick with Hal's suggestion.
> 
> The marketing materials etc call it the visionfive 2 lite, for example on
> kickstarter: https://www.kickstarter.com/projects/starfive/visionfive-2-lite-
> unlock-risc-v-sbc-at-199
> I'm happy enough with what Hal has here as a result.

Hi, Conor,

Thanks for your review. VisionFive 2 Lite is the official name of this product,
so it is appropriate to use "starfive,visionfive-2-lite" as the compatible and
"jh7110s-starfive-visionfive-2-lite.dts" as the device tree filename.

Best regards,
Hal

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Emil Renner Berthing]

Quoting Hal Feng (2025-11-07 10:55:22)
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
>
> Board features:
> - JH7110S SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
>
> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html


Hi Hal,

Currently the JH7110 device trees are layed out like this, with a nice
separation between the SoC description and board descriptions:

jh7110.dtsi               # JH7110 SoC description
|- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
   |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
   |  |- <VF2 boards>     # Final VF2 board descriptions
   |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
   |  |- <Mars CM boards> # Final Mars CM board descriptions
   |- <other boards>      # Other JH7110 board descriptions

With this series it moves to

jh711x.dtsi
|- jh711x-common.dtsi
   |- jh7110-common.dtsi
   |  |- <jh7110 boards>
   |- jh7110s-common.dtsi
      |- <jh7110s boards>

..which I can't even give clear labels like above. In other words when new
patches are sent in it would not be easy to explain exactly where each change
should go and why.
I'm also worried that you'll find that more of the peripherals on the JH7110S
need special handling and a new jh7110s-... compatible string. Then I guess
they'll need to jump from jh7110x.dtsi two levels down to jh7110{,s}-common.dtsi
which then both describe SoC and board properties.

If you're serious about calling this a new SoC then I'd expect something more
like this:

jh711x.dtsi                  # Peripherals common to both SoCs
|- jh7110.dtsi               # JH7110 SoC description
|  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
|     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
|     |  |- <VF2 boards>     # Final VF2 board descriptions
|     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
|     |  |- <Mars CM boards> # Final Mars CM board descriptions
|     |- <other boards>      # Other JH7110 board descriptions
|- jh7110s.dtsi              # JH7110S SoC description
   |- jh7110s-common.dtsi    # Peripherals common to all JH7110S boards
      |- <JH7110S boards>    # Final JH7110S board descriptions

I know this will mean some duplication in jh7110{,s}-common.dtsi, but I would
prefer that to not having a clear explanation of what each file describes.

Do you think this layout could work for you?

/Emil

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Conor Dooley]

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On Wed, Nov 12, 2025 at 05:54:09AM -0800, Emil Renner Berthing wrote:
> Quoting Hal Feng (2025-11-07 10:55:22)
> > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> > SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
> >
> > Board features:
> > - JH7110S SoC
> > - 4/8 GiB LPDDR4 DRAM
> > - AXP15060 PMIC
> > - 40 pin GPIO header
> > - 1x USB 3.0 host port
> > - 3x USB 2.0 host port
> > - 1x M.2 M-Key (size: 2242)
> > - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> > - 1x QSPI Flash
> > - 1x I2C EEPROM
> > - 1x 1Gbps Ethernet port
> > - SDIO-based Wi-Fi & UART-based Bluetooth
> > - 1x HDMI port
> > - 1x 2-lane DSI
> > - 1x 2-lane CSI
> >
> > VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> > VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> > More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
> 
> 
> Hi Hal,
> 
> Currently the JH7110 device trees are layed out like this, with a nice
> separation between the SoC description and board descriptions:
> 
> jh7110.dtsi               # JH7110 SoC description
> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>    |  |- <VF2 boards>     # Final VF2 board descriptions
>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>    |- <other boards>      # Other JH7110 board descriptions
> 
> With this series it moves to
> 
> jh711x.dtsi

Now that you notice it, why does this have an x to begin with, when both
users have jh7110 in them? Wouldn't to just be jh7110.dtsi for both?

> |- jh711x-common.dtsi
>    |- jh7110-common.dtsi
>    |  |- <jh7110 boards>
>    |- jh7110s-common.dtsi
>       |- <jh7110s boards>

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RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

> On 12.11.25 21:54, Emil Renner Berthing wrote:
> Quoting Hal Feng (2025-11-07 10:55:22)
> > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
> > industrial SoC which can run at -40~85 degrees centigrade and up to
> 1.25GHz.
> >
> > Board features:
> > - JH7110S SoC
> > - 4/8 GiB LPDDR4 DRAM
> > - AXP15060 PMIC
> > - 40 pin GPIO header
> > - 1x USB 3.0 host port
> > - 3x USB 2.0 host port
> > - 1x M.2 M-Key (size: 2242)
> > - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> > - 1x QSPI Flash
> > - 1x I2C EEPROM
> > - 1x 1Gbps Ethernet port
> > - SDIO-based Wi-Fi & UART-based Bluetooth
> > - 1x HDMI port
> > - 1x 2-lane DSI
> > - 1x 2-lane CSI
> >
> > VisionFive 2 Lite schematics:
> > https://doc-
> en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250
> > 818_SCH.pdf VisionFive 2 Lite Quick Start Guide:
> > https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.ht
> > ml More documents:
> > https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
> 
> 
> Hi Hal,
> 
> Currently the JH7110 device trees are layed out like this, with a nice separation
> between the SoC description and board descriptions:
> 
> jh7110.dtsi               # JH7110 SoC description
> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>    |  |- <VF2 boards>     # Final VF2 board descriptions
>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>    |- <other boards>      # Other JH7110 board descriptions
> 
> With this series it moves to
> 
> jh711x.dtsi
> |- jh711x-common.dtsi
>    |- jh7110-common.dtsi
>    |  |- <jh7110 boards>
>    |- jh7110s-common.dtsi
>       |- <jh7110s boards>
> 
> ..which I can't even give clear labels like above. In other words when new
> patches are sent in it would not be easy to explain exactly where each change
> should go and why.
> I'm also worried that you'll find that more of the peripherals on the JH7110S
> need special handling and a new jh7110s-... compatible string. Then I guess
> they'll need to jump from jh7110x.dtsi two levels down to jh7110{,s}-
> common.dtsi which then both describe SoC and board properties.
> 
> If you're serious about calling this a new SoC then I'd expect something more
> like this:
> 
> jh711x.dtsi                  # Peripherals common to both SoCs
> |- jh7110.dtsi               # JH7110 SoC description
> |  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> |     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> |     |  |- <VF2 boards>     # Final VF2 board descriptions
> |     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> |     |  |- <Mars CM boards> # Final Mars CM board descriptions
> |     |- <other boards>      # Other JH7110 board descriptions
> |- jh7110s.dtsi              # JH7110S SoC description
>    |- jh7110s-common.dtsi    # Peripherals common to all JH7110S boards
>       |- <JH7110S boards>    # Final JH7110S board descriptions
> 
> I know this will mean some duplication in jh7110{,s}-common.dtsi, but I
> would prefer that to not having a clear explanation of what each file describes.
> 
> Do you think this layout could work for you?

Yeah, it is clearer for developers and maintainers.

Considering Conor's suggestion, what about:

jh7110.dtsi               # JH7110 SoC description
|- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
   |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
   |  |- <VF2 boards>     # Final VF2 board descriptions
   |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
   |  |- <Mars CM boards> # Final Mars CM board descriptions
   |- <other boards>      # Other JH7110 board descriptions
|- <JH7110S boards>

Move the opp table from jh7110.dtsi to jh7110-common.dtsi.
Remove jh7110s-common.dtsi, because only one board uses JH7110S now.

Best regards,
Hal

RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Emil Renner Berthing]

Quoting Hal Feng (2025-11-13 04:42:05)
> > On 12.11.25 21:54, Emil Renner Berthing wrote:
> > Quoting Hal Feng (2025-11-07 10:55:22)
> > > VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
> > > industrial SoC which can run at -40~85 degrees centigrade and up to
> > > 1.25GHz.
[...]
> > Currently the JH7110 device trees are layed out like this, with a nice separation
> > between the SoC description and board descriptions:
> >
> > jh7110.dtsi               # JH7110 SoC description
> > |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> >    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> >    |  |- <VF2 boards>     # Final VF2 board descriptions
> >    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> >    |  |- <Mars CM boards> # Final Mars CM board descriptions
> >    |- <other boards>      # Other JH7110 board descriptions
> >
> > With this series it moves to
> >
> > jh711x.dtsi
> > |- jh711x-common.dtsi
> >    |- jh7110-common.dtsi
> >    |  |- <jh7110 boards>
> >    |- jh7110s-common.dtsi
> >       |- <jh7110s boards>
> >
> > ..which I can't even give clear labels like above. In other words when new
> > patches are sent in it would not be easy to explain exactly where each change
> > should go and why.
> > I'm also worried that you'll find that more of the peripherals on the JH7110S
> > need special handling and a new jh7110s-... compatible string. Then I guess
> > they'll need to jump from jh7110x.dtsi two levels down to jh7110{,s}-
> > common.dtsi which then both describe SoC and board properties.
> >
> > If you're serious about calling this a new SoC then I'd expect something more
> > like this:
> >
> > jh711x.dtsi                  # Peripherals common to both SoCs
> > |- jh7110.dtsi               # JH7110 SoC description
> > |  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> > |     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> > |     |  |- <VF2 boards>     # Final VF2 board descriptions
> > |     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> > |     |  |- <Mars CM boards> # Final Mars CM board descriptions
> > |     |- <other boards>      # Other JH7110 board descriptions
> > |- jh7110s.dtsi              # JH7110S SoC description
> >    |- jh7110s-common.dtsi    # Peripherals common to all JH7110S boards
> >       |- <JH7110S boards>    # Final JH7110S board descriptions
> >
> > I know this will mean some duplication in jh7110{,s}-common.dtsi, but I
> > would prefer that to not having a clear explanation of what each file describes.
> >
> > Do you think this layout could work for you?
>
> Yeah, it is clearer for developers and maintainers.
>
> Considering Conor's suggestion, what about:
>
> jh7110.dtsi               # JH7110 SoC description
> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>    |  |- <VF2 boards>     # Final VF2 board descriptions
>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>    |- <other boards>      # Other JH7110 board descriptions
> |- <JH7110S boards>
>
> Move the opp table from jh7110.dtsi to jh7110-common.dtsi.
> Remove jh7110s-common.dtsi, because only one board uses JH7110S now.

This patchset adds 2 different boards. Has this changed?

Also this would mean that you're not using the starfive,jh7110s compatible or
any other starfive,jh7110s-.. compatible strings, so effectively you're not
treating it as a new chip, but just a board that needs a different opp table.

I see now that the opp table is effectively the only difference between the two
chips in this patchset, so if that's closer to reality then what you suggest is
fine with me.

/Emil

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[E Shattow]

On 11/13/25 02:42, Emil Renner Berthing wrote:
> Quoting Hal Feng (2025-11-13 04:42:05)
>>> On 12.11.25 21:54, Emil Renner Berthing wrote:
>>> Quoting Hal Feng (2025-11-07 10:55:22)
>>>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
>>>> industrial SoC which can run at -40~85 degrees centigrade and up to
>>>> 1.25GHz.
> [...]
>>> Currently the JH7110 device trees are layed out like this, with a nice separation
>>> between the SoC description and board descriptions:
>>>
>>> jh7110.dtsi               # JH7110 SoC description
>>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>>>    |  |- <VF2 boards>     # Final VF2 board descriptions
>>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>>>    |- <other boards>      # Other JH7110 board descriptions
>>>
>>> With this series it moves to
>>>
>>> jh711x.dtsi
>>> |- jh711x-common.dtsi
>>>    |- jh7110-common.dtsi
>>>    |  |- <jh7110 boards>
>>>    |- jh7110s-common.dtsi
>>>       |- <jh7110s boards>
>>>
>>> ..which I can't even give clear labels like above. In other words when new
>>> patches are sent in it would not be easy to explain exactly where each change
>>> should go and why.
>>> I'm also worried that you'll find that more of the peripherals on the JH7110S
>>> need special handling and a new jh7110s-... compatible string. Then I guess
>>> they'll need to jump from jh7110x.dtsi two levels down to jh7110{,s}-
>>> common.dtsi which then both describe SoC and board properties.
>>>
>>> If you're serious about calling this a new SoC then I'd expect something more
>>> like this:
>>>
>>> jh711x.dtsi                  # Peripherals common to both SoCs
>>> |- jh7110.dtsi               # JH7110 SoC description
>>> |  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>>> |     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>>> |     |  |- <VF2 boards>     # Final VF2 board descriptions
>>> |     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>>> |     |  |- <Mars CM boards> # Final Mars CM board descriptions
>>> |     |- <other boards>      # Other JH7110 board descriptions
>>> |- jh7110s.dtsi              # JH7110S SoC description
>>>    |- jh7110s-common.dtsi    # Peripherals common to all JH7110S boards
>>>       |- <JH7110S boards>    # Final JH7110S board descriptions
>>>
>>> I know this will mean some duplication in jh7110{,s}-common.dtsi, but I
>>> would prefer that to not having a clear explanation of what each file describes.
>>>
>>> Do you think this layout could work for you?
>>
>> Yeah, it is clearer for developers and maintainers.
>>
>> Considering Conor's suggestion, what about:
>>
>> jh7110.dtsi               # JH7110 SoC description
>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>>    |  |- <VF2 boards>     # Final VF2 board descriptions
>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>>    |- <other boards>      # Other JH7110 board descriptions
>> |- <JH7110S boards>
>>

JH-7110 and JH-7110I reference docs are listed (not any JH-7110S) at:
https://doc-en.rvspace.org/Doc_Center/datasheet_0.html

Does the JH-7110I use the OPP table for JH-7110 or JH-7110S?

>> Move the opp table from jh7110.dtsi to jh7110-common.dtsi.
>> Remove jh7110s-common.dtsi, because only one board uses JH7110S now.
> 
> This patchset adds 2 different boards. Has this changed?
> 
> Also this would mean that you're not using the starfive,jh7110s compatible or
> any other starfive,jh7110s-.. compatible strings, so effectively you're not
> treating it as a new chip, but just a board that needs a different opp table.
> 
> I see now that the opp table is effectively the only difference between the two
> chips in this patchset, so if that's closer to reality then what you suggest is
> fine with me.
> 
> /Emil

Are we now re-visiting Hal's suggestion then (during code review for
Milk-V Mars CM and Mars CM Lite) to split out the OPP tables and make
them per-board, as before introduction of the StarFive VisionFive 2 Lite
board(s) ?

Can we then do as from where we are now before this series:

- Move "the JH-7110" OPP table into jh7110-common-opp-1500.dtsi

- Each board jh7110-{deepcomputing,milkv,pine64,starfive}*.dts includes
said OPP dtsi file.

and for this series:

- Drop the adding of a new compatible

- Add "the JH-7110S" OPP table into jh7110-common-opp-1250.dtsi

- Use existing jh7110-* prefix for "JH-7110S" board dtsi and dts,
include jh7110-common.dtsi as usual, and include jh7110-common-opp-1250.dtsi

The exact filename pattern for the OPP tables I suggest here are
approximations, however that idea is my suggestion if we're just doing a
breakout of the tables and not a new compatible.

I am positive on having the 1250MHz OPP tables split out into dtsi
instead of stuffing them into the VisionFive 2 Lite common dtsi. That's
all it is?

-E

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Emil Renner Berthing]

Quoting E Shattow (2025-11-13 16:16:12)
>
>
> On 11/13/25 02:42, Emil Renner Berthing wrote:
> > Quoting Hal Feng (2025-11-13 04:42:05)
> >>> On 12.11.25 21:54, Emil Renner Berthing wrote:
> >>> Quoting Hal Feng (2025-11-07 10:55:22)
> >>>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
> >>>> industrial SoC which can run at -40~85 degrees centigrade and up to
> >>>> 1.25GHz.
> > [...]
> >>> Currently the JH7110 device trees are layed out like this, with a nice separation
> >>> between the SoC description and board descriptions:
> >>>
> >>> jh7110.dtsi               # JH7110 SoC description
> >>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> >>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> >>>    |  |- <VF2 boards>     # Final VF2 board descriptions
> >>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> >>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
> >>>    |- <other boards>      # Other JH7110 board descriptions
> >>>
> >>> With this series it moves to
> >>>
> >>> jh711x.dtsi
> >>> |- jh711x-common.dtsi
> >>>    |- jh7110-common.dtsi
> >>>    |  |- <jh7110 boards>
> >>>    |- jh7110s-common.dtsi
> >>>       |- <jh7110s boards>
> >>>
> >>> ..which I can't even give clear labels like above. In other words when new
> >>> patches are sent in it would not be easy to explain exactly where each change
> >>> should go and why.
> >>> I'm also worried that you'll find that more of the peripherals on the JH7110S
> >>> need special handling and a new jh7110s-... compatible string. Then I guess
> >>> they'll need to jump from jh7110x.dtsi two levels down to jh7110{,s}-
> >>> common.dtsi which then both describe SoC and board properties.
> >>>
> >>> If you're serious about calling this a new SoC then I'd expect something more
> >>> like this:
> >>>
> >>> jh711x.dtsi                  # Peripherals common to both SoCs
> >>> |- jh7110.dtsi               # JH7110 SoC description
> >>> |  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> >>> |     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> >>> |     |  |- <VF2 boards>     # Final VF2 board descriptions
> >>> |     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> >>> |     |  |- <Mars CM boards> # Final Mars CM board descriptions
> >>> |     |- <other boards>      # Other JH7110 board descriptions
> >>> |- jh7110s.dtsi              # JH7110S SoC description
> >>>    |- jh7110s-common.dtsi    # Peripherals common to all JH7110S boards
> >>>       |- <JH7110S boards>    # Final JH7110S board descriptions
> >>>
> >>> I know this will mean some duplication in jh7110{,s}-common.dtsi, but I
> >>> would prefer that to not having a clear explanation of what each file describes.
> >>>
> >>> Do you think this layout could work for you?
> >>
> >> Yeah, it is clearer for developers and maintainers.
> >>
> >> Considering Conor's suggestion, what about:
> >>
> >> jh7110.dtsi               # JH7110 SoC description
> >> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> >>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> >>    |  |- <VF2 boards>     # Final VF2 board descriptions
> >>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> >>    |  |- <Mars CM boards> # Final Mars CM board descriptions
> >>    |- <other boards>      # Other JH7110 board descriptions
> >> |- <JH7110S boards>
> >>
>
> JH-7110 and JH-7110I reference docs are listed (not any JH-7110S) at:
> https://doc-en.rvspace.org/Doc_Center/datasheet_0.html
>
> Does the JH-7110I use the OPP table for JH-7110 or JH-7110S?
>
> >> Move the opp table from jh7110.dtsi to jh7110-common.dtsi.
> >> Remove jh7110s-common.dtsi, because only one board uses JH7110S now.
> >
> > This patchset adds 2 different boards. Has this changed?
> >
> > Also this would mean that you're not using the starfive,jh7110s compatible or
> > any other starfive,jh7110s-.. compatible strings, so effectively you're not
> > treating it as a new chip, but just a board that needs a different opp table.
> >
> > I see now that the opp table is effectively the only difference between the two
> > chips in this patchset, so if that's closer to reality then what you suggest is
> > fine with me.
> >
> > /Emil
>
> Are we now re-visiting Hal's suggestion then (during code review for
> Milk-V Mars CM and Mars CM Lite) to split out the OPP tables and make
> them per-board, as before introduction of the StarFive VisionFive 2 Lite
> board(s) ?
>
> Can we then do as from where we are now before this series:
>
> - Move "the JH-7110" OPP table into jh7110-common-opp-1500.dtsi
>
> - Each board jh7110-{deepcomputing,milkv,pine64,starfive}*.dts includes
> said OPP dtsi file.
>
> and for this series:
>
> - Drop the adding of a new compatible
>
> - Add "the JH-7110S" OPP table into jh7110-common-opp-1250.dtsi
>
> - Use existing jh7110-* prefix for "JH-7110S" board dtsi and dts,
> include jh7110-common.dtsi as usual, and include jh7110-common-opp-1250.dtsi
>
> The exact filename pattern for the OPP tables I suggest here are
> approximations, however that idea is my suggestion if we're just doing a
> breakout of the tables and not a new compatible.
>
> I am positive on having the 1250MHz OPP tables split out into dtsi
> instead of stuffing them into the VisionFive 2 Lite common dtsi. That's
> all it is?

I think this suggestion makes sense if we're 100% sure the JH7110 and JH7110S
will only ever differ by the opp table. If there is any chance we'll need to add
different compatible string for some peripheral then I think Hal's suggestion
will be easier untangle. We'll even be able to do it without touching all the
board dts files once again.

I'm interested to hear Hal's opinion on this. Hopefully they'll have
more details
on the two version of the JH7110.

/Emil

RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

> On 16.11.25 00:29, Emil Renner Berthing wrote:
> Quoting E Shattow (2025-11-13 16:16:12)
> >
> >
> > On 11/13/25 02:42, Emil Renner Berthing wrote:
> > > Quoting Hal Feng (2025-11-13 04:42:05)
> > >>> On 12.11.25 21:54, Emil Renner Berthing wrote:
> > >>> Quoting Hal Feng (2025-11-07 10:55:22)
> > >>>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
> > >>>> industrial SoC which can run at -40~85 degrees centigrade and up
> > >>>> to 1.25GHz.
> > > [...]
> > >>> Currently the JH7110 device trees are layed out like this, with a
> > >>> nice separation between the SoC description and board descriptions:
> > >>>
> > >>> jh7110.dtsi               # JH7110 SoC description
> > >>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> > >>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2
> boards
> > >>>    |  |- <VF2 boards>     # Final VF2 board descriptions
> > >>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM
> boards
> > >>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
> > >>>    |- <other boards>      # Other JH7110 board descriptions
> > >>>
> > >>> With this series it moves to
> > >>>
> > >>> jh711x.dtsi
> > >>> |- jh711x-common.dtsi
> > >>>    |- jh7110-common.dtsi
> > >>>    |  |- <jh7110 boards>
> > >>>    |- jh7110s-common.dtsi
> > >>>       |- <jh7110s boards>
> > >>>
> > >>> ..which I can't even give clear labels like above. In other words
> > >>> when new patches are sent in it would not be easy to explain
> > >>> exactly where each change should go and why.
> > >>> I'm also worried that you'll find that more of the peripherals on
> > >>> the JH7110S need special handling and a new jh7110s-... compatible
> > >>> string. Then I guess they'll need to jump from jh7110x.dtsi two
> > >>> levels down to jh7110{,s}- common.dtsi which then both describe SoC
> and board properties.
> > >>>
> > >>> If you're serious about calling this a new SoC then I'd expect
> > >>> something more like this:
> > >>>
> > >>> jh711x.dtsi                  # Peripherals common to both SoCs
> > >>> |- jh7110.dtsi               # JH7110 SoC description
> > >>> |  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> > >>> |     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2
> boards
> > >>> |     |  |- <VF2 boards>     # Final VF2 board descriptions
> > >>> |     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM
> boards
> > >>> |     |  |- <Mars CM boards> # Final Mars CM board descriptions
> > >>> |     |- <other boards>      # Other JH7110 board descriptions
> > >>> |- jh7110s.dtsi              # JH7110S SoC description
> > >>>    |- jh7110s-common.dtsi    # Peripherals common to all JH7110S
> boards
> > >>>       |- <JH7110S boards>    # Final JH7110S board descriptions
> > >>>
> > >>> I know this will mean some duplication in jh7110{,s}-common.dtsi,
> > >>> but I would prefer that to not having a clear explanation of what each file
> describes.
> > >>>
> > >>> Do you think this layout could work for you?
> > >>
> > >> Yeah, it is clearer for developers and maintainers.
> > >>
> > >> Considering Conor's suggestion, what about:
> > >>
> > >> jh7110.dtsi               # JH7110 SoC description
> > >> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> > >>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> > >>    |  |- <VF2 boards>     # Final VF2 board descriptions
> > >>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> > >>    |  |- <Mars CM boards> # Final Mars CM board descriptions
> > >>    |- <other boards>      # Other JH7110 board descriptions
> > >> |- <JH7110S boards>
> > >>
> >
> > JH-7110 and JH-7110I reference docs are listed (not any JH-7110S) at:
> > https://doc-en.rvspace.org/Doc_Center/datasheet_0.html
> >
> > Does the JH-7110I use the OPP table for JH-7110 or JH-7110S?
> >
> > >> Move the opp table from jh7110.dtsi to jh7110-common.dtsi.
> > >> Remove jh7110s-common.dtsi, because only one board uses JH7110S
> now.
> > >
> > > This patchset adds 2 different boards. Has this changed?
> > >
> > > Also this would mean that you're not using the starfive,jh7110s
> > > compatible or any other starfive,jh7110s-.. compatible strings, so
> > > effectively you're not treating it as a new chip, but just a board that needs a
> different opp table.
> > >
> > > I see now that the opp table is effectively the only difference
> > > between the two chips in this patchset, so if that's closer to
> > > reality then what you suggest is fine with me.
> > >
> > > /Emil
> >
> > Are we now re-visiting Hal's suggestion then (during code review for
> > Milk-V Mars CM and Mars CM Lite) to split out the OPP tables and make
> > them per-board, as before introduction of the StarFive VisionFive 2
> > Lite
> > board(s) ?
> >
> > Can we then do as from where we are now before this series:
> >
> > - Move "the JH-7110" OPP table into jh7110-common-opp-1500.dtsi
> >
> > - Each board jh7110-{deepcomputing,milkv,pine64,starfive}*.dts
> > includes said OPP dtsi file.
> >
> > and for this series:
> >
> > - Drop the adding of a new compatible
> >
> > - Add "the JH-7110S" OPP table into jh7110-common-opp-1250.dtsi
> >
> > - Use existing jh7110-* prefix for "JH-7110S" board dtsi and dts,
> > include jh7110-common.dtsi as usual, and include
> > jh7110-common-opp-1250.dtsi
> >
> > The exact filename pattern for the OPP tables I suggest here are
> > approximations, however that idea is my suggestion if we're just doing
> > a breakout of the tables and not a new compatible.
> >
> > I am positive on having the 1250MHz OPP tables split out into dtsi
> > instead of stuffing them into the VisionFive 2 Lite common dtsi.
> > That's all it is?
> 
> I think this suggestion makes sense if we're 100% sure the JH7110 and
> JH7110S will only ever differ by the opp table. If there is any chance we'll need
> to add different compatible string for some peripheral then I think Hal's
> suggestion will be easier untangle. We'll even be able to do it without touching
> all the board dts files once again.
> 
> I'm interested to hear Hal's opinion on this. Hopefully they'll have more details
> on the two version of the JH7110.

Here are the differences between JH7110 and JH7110S: 
JH7110 supports 0~70 degrees centigrade and up to 1.5GHz.
JH7110S supports -40~85 degrees centigrade and up to 1.25GHz.

I prefer to keep "starfive,jh7110s" compatible, because "JH7110S" is the chip name
in StarFive documents and the name printed on the chip. It is easier for the users to
know which chip they are using and select the correct device tree.

And patch [1] and [2] had accepted the "starfive,jh7110s" compatible.
[1] https://lore.kernel.org/all/jurnfpufll4twv2hfp2dv6qk6d3gr7gfmek5czigb5bcon636q@opb6hrdb424p/
[2] https://lore.kernel.org/all/CAAhSdy2Jr+EoW9AZooRDa12Kx9MSSaBaDXbJUoVym1qTt3r0-Q@mail.gmail.com/

Best regards,
Hal

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[E Shattow]

On 11/16/25 22:54, Hal Feng wrote:
>> On 16.11.25 00:29, Emil Renner Berthing wrote:
>> Quoting E Shattow (2025-11-13 16:16:12)
>>>
>>>
>>> On 11/13/25 02:42, Emil Renner Berthing wrote:
>>>> Quoting Hal Feng (2025-11-13 04:42:05)
>>>>>> On 12.11.25 21:54, Emil Renner Berthing wrote:
>>>>>> Quoting Hal Feng (2025-11-07 10:55:22)
>>>>>>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
>>>>>>> industrial SoC which can run at -40~85 degrees centigrade and up
>>>>>>> to 1.25GHz.
>>>> [...]
>>>>>> Currently the JH7110 device trees are layed out like this, with a
>>>>>> nice separation between the SoC description and board descriptions:
>>>>>>
>>>>>> jh7110.dtsi               # JH7110 SoC description
>>>>>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>>>>>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2
>> boards
>>>>>>    |  |- <VF2 boards>     # Final VF2 board descriptions
>>>>>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM
>> boards
>>>>>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>>>>>>    |- <other boards>      # Other JH7110 board descriptions
>>>>>>
>>>>>> With this series it moves to
>>>>>>
>>>>>> jh711x.dtsi
>>>>>> |- jh711x-common.dtsi
>>>>>>    |- jh7110-common.dtsi
>>>>>>    |  |- <jh7110 boards>
>>>>>>    |- jh7110s-common.dtsi
>>>>>>       |- <jh7110s boards>
>>>>>>
>>>>>> ..which I can't even give clear labels like above. In other words
>>>>>> when new patches are sent in it would not be easy to explain
>>>>>> exactly where each change should go and why.
>>>>>> I'm also worried that you'll find that more of the peripherals on
>>>>>> the JH7110S need special handling and a new jh7110s-... compatible
>>>>>> string. Then I guess they'll need to jump from jh7110x.dtsi two
>>>>>> levels down to jh7110{,s}- common.dtsi which then both describe SoC
>> and board properties.
>>>>>>
>>>>>> If you're serious about calling this a new SoC then I'd expect
>>>>>> something more like this:
>>>>>>
>>>>>> jh711x.dtsi                  # Peripherals common to both SoCs
>>>>>> |- jh7110.dtsi               # JH7110 SoC description
>>>>>> |  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>>>>>> |     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2
>> boards
>>>>>> |     |  |- <VF2 boards>     # Final VF2 board descriptions
>>>>>> |     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM
>> boards
>>>>>> |     |  |- <Mars CM boards> # Final Mars CM board descriptions
>>>>>> |     |- <other boards>      # Other JH7110 board descriptions
>>>>>> |- jh7110s.dtsi              # JH7110S SoC description
>>>>>>    |- jh7110s-common.dtsi    # Peripherals common to all JH7110S
>> boards
>>>>>>       |- <JH7110S boards>    # Final JH7110S board descriptions
>>>>>>
>>>>>> I know this will mean some duplication in jh7110{,s}-common.dtsi,
>>>>>> but I would prefer that to not having a clear explanation of what each file
>> describes.
>>>>>>
>>>>>> Do you think this layout could work for you?
>>>>>
>>>>> Yeah, it is clearer for developers and maintainers.
>>>>>
>>>>> Considering Conor's suggestion, what about:
>>>>>
>>>>> jh7110.dtsi               # JH7110 SoC description
>>>>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>>>>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>>>>>    |  |- <VF2 boards>     # Final VF2 board descriptions
>>>>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>>>>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
>>>>>    |- <other boards>      # Other JH7110 board descriptions
>>>>> |- <JH7110S boards>
>>>>>
>>>
>>> JH-7110 and JH-7110I reference docs are listed (not any JH-7110S) at:
>>> https://doc-en.rvspace.org/Doc_Center/datasheet_0.html
>>>
>>> Does the JH-7110I use the OPP table for JH-7110 or JH-7110S?
>>>
>>>>> Move the opp table from jh7110.dtsi to jh7110-common.dtsi.
>>>>> Remove jh7110s-common.dtsi, because only one board uses JH7110S
>> now.
>>>>
>>>> This patchset adds 2 different boards. Has this changed?
>>>>
>>>> Also this would mean that you're not using the starfive,jh7110s
>>>> compatible or any other starfive,jh7110s-.. compatible strings, so
>>>> effectively you're not treating it as a new chip, but just a board that needs a
>> different opp table.
>>>>
>>>> I see now that the opp table is effectively the only difference
>>>> between the two chips in this patchset, so if that's closer to
>>>> reality then what you suggest is fine with me.
>>>>
>>>> /Emil
>>>
>>> Are we now re-visiting Hal's suggestion then (during code review for
>>> Milk-V Mars CM and Mars CM Lite) to split out the OPP tables and make
>>> them per-board, as before introduction of the StarFive VisionFive 2
>>> Lite
>>> board(s) ?
>>>
>>> Can we then do as from where we are now before this series:
>>>
>>> - Move "the JH-7110" OPP table into jh7110-common-opp-1500.dtsi
>>>
>>> - Each board jh7110-{deepcomputing,milkv,pine64,starfive}*.dts
>>> includes said OPP dtsi file.
>>>
>>> and for this series:
>>>
>>> - Drop the adding of a new compatible
>>>
>>> - Add "the JH-7110S" OPP table into jh7110-common-opp-1250.dtsi
>>>
>>> - Use existing jh7110-* prefix for "JH-7110S" board dtsi and dts,
>>> include jh7110-common.dtsi as usual, and include
>>> jh7110-common-opp-1250.dtsi
>>>
>>> The exact filename pattern for the OPP tables I suggest here are
>>> approximations, however that idea is my suggestion if we're just doing
>>> a breakout of the tables and not a new compatible.
>>>
>>> I am positive on having the 1250MHz OPP tables split out into dtsi
>>> instead of stuffing them into the VisionFive 2 Lite common dtsi.
>>> That's all it is?
>>
>> I think this suggestion makes sense if we're 100% sure the JH7110 and
>> JH7110S will only ever differ by the opp table. If there is any chance we'll need
>> to add different compatible string for some peripheral then I think Hal's
>> suggestion will be easier untangle. We'll even be able to do it without touching
>> all the board dts files once again.
>>
>> I'm interested to hear Hal's opinion on this. Hopefully they'll have more details
>> on the two version of the JH7110.
> 
> Here are the differences between JH7110 and JH7110S: 
> JH7110 supports 0~70 degrees centigrade and up to 1.5GHz.
> JH7110S supports -40~85 degrees centigrade and up to 1.25GHz.
> 
> I prefer to keep "starfive,jh7110s" compatible, because "JH7110S" is the chip name
> in StarFive documents and the name printed on the chip. It is easier for the users to
> know which chip they are using and select the correct device tree.
> 
> And patch [1] and [2] had accepted the "starfive,jh7110s" compatible.
> [1] https://lore.kernel.org/all/jurnfpufll4twv2hfp2dv6qk6d3gr7gfmek5czigb5bcon636q@opb6hrdb424p/
> [2] https://lore.kernel.org/all/CAAhSdy2Jr+EoW9AZooRDa12Kx9MSSaBaDXbJUoVym1qTt3r0-Q@mail.gmail.com/
> 
> Best regards,
> Hal

Hal,

OpenSBI development can accept a revert for that 1-liner of code if
needed, and anyways that new compatible was not tagged in any release
yet while also being moot because if you do use it somewhere else and
OpenSBI keeps this around it has no effect on upstream Linux using the
compatible for JH7110.

Devicetree in Linux describes hardware not related to the feelings of
customers so that should not be a concern here.

The data given for JH7110 and JH7110S does not make sense from what can
be found in published technical documentation. The technical
documentation is however lacking a chart for JH7110 from which to derive
any useful comment here.

All,

I repeat that the suggestion was made months ago (by Hal) to split out
the OPP tables per-board from the period of time when I was complaining
about 1.5GHz JH-7110 operation pushing TDP into over-temperature thermal
limit on Milk-V Mars CM SoM.

Whether or not JH7110S is a new compatible should follow precedence in
Linux development. JH-7110S is evidently the same tape-out as JH-7110
and however you deal with that in Linux is the appropriate way to deal
with that here. Selection of OPP table for correct operation will be
determined by bootloader, where, it is demonstrated by patch series sent
to U-Boot upstream to be selected ** per-board ** based on EEPROM
content as if it was any other JH-7110 board deciding dts based on
EEPROM content. Given that it is the same tape-out I do not find a valid
justification for a new compatible in the stack of adjacent software
besides going along with some kind of marketing-driven answer about
whether or not this is a new SoC.

What I care about now is that the VisionFive 2 Lite series is in good
enough shape and there's a possibility to act on this months-old
suggestion to split out the OPP tables which as we have confirmed the
JH7110S is the same SoC as JH7110 it makes a lot of sense to do.

How is it supposed to work for binned silicon in Linux?

-E

RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

> On 18.11.25 05:55, E Shattow wrote:
> On 11/16/25 22:54, Hal Feng wrote:
> >> On 16.11.25 00:29, Emil Renner Berthing wrote:
> >> Quoting E Shattow (2025-11-13 16:16:12)
> >>>
> >>>
> >>> On 11/13/25 02:42, Emil Renner Berthing wrote:
> >>>> Quoting Hal Feng (2025-11-13 04:42:05)
> >>>>>> On 12.11.25 21:54, Emil Renner Berthing wrote:
> >>>>>> Quoting Hal Feng (2025-11-07 10:55:22)
> >>>>>>> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S
> >>>>>>> industrial SoC which can run at -40~85 degrees centigrade and up
> >>>>>>> to 1.25GHz.
> >>>> [...]
> >>>>>> Currently the JH7110 device trees are layed out like this, with a
> >>>>>> nice separation between the SoC description and board descriptions:
> >>>>>>
> >>>>>> jh7110.dtsi               # JH7110 SoC description
> >>>>>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> >>>>>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to
> >>>>>> VF2
> >> boards
> >>>>>>    |  |- <VF2 boards>     # Final VF2 board descriptions
> >>>>>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM
> >> boards
> >>>>>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
> >>>>>>    |- <other boards>      # Other JH7110 board descriptions
> >>>>>>
> >>>>>> With this series it moves to
> >>>>>>
> >>>>>> jh711x.dtsi
> >>>>>> |- jh711x-common.dtsi
> >>>>>>    |- jh7110-common.dtsi
> >>>>>>    |  |- <jh7110 boards>
> >>>>>>    |- jh7110s-common.dtsi
> >>>>>>       |- <jh7110s boards>
> >>>>>>
> >>>>>> ..which I can't even give clear labels like above. In other words
> >>>>>> when new patches are sent in it would not be easy to explain
> >>>>>> exactly where each change should go and why.
> >>>>>> I'm also worried that you'll find that more of the peripherals on
> >>>>>> the JH7110S need special handling and a new jh7110s-...
> >>>>>> compatible string. Then I guess they'll need to jump from
> >>>>>> jh7110x.dtsi two levels down to jh7110{,s}- common.dtsi which
> >>>>>> then both describe SoC
> >> and board properties.
> >>>>>>
> >>>>>> If you're serious about calling this a new SoC then I'd expect
> >>>>>> something more like this:
> >>>>>>
> >>>>>> jh711x.dtsi                  # Peripherals common to both SoCs
> >>>>>> |- jh7110.dtsi               # JH7110 SoC description
> >>>>>> |  |- jh7110-common.dtsi     # Peripherals common to all JH7110
> boards
> >>>>>> |     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common
> >>>>>> |to VF2
> >> boards
> >>>>>> |     |  |- <VF2 boards>     # Final VF2 board descriptions
> >>>>>> |     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM
> >> boards
> >>>>>> |     |  |- <Mars CM boards> # Final Mars CM board descriptions
> >>>>>> |     |- <other boards>      # Other JH7110 board descriptions
> >>>>>> |- jh7110s.dtsi              # JH7110S SoC description
> >>>>>>    |- jh7110s-common.dtsi    # Peripherals common to all JH7110S
> >> boards
> >>>>>>       |- <JH7110S boards>    # Final JH7110S board descriptions
> >>>>>>
> >>>>>> I know this will mean some duplication in jh7110{,s}-common.dtsi,
> >>>>>> but I would prefer that to not having a clear explanation of what
> >>>>>> each file
> >> describes.
> >>>>>>
> >>>>>> Do you think this layout could work for you?
> >>>>>
> >>>>> Yeah, it is clearer for developers and maintainers.
> >>>>>
> >>>>> Considering Conor's suggestion, what about:
> >>>>>
> >>>>> jh7110.dtsi               # JH7110 SoC description
> >>>>> |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> >>>>>    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2
> boards
> >>>>>    |  |- <VF2 boards>     # Final VF2 board descriptions
> >>>>>    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM
> boards
> >>>>>    |  |- <Mars CM boards> # Final Mars CM board descriptions
> >>>>>    |- <other boards>      # Other JH7110 board descriptions
> >>>>> |- <JH7110S boards>
> >>>>>
> >>>
> >>> JH-7110 and JH-7110I reference docs are listed (not any JH-7110S) at:
> >>> https://doc-en.rvspace.org/Doc_Center/datasheet_0.html
> >>>
> >>> Does the JH-7110I use the OPP table for JH-7110 or JH-7110S?
> >>>
> >>>>> Move the opp table from jh7110.dtsi to jh7110-common.dtsi.
> >>>>> Remove jh7110s-common.dtsi, because only one board uses JH7110S
> >> now.
> >>>>
> >>>> This patchset adds 2 different boards. Has this changed?
> >>>>
> >>>> Also this would mean that you're not using the starfive,jh7110s
> >>>> compatible or any other starfive,jh7110s-.. compatible strings, so
> >>>> effectively you're not treating it as a new chip, but just a board
> >>>> that needs a
> >> different opp table.
> >>>>
> >>>> I see now that the opp table is effectively the only difference
> >>>> between the two chips in this patchset, so if that's closer to
> >>>> reality then what you suggest is fine with me.
> >>>>
> >>>> /Emil
> >>>
> >>> Are we now re-visiting Hal's suggestion then (during code review for
> >>> Milk-V Mars CM and Mars CM Lite) to split out the OPP tables and
> >>> make them per-board, as before introduction of the StarFive
> >>> VisionFive 2 Lite
> >>> board(s) ?
> >>>
> >>> Can we then do as from where we are now before this series:
> >>>
> >>> - Move "the JH-7110" OPP table into jh7110-common-opp-1500.dtsi
> >>>
> >>> - Each board jh7110-{deepcomputing,milkv,pine64,starfive}*.dts
> >>> includes said OPP dtsi file.
> >>>
> >>> and for this series:
> >>>
> >>> - Drop the adding of a new compatible
> >>>
> >>> - Add "the JH-7110S" OPP table into jh7110-common-opp-1250.dtsi
> >>>
> >>> - Use existing jh7110-* prefix for "JH-7110S" board dtsi and dts,
> >>> include jh7110-common.dtsi as usual, and include
> >>> jh7110-common-opp-1250.dtsi
> >>>
> >>> The exact filename pattern for the OPP tables I suggest here are
> >>> approximations, however that idea is my suggestion if we're just
> >>> doing a breakout of the tables and not a new compatible.
> >>>
> >>> I am positive on having the 1250MHz OPP tables split out into dtsi
> >>> instead of stuffing them into the VisionFive 2 Lite common dtsi.
> >>> That's all it is?
> >>
> >> I think this suggestion makes sense if we're 100% sure the JH7110 and
> >> JH7110S will only ever differ by the opp table. If there is any
> >> chance we'll need to add different compatible string for some
> >> peripheral then I think Hal's suggestion will be easier untangle.
> >> We'll even be able to do it without touching all the board dts files once
> again.
> >>
> >> I'm interested to hear Hal's opinion on this. Hopefully they'll have
> >> more details on the two version of the JH7110.
> >
> > Here are the differences between JH7110 and JH7110S:
> > JH7110 supports 0~70 degrees centigrade and up to 1.5GHz.
> > JH7110S supports -40~85 degrees centigrade and up to 1.25GHz.
> >
> > I prefer to keep "starfive,jh7110s" compatible, because "JH7110S" is
> > the chip name in StarFive documents and the name printed on the chip.
> > It is easier for the users to know which chip they are using and select the
> correct device tree.
> >
> > And patch [1] and [2] had accepted the "starfive,jh7110s" compatible.
> > [1]
> > https://lore.kernel.org/all/jurnfpufll4twv2hfp2dv6qk6d3gr7gfmek5czigb5
> > bcon636q@opb6hrdb424p/ [2]
> >
> https://lore.kernel.org/all/CAAhSdy2Jr+EoW9AZooRDa12Kx9MSSaBaDXbJUo
> Vym
> > 1qTt3r0-Q@mail.gmail.com/
> >
> > Best regards,
> > Hal
> 
> Hal,
> 
> OpenSBI development can accept a revert for that 1-liner of code if needed,
> and anyways that new compatible was not tagged in any release yet while also
> being moot because if you do use it somewhere else and OpenSBI keeps this
> around it has no effect on upstream Linux using the compatible for JH7110.
> 
> Devicetree in Linux describes hardware not related to the feelings of customers
> so that should not be a concern here.
> 
> The data given for JH7110 and JH7110S does not make sense from what can
> be found in published technical documentation. The technical documentation
> is however lacking a chart for JH7110 from which to derive any useful
> comment here.
> 
> All,
> 
> I repeat that the suggestion was made months ago (by Hal) to split out the
> OPP tables per-board from the period of time when I was complaining about
> 1.5GHz JH-7110 operation pushing TDP into over-temperature thermal limit
> on Milk-V Mars CM SoM.
> 
> Whether or not JH7110S is a new compatible should follow precedence in
> Linux development. JH-7110S is evidently the same tape-out as JH-7110 and
> however you deal with that in Linux is the appropriate way to deal with that
> here. Selection of OPP table for correct operation will be determined by
> bootloader, where, it is demonstrated by patch series sent to U-Boot
> upstream to be selected ** per-board ** based on EEPROM content as if it
> was any other JH-7110 board deciding dts based on EEPROM content. Given
> that it is the same tape-out I do not find a valid justification for a new
> compatible in the stack of adjacent software besides going along with some
> kind of marketing-driven answer about whether or not this is a new SoC.
> 
> What I care about now is that the VisionFive 2 Lite series is in good enough
> shape and there's a possibility to act on this months-old suggestion to split out
> the OPP tables which as we have confirmed the JH7110S is the same SoC as
> JH7110 it makes a lot of sense to do.
> 
> How is it supposed to work for binned silicon in Linux?

Hi, Conor,  Emil, 

What do you think about this? Hope to hear from you.

Best regards,
Hal

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Conor Dooley]

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On Tue, Nov 18, 2025 at 02:12:58AM +0000, Hal Feng wrote:
> > All,
> > 
> > I repeat that the suggestion was made months ago (by Hal) to split out the
> > OPP tables per-board from the period of time when I was complaining about
> > 1.5GHz JH-7110 operation pushing TDP into over-temperature thermal limit
> > on Milk-V Mars CM SoM.
> > 
> > Whether or not JH7110S is a new compatible should follow precedence in
> > Linux development. JH-7110S is evidently the same tape-out as JH-7110 and
> > however you deal with that in Linux is the appropriate way to deal with that
> > here. Selection of OPP table for correct operation will be determined by
> > bootloader, where, it is demonstrated by patch series sent to U-Boot
> > upstream to be selected ** per-board ** based on EEPROM content as if it
> > was any other JH-7110 board deciding dts based on EEPROM content. Given
> > that it is the same tape-out I do not find a valid justification for a new
> > compatible in the stack of adjacent software besides going along with some
> > kind of marketing-driven answer about whether or not this is a new SoC.
> > 
> > What I care about now is that the VisionFive 2 Lite series is in good enough
> > shape and there's a possibility to act on this months-old suggestion to split out
> > the OPP tables which as we have confirmed the JH7110S is the same SoC as
> > JH7110 it makes a lot of sense to do.
> > 
> > How is it supposed to work for binned silicon in Linux?
> 
> Hi, Conor,  Emil, 
> 
> What do you think about this? Hope to hear from you.

Can someone just give me a yes/no question out of this thread? I'm not
really immediately sure what's being asked of me. What exactly do you
want to do with the opp-tables? "Split out" isn't super clear. Does that
mean into board files? I am guessing it does, since you're saying that a
particular board cannot support the 1.5 GHz mode. It's not unusual
though to use delete node for unsupported opp-table entries, could that
be done instead?

FWIW, this weekend is -rc7, so I won't be applying any new material
after that.


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Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Heinrich Schuchardt]

On 11/19/25 00:10, Conor Dooley wrote:
> On Tue, Nov 18, 2025 at 02:12:58AM +0000, Hal Feng wrote:
>>> All,
>>>
>>> I repeat that the suggestion was made months ago (by Hal) to split out the
>>> OPP tables per-board from the period of time when I was complaining about
>>> 1.5GHz JH-7110 operation pushing TDP into over-temperature thermal limit
>>> on Milk-V Mars CM SoM.
>>>
>>> Whether or not JH7110S is a new compatible should follow precedence in
>>> Linux development. JH-7110S is evidently the same tape-out as JH-7110 and
>>> however you deal with that in Linux is the appropriate way to deal with that
>>> here. Selection of OPP table for correct operation will be determined by
>>> bootloader, where, it is demonstrated by patch series sent to U-Boot
>>> upstream to be selected ** per-board ** based on EEPROM content as if it
>>> was any other JH-7110 board deciding dts based on EEPROM content. Given
>>> that it is the same tape-out I do not find a valid justification for a new
>>> compatible in the stack of adjacent software besides going along with some
>>> kind of marketing-driven answer about whether or not this is a new SoC.
>>>
>>> What I care about now is that the VisionFive 2 Lite series is in good enough
>>> shape and there's a possibility to act on this months-old suggestion to split out
>>> the OPP tables which as we have confirmed the JH7110S is the same SoC as
>>> JH7110 it makes a lot of sense to do.
>>>
>>> How is it supposed to work for binned silicon in Linux?
>>
>> Hi, Conor,  Emil,
>>
>> What do you think about this? Hope to hear from you.
> 
> Can someone just give me a yes/no question out of this thread? I'm not
> really immediately sure what's being asked of me. What exactly do you
> want to do with the opp-tables? "Split out" isn't super clear. Does that
> mean into board files? I am guessing it does, since you're saying that a
> particular board cannot support the 1.5 GHz mode. It's not unusual
> though to use delete node for unsupported opp-table entries, could that
> be done instead?
> 
> FWIW, this weekend is -rc7, so I won't be applying any new material
> after that.
> 

There was agreement that the JH7110 and JH7110S need different operating 
points. This is realized via the different includes for the VisionFive 2 
Lite boards and the other boards.

Support for the new compatible string "starfive,jh7110s" used by the 
VisionFive 2 Lite is already implemented in OpenSBI where it is needed 
for platform support (specifically reboot). It is also used in tag 
next-20251119 in drivers/cpufreq/cpufreq-dt-platdev.c. There is no 
technical need to role this back.

The changes in OpenSBI and the cpu frequency driver could have been 
avoided by using

compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s", 
"starfive,jh7110"

to indicate that JH7110s is just a variety of JH7110. This also would 
match the best practice example in Documentation/devicetree/usage-model.rst:

     compatible = "ti,omap3-beagleboard", "ti,omap3450", "ti,omap3";

I guess we could add that third compatible value in a later patch.

As U-Boot uses the Linux device-trees too, I have built U-Boot with the 
updated device-trees and had no problem to boot all supported JH7110 and 
JH7110S devices including the StarFive VisionFive 2 Lite.

A bootph-pre-ram property for booting from SD-card that was already 
missing before the series can be added via a separate patch.

I think we should go ahead as is.

Best regards

Heinrich

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[E Shattow]

On 11/18/25 23:04, Heinrich Schuchardt wrote:
> On 11/19/25 00:10, Conor Dooley wrote:
>> On Tue, Nov 18, 2025 at 02:12:58AM +0000, Hal Feng wrote:
>>>> All,
>>>>
>>>> I repeat that the suggestion was made months ago (by Hal) to split
>>>> out the
>>>> OPP tables per-board from the period of time when I was complaining
>>>> about
>>>> 1.5GHz JH-7110 operation pushing TDP into over-temperature thermal
>>>> limit
>>>> on Milk-V Mars CM SoM.
>>>>
>>>> Whether or not JH7110S is a new compatible should follow precedence in
>>>> Linux development. JH-7110S is evidently the same tape-out as
>>>> JH-7110 and
>>>> however you deal with that in Linux is the appropriate way to deal
>>>> with that
>>>> here. Selection of OPP table for correct operation will be
>>>> determined by
>>>> bootloader, where, it is demonstrated by patch series sent to U-Boot
>>>> upstream to be selected ** per-board ** based on EEPROM content as
>>>> if it
>>>> was any other JH-7110 board deciding dts based on EEPROM content. Given
>>>> that it is the same tape-out I do not find a valid justification for
>>>> a new
>>>> compatible in the stack of adjacent software besides going along
>>>> with some
>>>> kind of marketing-driven answer about whether or not this is a new SoC.
>>>>
>>>> What I care about now is that the VisionFive 2 Lite series is in
>>>> good enough
>>>> shape and there's a possibility to act on this months-old suggestion
>>>> to split out
>>>> the OPP tables which as we have confirmed the JH7110S is the same
>>>> SoC as
>>>> JH7110 it makes a lot of sense to do.
>>>>
>>>> How is it supposed to work for binned silicon in Linux?
>>>
>>> Hi, Conor,  Emil,
>>>
>>> What do you think about this? Hope to hear from you.
>>
>> Can someone just give me a yes/no question out of this thread? I'm not
>> really immediately sure what's being asked of me. What exactly do you
>> want to do with the opp-tables? "Split out" isn't super clear. Does that
>> mean into board files? I am guessing it does, since you're saying that a
>> particular board cannot support the 1.5 GHz mode. It's not unusual
>> though to use delete node for unsupported opp-table entries, could that
>> be done instead?
>>
>> FWIW, this weekend is -rc7, so I won't be applying any new material
>> after that.
>>
> 
> There was agreement that the JH7110 and JH7110S need different operating
> points. This is realized via the different includes for the VisionFive 2
> Lite boards and the other boards.
> 
> Support for the new compatible string "starfive,jh7110s" used by the
> VisionFive 2 Lite is already implemented in OpenSBI where it is needed
> for platform support (specifically reboot). It is also used in tag
> next-20251119 in drivers/cpufreq/cpufreq-dt-platdev.c. There is no
> technical need to role this back.
> 
> The changes in OpenSBI and the cpu frequency driver could have been
> avoided by using
> 
> compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s",
> "starfive,jh7110"
> 
> to indicate that JH7110s is just a variety of JH7110. This also would
> match the best practice example in Documentation/devicetree/usage-
> model.rst:
> 
>     compatible = "ti,omap3-beagleboard", "ti,omap3450", "ti,omap3";
> 
> I guess we could add that third compatible value in a later patch.

No, how about doing that now instead of pushing out the wrong result?

> 
> As U-Boot uses the Linux device-trees too, I have built U-Boot with the
> updated device-trees and had no problem to boot all supported JH7110 and
> JH7110S devices including the StarFive VisionFive 2 Lite.
> 

Yes that is clear when reading the documentation, sounds good to me if
following the docs.

> A bootph-pre-ram property for booting from SD-card that was already
> missing before the series can be added via a separate patch.

You are referring to booting U-Boot SPL from SD-card. The supported
method for new designs (StarFive VisionFive 2 Lite is a new design) is
to boot U-Boot SPL from UART serial or SPI Flash. U-Boot Main has the
full unfiltered devicetree available and does in fact boot Linux from
SD-card as-is without what you refer to.

How then is U-Boot SPL boot from SD-card possible on StarFive VisionFive
2 Lite? There is only a boot button (serial or spi flash select). Is
this for a developer board with MSEL DIP, or some other boot selection
in hardware not mentioned?

> 
> I think we should go ahead as is.

This is the review feedback I wish we'd had for Hal with the RFC and v1
of this series. I would now like the identified changes to be applied to
the devicetree. It says right there in the documentation how to do it,
thank you.

> 
> Best regards
> 
> Heinrich

B.R.,

-E

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Emil Renner Berthing]

Quoting Conor Dooley (2025-11-19 00:10:08)
> On Tue, Nov 18, 2025 at 02:12:58AM +0000, Hal Feng wrote:
> > > All,
> > >
> > > I repeat that the suggestion was made months ago (by Hal) to split out the
> > > OPP tables per-board from the period of time when I was complaining about
> > > 1.5GHz JH-7110 operation pushing TDP into over-temperature thermal limit
> > > on Milk-V Mars CM SoM.
> > >
> > > Whether or not JH7110S is a new compatible should follow precedence in
> > > Linux development. JH-7110S is evidently the same tape-out as JH-7110 and
> > > however you deal with that in Linux is the appropriate way to deal with that
> > > here. Selection of OPP table for correct operation will be determined by
> > > bootloader, where, it is demonstrated by patch series sent to U-Boot
> > > upstream to be selected ** per-board ** based on EEPROM content as if it
> > > was any other JH-7110 board deciding dts based on EEPROM content. Given
> > > that it is the same tape-out I do not find a valid justification for a new
> > > compatible in the stack of adjacent software besides going along with some
> > > kind of marketing-driven answer about whether or not this is a new SoC.
> > >
> > > What I care about now is that the VisionFive 2 Lite series is in good enough
> > > shape and there's a possibility to act on this months-old suggestion to split out
> > > the OPP tables which as we have confirmed the JH7110S is the same SoC as
> > > JH7110 it makes a lot of sense to do.
> > >
> > > How is it supposed to work for binned silicon in Linux?
> >
> > Hi, Conor,  Emil,
> >
> > What do you think about this? Hope to hear from you.
>
> Can someone just give me a yes/no question out of this thread? I'm not
> really immediately sure what's being asked of me. What exactly do you
> want to do with the opp-tables? "Split out" isn't super clear. Does that
> mean into board files? I am guessing it does, since you're saying that a
> particular board cannot support the 1.5 GHz mode. It's not unusual
> though to use delete node for unsupported opp-table entries, could that
> be done instead?

Yes, as far as I can tell we should be able to just add the board description
like this:

 jh7110.dtsi               # JH7110 SoC description
 |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
    |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
    |  |- <VF2 boards>     # Final VF2 board descriptions
    |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
    |  |- <Mars CM boards> # Final Mars CM board descriptions
    |- <other boards>      # Other JH7110 board descriptions
+   |- jh7110-starfive-visionfive-2-lite.dts

and have it do

&cpu_opp {
    /delete-node/ opp-375000000;
    /delete-node/ opp-500000000;
    /delete-node/ opp-750000000;
    /delete-node/ opp-1500000000;

    opp-312500000 {
        opp-hz = /bits/ 64 <312500000>;
        opp-microvolt = <800000>;
    };
    opp-417000000 {
        opp-hz = /bits/ 64 <417000000>;
        opp-microvolt = <800000>;
    };
    opp-625000000 {
        opp-hz = /bits/ 64 <625000000>;
        opp-microvolt = <800000>;
    };
    opp-1250000000 {
        opp-hz = /bits/ 64 <1250000000>;
        opp-microvolt = <1000000>;
    };
};

This seems to be the minimal amount of changes needed. I looked through the
latest OpenSBI and it does match "starfive,jh7110s", but it treats it exactly
the same as "starfive,jh7110" and Hal have not really given any other reason
we'd need new compatible strings.

E: I know this doesn't split out the opp table like you suggested, but I think
that can come later if needed. Let's just start with the minimal amount of
changes to get the VF2 Lite supported.

Hal: Do you think this could work? You might need a patch to move some mmc
properties out of jh7110-common.dtsi

/Emil

Re: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 4681 bytes --]

On Wed, Nov 19, 2025 at 05:27:30AM -0800, Emil Renner Berthing wrote:
> Quoting Conor Dooley (2025-11-19 00:10:08)
> > On Tue, Nov 18, 2025 at 02:12:58AM +0000, Hal Feng wrote:
> > > > All,
> > > >
> > > > I repeat that the suggestion was made months ago (by Hal) to split out the
> > > > OPP tables per-board from the period of time when I was complaining about
> > > > 1.5GHz JH-7110 operation pushing TDP into over-temperature thermal limit
> > > > on Milk-V Mars CM SoM.
> > > >
> > > > Whether or not JH7110S is a new compatible should follow precedence in
> > > > Linux development. JH-7110S is evidently the same tape-out as JH-7110 and
> > > > however you deal with that in Linux is the appropriate way to deal with that
> > > > here. Selection of OPP table for correct operation will be determined by
> > > > bootloader, where, it is demonstrated by patch series sent to U-Boot
> > > > upstream to be selected ** per-board ** based on EEPROM content as if it
> > > > was any other JH-7110 board deciding dts based on EEPROM content. Given
> > > > that it is the same tape-out I do not find a valid justification for a new
> > > > compatible in the stack of adjacent software besides going along with some
> > > > kind of marketing-driven answer about whether or not this is a new SoC.
> > > >
> > > > What I care about now is that the VisionFive 2 Lite series is in good enough
> > > > shape and there's a possibility to act on this months-old suggestion to split out
> > > > the OPP tables which as we have confirmed the JH7110S is the same SoC as
> > > > JH7110 it makes a lot of sense to do.
> > > >
> > > > How is it supposed to work for binned silicon in Linux?
> > >
> > > Hi, Conor,  Emil,
> > >
> > > What do you think about this? Hope to hear from you.
> >
> > Can someone just give me a yes/no question out of this thread? I'm not
> > really immediately sure what's being asked of me. What exactly do you
> > want to do with the opp-tables? "Split out" isn't super clear. Does that
> > mean into board files? I am guessing it does, since you're saying that a
> > particular board cannot support the 1.5 GHz mode. It's not unusual
> > though to use delete node for unsupported opp-table entries, could that
> > be done instead?
> 
> Yes, as far as I can tell we should be able to just add the board description
> like this:
> 
>  jh7110.dtsi               # JH7110 SoC description
>  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>     |  |- <VF2 boards>     # Final VF2 board descriptions
>     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>     |  |- <Mars CM boards> # Final Mars CM board descriptions
>     |- <other boards>      # Other JH7110 board descriptions
> +   |- jh7110-starfive-visionfive-2-lite.dts
> 
> and have it do
> 
> &cpu_opp {
>     /delete-node/ opp-375000000;
>     /delete-node/ opp-500000000;
>     /delete-node/ opp-750000000;
>     /delete-node/ opp-1500000000;
> 
>     opp-312500000 {
>         opp-hz = /bits/ 64 <312500000>;
>         opp-microvolt = <800000>;
>     };
>     opp-417000000 {
>         opp-hz = /bits/ 64 <417000000>;
>         opp-microvolt = <800000>;
>     };
>     opp-625000000 {
>         opp-hz = /bits/ 64 <625000000>;
>         opp-microvolt = <800000>;
>     };
>     opp-1250000000 {
>         opp-hz = /bits/ 64 <1250000000>;
>         opp-microvolt = <1000000>;
>     };
> };
> 
> This seems to be the minimal amount of changes needed. I looked through the
> latest OpenSBI and it does match "starfive,jh7110s", but it treats it exactly
> the same as "starfive,jh7110" and Hal have not really given any other reason
> we'd need new compatible strings.

FWIW, chucking in the extra compatible is pretty straightforward if
there's a respin to adjust to the above file layout, so can probably
just go and do it.

> E: I know this doesn't split out the opp table like you suggested, but I think
> that can come later if needed. Let's just start with the minimal amount of
> changes to get the VF2 Lite supported.
> 
> Hal: Do you think this could work? You might need a patch to move some mmc
> properties out of jh7110-common.dtsi

I'm going to consider this "Changes Requested" then, and I'll expect
another version with the file layout above.

I was starting on my 6.19 PRs today, and I remembered that I actually
have some dts material for the second week of the merge window, so
you've got an extra week out of that Hal before it'd be 6.20 content
instead.

Cheers,
Conor.

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RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

> On 20.11.25 08:48, Conor Dooley wrote:
> On Wed, Nov 19, 2025 at 05:27:30AM -0800, Emil Renner Berthing wrote:
> > Quoting Conor Dooley (2025-11-19 00:10:08)
> > > On Tue, Nov 18, 2025 at 02:12:58AM +0000, Hal Feng wrote:
> > > > > All,
> > > > >
> > > > > I repeat that the suggestion was made months ago (by Hal) to
> > > > > split out the OPP tables per-board from the period of time when
> > > > > I was complaining about 1.5GHz JH-7110 operation pushing TDP
> > > > > into over-temperature thermal limit on Milk-V Mars CM SoM.
> > > > >
> > > > > Whether or not JH7110S is a new compatible should follow
> > > > > precedence in Linux development. JH-7110S is evidently the same
> > > > > tape-out as JH-7110 and however you deal with that in Linux is
> > > > > the appropriate way to deal with that here. Selection of OPP
> > > > > table for correct operation will be determined by bootloader,
> > > > > where, it is demonstrated by patch series sent to U-Boot
> > > > > upstream to be selected ** per-board ** based on EEPROM content
> > > > > as if it was any other JH-7110 board deciding dts based on
> > > > > EEPROM content. Given that it is the same tape-out I do not find
> > > > > a valid justification for a new compatible in the stack of adjacent
> software besides going along with some kind of marketing-driven answer
> about whether or not this is a new SoC.
> > > > >
> > > > > What I care about now is that the VisionFive 2 Lite series is in
> > > > > good enough shape and there's a possibility to act on this
> > > > > months-old suggestion to split out the OPP tables which as we
> > > > > have confirmed the JH7110S is the same SoC as
> > > > > JH7110 it makes a lot of sense to do.
> > > > >
> > > > > How is it supposed to work for binned silicon in Linux?
> > > >
> > > > Hi, Conor,  Emil,
> > > >
> > > > What do you think about this? Hope to hear from you.
> > >
> > > Can someone just give me a yes/no question out of this thread? I'm
> > > not really immediately sure what's being asked of me. What exactly
> > > do you want to do with the opp-tables? "Split out" isn't super
> > > clear. Does that mean into board files? I am guessing it does, since
> > > you're saying that a particular board cannot support the 1.5 GHz
> > > mode. It's not unusual though to use delete node for unsupported
> > > opp-table entries, could that be done instead?
> >
> > Yes, as far as I can tell we should be able to just add the board
> > description like this:
> >
> >  jh7110.dtsi               # JH7110 SoC description
> >  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
> >     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
> >     |  |- <VF2 boards>     # Final VF2 board descriptions
> >     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
> >     |  |- <Mars CM boards> # Final Mars CM board descriptions
> >     |- <other boards>      # Other JH7110 board descriptions
> > +   |- jh7110-starfive-visionfive-2-lite.dts
> >
> > and have it do
> >
> > &cpu_opp {
> >     /delete-node/ opp-375000000;
> >     /delete-node/ opp-500000000;
> >     /delete-node/ opp-750000000;
> >     /delete-node/ opp-1500000000;
> >
> >     opp-312500000 {
> >         opp-hz = /bits/ 64 <312500000>;
> >         opp-microvolt = <800000>;
> >     };
> >     opp-417000000 {
> >         opp-hz = /bits/ 64 <417000000>;
> >         opp-microvolt = <800000>;
> >     };
> >     opp-625000000 {
> >         opp-hz = /bits/ 64 <625000000>;
> >         opp-microvolt = <800000>;
> >     };
> >     opp-1250000000 {
> >         opp-hz = /bits/ 64 <1250000000>;
> >         opp-microvolt = <1000000>;
> >     };
> > };
> >
> > This seems to be the minimal amount of changes needed. I looked
> > through the latest OpenSBI and it does match "starfive,jh7110s", but
> > it treats it exactly the same as "starfive,jh7110" and Hal have not
> > really given any other reason we'd need new compatible strings.
> 
> FWIW, chucking in the extra compatible is pretty straightforward if there's a
> respin to adjust to the above file layout, so can probably just go and do it.
> 
> > E: I know this doesn't split out the opp table like you suggested, but
> > I think that can come later if needed. Let's just start with the
> > minimal amount of changes to get the VF2 Lite supported.
> >
> > Hal: Do you think this could work? You might need a patch to move some
> > mmc properties out of jh7110-common.dtsi
> 
> I'm going to consider this "Changes Requested" then, and I'll expect another
> version with the file layout above.

I will send out the new version today.

> 
> I was starting on my 6.19 PRs today, and I remembered that I actually have
> some dts material for the second week of the merge window, so you've got an
> extra week out of that Hal before it'd be 6.20 content instead.

We really hope VF2 Lite can be supported in the coming v6.19.
Wish everything goes well.

Best regard,
Hal

RE: [PATCH v2 0/8] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

> On 19.11.25 21:28, Emil Renner Berthing wrote:
> Quoting Conor Dooley (2025-11-19 00:10:08)
> > On Tue, Nov 18, 2025 at 02:12:58AM +0000, Hal Feng wrote:
> > > > All,
> > > >
> > > > I repeat that the suggestion was made months ago (by Hal) to split
> > > > out the OPP tables per-board from the period of time when I was
> > > > complaining about 1.5GHz JH-7110 operation pushing TDP into
> > > > over-temperature thermal limit on Milk-V Mars CM SoM.
> > > >
> > > > Whether or not JH7110S is a new compatible should follow
> > > > precedence in Linux development. JH-7110S is evidently the same
> > > > tape-out as JH-7110 and however you deal with that in Linux is the
> > > > appropriate way to deal with that here. Selection of OPP table for
> > > > correct operation will be determined by bootloader, where, it is
> > > > demonstrated by patch series sent to U-Boot upstream to be
> > > > selected ** per-board ** based on EEPROM content as if it was any
> > > > other JH-7110 board deciding dts based on EEPROM content. Given
> > > > that it is the same tape-out I do not find a valid justification
> > > > for a new compatible in the stack of adjacent software besides going
> along with some kind of marketing-driven answer about whether or not this is
> a new SoC.
> > > >
> > > > What I care about now is that the VisionFive 2 Lite series is in
> > > > good enough shape and there's a possibility to act on this
> > > > months-old suggestion to split out the OPP tables which as we have
> > > > confirmed the JH7110S is the same SoC as
> > > > JH7110 it makes a lot of sense to do.
> > > >
> > > > How is it supposed to work for binned silicon in Linux?
> > >
> > > Hi, Conor,  Emil,
> > >
> > > What do you think about this? Hope to hear from you.
> >
> > Can someone just give me a yes/no question out of this thread? I'm not
> > really immediately sure what's being asked of me. What exactly do you
> > want to do with the opp-tables? "Split out" isn't super clear. Does
> > that mean into board files? I am guessing it does, since you're saying
> > that a particular board cannot support the 1.5 GHz mode. It's not
> > unusual though to use delete node for unsupported opp-table entries,
> > could that be done instead?
> 
> Yes, as far as I can tell we should be able to just add the board description like
> this:
> 
>  jh7110.dtsi               # JH7110 SoC description
>  |- jh7110-common.dtsi     # Peripherals common to all JH7110 boards
>     |- jh7110-starfive-visionfive-2.dtsi # Peripherals common to VF2 boards
>     |  |- <VF2 boards>     # Final VF2 board descriptions
>     |- jh7110-milkv-marscm.dtsi # Peripherals common to Mars CM boards
>     |  |- <Mars CM boards> # Final Mars CM board descriptions
>     |- <other boards>      # Other JH7110 board descriptions
> +   |- jh7110-starfive-visionfive-2-lite.dts
> 
> and have it do
> 
> &cpu_opp {
>     /delete-node/ opp-375000000;
>     /delete-node/ opp-500000000;
>     /delete-node/ opp-750000000;
>     /delete-node/ opp-1500000000;
> 
>     opp-312500000 {
>         opp-hz = /bits/ 64 <312500000>;
>         opp-microvolt = <800000>;
>     };
>     opp-417000000 {
>         opp-hz = /bits/ 64 <417000000>;
>         opp-microvolt = <800000>;
>     };
>     opp-625000000 {
>         opp-hz = /bits/ 64 <625000000>;
>         opp-microvolt = <800000>;
>     };
>     opp-1250000000 {
>         opp-hz = /bits/ 64 <1250000000>;
>         opp-microvolt = <1000000>;
>     };
> };
> 
> This seems to be the minimal amount of changes needed. I looked through the
> latest OpenSBI and it does match "starfive,jh7110s", but it treats it exactly the
> same as "starfive,jh7110" and Hal have not really given any other reason we'd
> need new compatible strings.
> 
> E: I know this doesn't split out the opp table like you suggested, but I think
> that can come later if needed. Let's just start with the minimal amount of
> changes to get the VF2 Lite supported.
> 
> Hal: Do you think this could work? You might need a patch to move some mmc
> properties out of jh7110-common.dtsi

Yes, I will send out a new version with the file layout above today. Thank you.

Best regards,
Hal