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From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	abelvesa@kernel.org, peng.fan@nxp.com, mturquette@baylibre.com,
	sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
	festevam@gmail.com, Richard Zhu <hongxing.zhu@nxp.com>
Cc: hongxing.zhu@nxp.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
	imx@lists.linux.dev, kernel@pengutronix.de
Subject: Re: [PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block
Date: Tue, 15 Oct 2024 11:18:53 +0200	[thread overview]
Message-ID: <4963051.31r3eYUQgx@steina-w> (raw)
In-Reply-To: <1728977644-8207-3-git-send-email-hongxing.zhu@nxp.com>

Hi Richard,

Am Dienstag, 15. Oktober 2024, 09:34:04 CEST schrieb Richard Zhu:
> CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
> enable/disable.
> 
> Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF clock
> out gate.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk-imx95-blk-ctl.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c b/drivers/clk/imx/clk-imx95-blk-ctl.c
> index 19a62da74be4..25974947ad0c 100644
> --- a/drivers/clk/imx/clk-imx95-blk-ctl.c
> +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c
> @@ -277,6 +277,25 @@ static const struct imx95_blk_ctl_dev_data netcmix_dev_data = {
>  	.clk_reg_offset = 0,
>  };
>  
> +static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
> +	[0] = {
> +		.name = "hsio_blk_ctl_clk",
> +		.parent_names = (const char *[]){ "hsio_pll", },
> +		.num_parents = 1,
> +		.reg = 0,

According to RM the register LFAST_IO_REG has offset 0xc0. How does the DT node look like?
If this is the HSIO block control I would have expected this to control the whole block.

Best regards,
Alexander

> +		.bit_idx = 6,
> +		.bit_width = 1,
> +		.type = CLK_GATE,
> +		.flags = CLK_SET_RATE_PARENT,
> +	}
> +};
> +
> +static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
> +	.num_clks = 1,
> +	.clk_dev_data = hsio_blk_ctl_clk_dev_data,
> +	.clk_reg_offset = 0,
> +};
> +
>  static int imx95_bc_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> @@ -447,6 +466,7 @@ static const struct of_device_id imx95_bc_of_match[] = {
>  	{ .compatible = "nxp,imx95-display-master-csr", },
>  	{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },
>  	{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },
> +	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },
>  	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },
>  	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
>  	{ /* Sentinel */ },
> 


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  reply	other threads:[~2024-10-15  9:20 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-15  7:34 [PATCH v5 0/2] Add one clock gate for i.MX95 HSIO block Richard Zhu
2024-10-15  7:34 ` [PATCH v5 1/2] dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL Richard Zhu
2024-10-15  7:34 ` [PATCH v5 2/2] clk: imx95-blk-ctl: Add one clock gate for HSIO block Richard Zhu
2024-10-15  9:18   ` Alexander Stein [this message]
2024-10-16  2:55     ` Hongxing Zhu
2024-10-22 14:36 ` [PATCH v5 0/2] Add one clock gate for i.MX95 " Abel Vesa

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