* [PATCH v1 1/3] dt-bindings: dma: snps,dw-axi-dmac: Update resets and add snps,num-hs-if
2023-02-06 11:38 [PATCH v1 0/3] Add DMA driver for StarFive JH7110 SoC Walker Chen
@ 2023-02-06 11:38 ` Walker Chen
2023-02-07 20:58 ` Rob Herring
2023-02-06 11:38 ` [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA Walker Chen
2023-02-06 11:38 ` [PATCH v1 3/3] riscv: dts: starfive: add dma controller node Walker Chen
2 siblings, 1 reply; 9+ messages in thread
From: Walker Chen @ 2023-02-06 11:38 UTC (permalink / raw)
To: linux-riscv, dmaengine, devicetree
Cc: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, Walker Chen,
linux-kernel
Add two reset items and properties 'snps,num-hs-if'.
The DMA controller needs to be reset before being used in JH7110 SoC.
Another difference from the original version is that the hardware
handshake number of DMA can be up to 56 while the number in original
version is less than 16, and different registers are selected according
to this.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 67aa7bb6d36a..1a8d8c20e254 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -9,6 +9,7 @@ title: Synopsys DesignWare AXI DMA Controller
maintainers:
- Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
- Jee Heng Sia <jee.heng.sia@intel.com>
+ - Walker Chen <walker.chen@starfivetech.com>
description:
Synopsys DesignWare AXI DMA Controller DT Binding
@@ -21,6 +22,7 @@ properties:
enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
+ - starfive,axi-dma
reg:
minItems: 1
@@ -59,7 +61,12 @@ properties:
maximum: 8
resets:
- maxItems: 1
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: axi-rst
+ - const: ahb-rst
snps,dma-masters:
description: |
@@ -74,6 +81,14 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6]
+ snps,num-hs-if:
+ description: |
+ The number of hardware handshake. If it is more than 16,
+ CHx_CFG2 is used to configure the DMA transfer instead of CHx_CFG.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 256
+
snps,priority:
description: |
Channel priority specifier associated with the DMA channels.
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v1 1/3] dt-bindings: dma: snps,dw-axi-dmac: Update resets and add snps,num-hs-if
2023-02-06 11:38 ` [PATCH v1 1/3] dt-bindings: dma: snps,dw-axi-dmac: Update resets and add snps,num-hs-if Walker Chen
@ 2023-02-07 20:58 ` Rob Herring
2023-02-13 10:08 ` Walker Chen
0 siblings, 1 reply; 9+ messages in thread
From: Rob Herring @ 2023-02-07 20:58 UTC (permalink / raw)
To: Walker Chen
Cc: linux-riscv, dmaengine, devicetree, Eugeniy Paltsev, Vinod Koul,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt,
Emil Renner Berthing, linux-kernel
On Mon, Feb 06, 2023 at 07:38:09PM +0800, Walker Chen wrote:
> Add two reset items and properties 'snps,num-hs-if'.
> The DMA controller needs to be reset before being used in JH7110 SoC.
> Another difference from the original version is that the hardware
> handshake number of DMA can be up to 56 while the number in original
> version is less than 16, and different registers are selected according
> to this.
>
> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 67aa7bb6d36a..1a8d8c20e254 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -9,6 +9,7 @@ title: Synopsys DesignWare AXI DMA Controller
> maintainers:
> - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> - Jee Heng Sia <jee.heng.sia@intel.com>
> + - Walker Chen <walker.chen@starfivetech.com>
>
> description:
> Synopsys DesignWare AXI DMA Controller DT Binding
> @@ -21,6 +22,7 @@ properties:
> enum:
> - snps,axi-dma-1.01a
> - intel,kmb-axi-dma
> + - starfive,axi-dma
This should be SoC specific.
>
> reg:
> minItems: 1
> @@ -59,7 +61,12 @@ properties:
> maximum: 8
>
> resets:
> - maxItems: 1
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: axi-rst
> + - const: ahb-rst
'-rst' is redundant.
>
> snps,dma-masters:
> description: |
> @@ -74,6 +81,14 @@ properties:
> $ref: /schemas/types.yaml#/definitions/uint32
> enum: [0, 1, 2, 3, 4, 5, 6]
>
> + snps,num-hs-if:
> + description: |
> + The number of hardware handshake. If it is more than 16,
> + CHx_CFG2 is used to configure the DMA transfer instead of CHx_CFG.
Can't you infer this from the compatible string?
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 256
> +
> snps,priority:
> description: |
> Channel priority specifier associated with the DMA channels.
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 1/3] dt-bindings: dma: snps,dw-axi-dmac: Update resets and add snps,num-hs-if
2023-02-07 20:58 ` Rob Herring
@ 2023-02-13 10:08 ` Walker Chen
0 siblings, 0 replies; 9+ messages in thread
From: Walker Chen @ 2023-02-13 10:08 UTC (permalink / raw)
To: Rob Herring
Cc: linux-riscv, dmaengine, devicetree, Eugeniy Paltsev, Vinod Koul,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt,
Emil Renner Berthing, linux-kernel
On 2023/2/8 4:58, Rob Herring wrote:
> On Mon, Feb 06, 2023 at 07:38:09PM +0800, Walker Chen wrote:
>> Add two reset items and properties 'snps,num-hs-if'.
>> The DMA controller needs to be reset before being used in JH7110 SoC.
>> Another difference from the original version is that the hardware
>> handshake number of DMA can be up to 56 while the number in original
>> version is less than 16, and different registers are selected according
>> to this.
>>
>> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
>> ---
>> .../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++++++-
>> 1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> index 67aa7bb6d36a..1a8d8c20e254 100644
>> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> @@ -9,6 +9,7 @@ title: Synopsys DesignWare AXI DMA Controller
>> maintainers:
>> - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
>> - Jee Heng Sia <jee.heng.sia@intel.com>
>> + - Walker Chen <walker.chen@starfivetech.com>
>>
>> description:
>> Synopsys DesignWare AXI DMA Controller DT Binding
>> @@ -21,6 +22,7 @@ properties:
>> enum:
>> - snps,axi-dma-1.01a
>> - intel,kmb-axi-dma
>> + - starfive,axi-dma
>
> This should be SoC specific.
Well, so this should be 'starfive,jh7110-axi-dma'.
>
>>
>> reg:
>> minItems: 1
>> @@ -59,7 +61,12 @@ properties:
>> maximum: 8
>>
>> resets:
>> - maxItems: 1
>> + maxItems: 2
>> +
>> + reset-names:
>> + items:
>> + - const: axi-rst
>> + - const: ahb-rst
>
> '-rst' is redundant.
Okay, will be drop '-rst' in next version.
>
>>
>> snps,dma-masters:
>> description: |
>> @@ -74,6 +81,14 @@ properties:
>> $ref: /schemas/types.yaml#/definitions/uint32
>> enum: [0, 1, 2, 3, 4, 5, 6]
>>
>> + snps,num-hs-if:
>> + description: |
>> + The number of hardware handshake. If it is more than 16,
>> + CHx_CFG2 is used to configure the DMA transfer instead of CHx_CFG.
>
> Can't you infer this from the compatible string?
Yeah, maybe this is also feasible from the compatible string.
Thanks.
Best regards,
Walker
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA
2023-02-06 11:38 [PATCH v1 0/3] Add DMA driver for StarFive JH7110 SoC Walker Chen
2023-02-06 11:38 ` [PATCH v1 1/3] dt-bindings: dma: snps,dw-axi-dmac: Update resets and add snps,num-hs-if Walker Chen
@ 2023-02-06 11:38 ` Walker Chen
2023-02-10 8:59 ` Vinod Koul
2023-02-15 1:22 ` Walker Chen
2023-02-06 11:38 ` [PATCH v1 3/3] riscv: dts: starfive: add dma controller node Walker Chen
2 siblings, 2 replies; 9+ messages in thread
From: Walker Chen @ 2023-02-06 11:38 UTC (permalink / raw)
To: linux-riscv, dmaengine, devicetree
Cc: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, Walker Chen,
linux-kernel
Adding DMA reset operation in device probe, and using different
registers according to the hardware handshake number.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index a183d93bd7e2..3581810033d2 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -25,6 +25,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/types.h>
@@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
- if (chan->chip->dw->hdata->reg_map_8_channels) {
+ if (chan->chip->dw->hdata->reg_map_8_channels &&
+ !chan->chip->dw->hdata->use_cfg2) {
cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
@@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
(chan->id * DMA_APB_HS_SEL_BIT_SIZE));
reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
-
- return;
}
/*
@@ -1136,7 +1136,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
axi_chan_disable(chan);
ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
- !(val & chan_active), 1000, 10000);
+ !(val & chan_active), 1000, DMAC_TIMEOUT_US);
if (ret == -ETIMEDOUT)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
@@ -1323,6 +1323,12 @@ static int parse_device_properties(struct axi_dma_chip *chip)
chip->dw->hdata->m_data_width = tmp;
+ ret = device_property_read_u32(dev, "snps,num-hs-if", &tmp);
+ if (!ret) {
+ if (tmp > 16)
+ chip->dw->hdata->use_cfg2 = true;
+ }
+
ret = device_property_read_u32_array(dev, "snps,block-size", carr,
chip->dw->hdata->nr_channels);
if (ret)
@@ -1410,6 +1416,16 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->cfgr_clk))
return PTR_ERR(chip->cfgr_clk);
+ if (of_device_is_compatible(node, "starfive,axi-dma")) {
+ chip->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
+ if (IS_ERR(chip->resets))
+ return PTR_ERR(chip->resets);
+
+ ret = reset_control_deassert(chip->resets);
+ if (ret)
+ return ret;
+ }
+
ret = parse_device_properties(chip);
if (ret)
return ret;
@@ -1554,6 +1570,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
{ .compatible = "intel,kmb-axi-dma" },
+ { .compatible = "starfive,axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index e9d5eb0fd594..761d95691c02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -21,6 +21,7 @@
#define DMAC_MAX_CHANNELS 16
#define DMAC_MAX_MASTERS 2
#define DMAC_MAX_BLK_SIZE 0x200000
+#define DMAC_TIMEOUT_US 200000
struct dw_axi_dma_hcfg {
u32 nr_channels;
@@ -33,6 +34,7 @@ struct dw_axi_dma_hcfg {
/* Register map for DMAX_NUM_CHANNELS <= 8 */
bool reg_map_8_channels;
bool restrict_axi_burst_len;
+ bool use_cfg2;
};
struct axi_dma_chan {
@@ -70,6 +72,7 @@ struct axi_dma_chip {
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
+ struct reset_control *resets;
};
/* LLI == Linked List Item */
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA
2023-02-06 11:38 ` [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA Walker Chen
@ 2023-02-10 8:59 ` Vinod Koul
2023-02-13 13:08 ` Walker Chen
2023-02-15 1:22 ` Walker Chen
1 sibling, 1 reply; 9+ messages in thread
From: Vinod Koul @ 2023-02-10 8:59 UTC (permalink / raw)
To: Walker Chen
Cc: linux-riscv, dmaengine, devicetree, Eugeniy Paltsev, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt,
Emil Renner Berthing, linux-kernel
On 06-02-23, 19:38, Walker Chen wrote:
> Adding DMA reset operation in device probe, and using different
> registers according to the hardware handshake number.
subsystem tag is dmaengine: xxx
>
> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
> 2 files changed, 24 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index a183d93bd7e2..3581810033d2 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -25,6 +25,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/types.h>
>
> @@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>
> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> - if (chan->chip->dw->hdata->reg_map_8_channels) {
> + if (chan->chip->dw->hdata->reg_map_8_channels &&
> + !chan->chip->dw->hdata->use_cfg2) {
what about older/other platforms that dont have use_cfg2?
> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> @@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
> (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
> reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
> lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
> -
> - return;
> }
>
> /*
> @@ -1136,7 +1136,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
> axi_chan_disable(chan);
>
> ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
> - !(val & chan_active), 1000, 10000);
> + !(val & chan_active), 1000, DMAC_TIMEOUT_US);
> if (ret == -ETIMEDOUT)
> dev_warn(dchan2dev(dchan),
> "%s failed to stop\n", axi_chan_name(chan));
> @@ -1323,6 +1323,12 @@ static int parse_device_properties(struct axi_dma_chip *chip)
>
> chip->dw->hdata->m_data_width = tmp;
>
> + ret = device_property_read_u32(dev, "snps,num-hs-if", &tmp);
> + if (!ret) {
> + if (tmp > 16)
> + chip->dw->hdata->use_cfg2 = true;
> + }
> +
> ret = device_property_read_u32_array(dev, "snps,block-size", carr,
> chip->dw->hdata->nr_channels);
> if (ret)
> @@ -1410,6 +1416,16 @@ static int dw_probe(struct platform_device *pdev)
> if (IS_ERR(chip->cfgr_clk))
> return PTR_ERR(chip->cfgr_clk);
>
> + if (of_device_is_compatible(node, "starfive,axi-dma")) {
> + chip->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
> + if (IS_ERR(chip->resets))
> + return PTR_ERR(chip->resets);
> +
> + ret = reset_control_deassert(chip->resets);
> + if (ret)
> + return ret;
> + }
> +
> ret = parse_device_properties(chip);
> if (ret)
> return ret;
> @@ -1554,6 +1570,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
> static const struct of_device_id dw_dma_of_id_table[] = {
> { .compatible = "snps,axi-dma-1.01a" },
> { .compatible = "intel,kmb-axi-dma" },
> + { .compatible = "starfive,axi-dma" },
> {}
> };
> MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index e9d5eb0fd594..761d95691c02 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -21,6 +21,7 @@
> #define DMAC_MAX_CHANNELS 16
> #define DMAC_MAX_MASTERS 2
> #define DMAC_MAX_BLK_SIZE 0x200000
> +#define DMAC_TIMEOUT_US 200000
>
> struct dw_axi_dma_hcfg {
> u32 nr_channels;
> @@ -33,6 +34,7 @@ struct dw_axi_dma_hcfg {
> /* Register map for DMAX_NUM_CHANNELS <= 8 */
> bool reg_map_8_channels;
> bool restrict_axi_burst_len;
> + bool use_cfg2;
> };
>
> struct axi_dma_chan {
> @@ -70,6 +72,7 @@ struct axi_dma_chip {
> struct clk *core_clk;
> struct clk *cfgr_clk;
> struct dw_axi_dma *dw;
> + struct reset_control *resets;
> };
>
> /* LLI == Linked List Item */
> --
> 2.17.1
--
~Vinod
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA
2023-02-10 8:59 ` Vinod Koul
@ 2023-02-13 13:08 ` Walker Chen
0 siblings, 0 replies; 9+ messages in thread
From: Walker Chen @ 2023-02-13 13:08 UTC (permalink / raw)
To: Vinod Koul
Cc: linux-riscv, dmaengine, devicetree, Eugeniy Paltsev, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt,
Emil Renner Berthing, linux-kernel
On 2023/2/10 16:59, Vinod Koul wrote:
> On 06-02-23, 19:38, Walker Chen wrote:
>> Adding DMA reset operation in device probe, and using different
>> registers according to the hardware handshake number.
>
> subsystem tag is dmaengine: xxx
OK, the tag will be changed to dmaengine.
>
>>
>> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
>> ---
>> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++---
>> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++
>> 2 files changed, 24 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> index a183d93bd7e2..3581810033d2 100644
>> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> @@ -25,6 +25,7 @@
>> #include <linux/platform_device.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/property.h>
>> +#include <linux/reset.h>
>> #include <linux/slab.h>
>> #include <linux/types.h>
>>
>> @@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>>
>> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
>> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
>> - if (chan->chip->dw->hdata->reg_map_8_channels) {
>> + if (chan->chip->dw->hdata->reg_map_8_channels &&
>> + !chan->chip->dw->hdata->use_cfg2) {
>
> what about older/other platforms that dont have use_cfg2?
The use_cfg2 variable's default value is false, the original logic will not be affected.
Rob herring gave a suggestion that it is assigned according to compatible string, like that:
if (of_device_is_compatible(node, "starfive,jh7110-axi-dma")) {
...
chip->dw->hdata->use_cfg2 = true;
}
>
>> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
>> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
>> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
>> @@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set)
>> (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
>> reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE));
>> lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
>> -
>> - return;
>> }
>>
Thanks
Best regards,
Walker
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA
2023-02-06 11:38 ` [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA Walker Chen
2023-02-10 8:59 ` Vinod Koul
@ 2023-02-15 1:22 ` Walker Chen
1 sibling, 0 replies; 9+ messages in thread
From: Walker Chen @ 2023-02-15 1:22 UTC (permalink / raw)
To: linux-riscv, dmaengine, devicetree
Cc: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, linux-kernel
On 2023/2/6 19:38, Walker Chen wrote:
> Adding DMA reset operation in device probe, and using different
> registers according to the hardware handshake number.
>
> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Hi Eugeniy Paltsev / Emil,
Could you please help to review and provide comments on this patch series?
Any comments will be appreciated!
Best regards,
Walker Chen
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1 3/3] riscv: dts: starfive: add dma controller node
2023-02-06 11:38 [PATCH v1 0/3] Add DMA driver for StarFive JH7110 SoC Walker Chen
2023-02-06 11:38 ` [PATCH v1 1/3] dt-bindings: dma: snps,dw-axi-dmac: Update resets and add snps,num-hs-if Walker Chen
2023-02-06 11:38 ` [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA Walker Chen
@ 2023-02-06 11:38 ` Walker Chen
2 siblings, 0 replies; 9+ messages in thread
From: Walker Chen @ 2023-02-06 11:38 UTC (permalink / raw)
To: linux-riscv, dmaengine, devicetree
Cc: Eugeniy Paltsev, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Palmer Dabbelt, Emil Renner Berthing, Walker Chen,
linux-kernel
Adding the dma controller node for the Starfive JH7110 SoC.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index cfbaff4ea64b..1628c0f33fab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -412,6 +412,26 @@
#gpio-cells = <2>;
};
+ dma: dma-controller@16050000 {
+ compatible = "starfive,axi-dma";
+ reg = <0x0 0x16050000 0x0 0x10000>;
+ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
+ <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
+ <&stgcrg JH7110_STGRST_DMA1P_AHB>;
+ reset-names = "axi-rst", "ahb-rst";
+ interrupts = <73>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <3>;
+ snps,num-hs-if = <56>;
+ snps,block-size = <65536 65536 65536 65536>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread