[Question] PCIe bridge representation

[Question] PCIe bridge representation

[Steven A. Falco]

I have a custom embedded board using the PPC405EX.  On one of the PCIe
controllers, there is a PLX PCIe switch (PEX8613).  Downstream from that
are two ASICs.

When I attempt to load the driver for the ASICs, I get an error:

0001:43:00.0: device not available because of BAR 0 [0xa1000000-0xa1ffffff] collisions

My device tree is basically copied from the Kilauea evaluation board.
The ranges property for the host bridge is:

ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x10000000
          0x01000000 0x00000000 0x00000000 0xe8010000 0x00000000 0x00010000>;

The strange thing is, the ASICs should be assigned addresses in the
0x90000000 space, not 0xa1000000.

So I'm wondering if I need something explicit in the device tree to
describe the PCIe switch, and possibly the ASICs as well.

I'll note in passing that a previous custom board we built used a PCI bridge
chip instead of the PCIe switch.  On that board, nothing special was needed.
The addresses were allocated in 0x90000000 as expected.

	Steve

-- 
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