From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Subject: Re: [PATCHv4] mtd: gpio-nand: add device tree bindings Date: Wed, 10 Aug 2011 10:13:27 -0500 Message-ID: <4E42A017.7040608@freescale.com> References: <1312902747-21372-1-git-send-email-jamie@jamieiles.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1312902747-21372-1-git-send-email-jamie-wmLquQDDieKakBO8gow8eQ@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org To: Jamie Iles Cc: David Woodhouse , devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Artem Bityutskiy List-Id: devicetree@vger.kernel.org On 08/09/2011 10:12 AM, Jamie Iles wrote: > +Optional properties: > +- bank-width : Width (in bytes) of the device. If not present, the width > + defaults to 8 bits. "in bytes" versus "defaults to 8 bits"... > +- chip-delay : chip dependent delay for transferring data from array to > + read registers (tR). If not present then a default of 0 is used. nand_set_defaults() will set this to 20 us if you pass in zero. > +- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read > + location used to guard against bus reordering with regards to accesses to > + the GPIO's and the NAND flash data bus. If present, then after changing > + GPIO state, this register will be read to ensure that the accesses have > + completed. The driver does it before and after all cmd_ctrl byte writes, in addition to after changing the GPIO state. -Scott