* [PATCH 0/8] of/MIPS/i2c/net: Convert OCTEON to use device-tree
@ 2011-11-11 2:21 ddaney.cavm
2011-11-11 2:21 ` [PATCH 1/8] MIPS: Octeon: Add device tree source files ddaney.cavm
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: ddaney.cavm @ 2011-11-11 2:21 UTC (permalink / raw)
To: linux-mips, ralf, devicetree-discuss, grant.likely, linux-kernel
Cc: devel, David Daney, netdev, Greg Kroah-Hartman, linux-i2c,
Ben Dooks (embedded platforms), Jean Delvare (PC drivers, core),
David S. Miller
From: David Daney <david.daney@cavium.com>
This series touches several different drivers, but since OCTEON is a
MIPS based SOC, we may want to merge the whole series via Ralf's
linux-mips.org tree.
Summary of the patches:
1) Template device trees to be patched in early boot for legacy boards
that do not supply a device tree.
2) Get rid of some garbage.
3) Interrupt mapping support.
4) Patch/fix-up device tree for lagacy boards.
5) I2C bus driver.
6) MDIO bus driver.
7,8) Ethernet drivers.
Cc: "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>
Cc: "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>
Cc: linux-i2c@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: netdev@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Cc: devel@driverdev.osuosl.org
David Daney (8):
MIPS: Octeon: Add device tree source files.
MIPS: Prune some target specific code out of prom.c
MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts.
MIPS: Octeon: Initialize and fixup device tree.
i2c: Convert i2c-octeon.c to use device tree.
netdev: mdio-octeon.c: Convert to use device tree.
netdev: octeon_mgmt: Convert to use device tree.
staging: octeon_ethernet: Convert to use device tree.
.../bindings/ata/cavium-compact-flash.txt | 30 +
.../bindings/gpio/cavium-octeon-gpio.txt | 48 ++
.../devicetree/bindings/i2c/cavium-i2c.txt | 34 +
.../devicetree/bindings/mips/cavium/bootbus.txt | 126 ++++
.../devicetree/bindings/mips/cavium/ciu.txt | 26 +
.../devicetree/bindings/mips/cavium/ciu2.txt | 27 +
.../devicetree/bindings/mips/cavium/dma-engine.txt | 21 +
.../devicetree/bindings/mips/cavium/uctl.txt | 47 ++
.../devicetree/bindings/net/cavium-mdio.txt | 27 +
.../devicetree/bindings/net/cavium-mix.txt | 40 ++
.../devicetree/bindings/net/cavium-pip.txt | 98 +++
.../devicetree/bindings/serial/cavium-uart.txt | 19 +
arch/mips/Kconfig | 1 +
arch/mips/cavium-octeon/.gitignore | 2 +
arch/mips/cavium-octeon/Makefile | 16 +
arch/mips/cavium-octeon/octeon-irq.c | 188 ++++++-
arch/mips/cavium-octeon/octeon-platform.c | 699 +++++++++++++++-----
arch/mips/cavium-octeon/octeon_3xxx.dts | 571 ++++++++++++++++
arch/mips/cavium-octeon/octeon_68xx.dts | 625 +++++++++++++++++
arch/mips/cavium-octeon/setup.c | 45 ++
arch/mips/include/asm/octeon/octeon.h | 5 -
arch/mips/kernel/prom.c | 50 --
drivers/i2c/busses/i2c-octeon.c | 94 ++--
drivers/net/ethernet/octeon/octeon_mgmt.c | 312 ++++++---
drivers/net/phy/mdio-octeon.c | 89 ++-
drivers/staging/octeon/ethernet-mdio.c | 28 +-
drivers/staging/octeon/ethernet.c | 91 ++-
drivers/staging/octeon/octeon-ethernet.h | 3 +
28 files changed, 2901 insertions(+), 461 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/cavium-compact-flash.txt
create mode 100644 Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
create mode 100644 Documentation/devicetree/bindings/i2c/cavium-i2c.txt
create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt
create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt
create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu2.txt
create mode 100644 Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt
create mode 100644 Documentation/devicetree/bindings/net/cavium-mdio.txt
create mode 100644 Documentation/devicetree/bindings/net/cavium-mix.txt
create mode 100644 Documentation/devicetree/bindings/net/cavium-pip.txt
create mode 100644 Documentation/devicetree/bindings/serial/cavium-uart.txt
create mode 100644 arch/mips/cavium-octeon/.gitignore
create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts
create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts
--
1.7.2.3
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 1/8] MIPS: Octeon: Add device tree source files. 2011-11-11 2:21 [PATCH 0/8] of/MIPS/i2c/net: Convert OCTEON to use device-tree ddaney.cavm @ 2011-11-11 2:21 ` ddaney.cavm 2011-11-11 2:21 ` [PATCH 3/8] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts ddaney.cavm ` (3 subsequent siblings) 4 siblings, 0 replies; 14+ messages in thread From: ddaney.cavm @ 2011-11-11 2:21 UTC (permalink / raw) To: linux-mips, ralf, devicetree-discuss, grant.likely, linux-kernel Cc: David Daney From: David Daney <david.daney@cavium.com> The two device tree files octeon_3xxx.dts and octeon_68xx.dts are trimmed by code in a subsequent patch to reflect the hardware actually present on the board. To this end several properties that are not part of the declared bindings are added to aid in trimming off unwanted nodes. Since the device tree and the code that trims it are bound into the kernel binary, these 'marker' properties never escape into the wild, and are purely an implementation detail of the kernel early boot process. This is done for backwards compatibility with existing boards (identified by a board type enumeration value by their bootloaders). New boards will always pass a device tree from the bootloader, the built-in trees are ignored in this case. Signed-off-by: David Daney <david.daney@cavium.com> --- .../bindings/ata/cavium-compact-flash.txt | 30 + .../bindings/gpio/cavium-octeon-gpio.txt | 48 ++ .../devicetree/bindings/i2c/cavium-i2c.txt | 34 ++ .../devicetree/bindings/mips/cavium/bootbus.txt | 126 ++++ .../devicetree/bindings/mips/cavium/ciu.txt | 26 + .../devicetree/bindings/mips/cavium/ciu2.txt | 27 + .../devicetree/bindings/mips/cavium/dma-engine.txt | 21 + .../devicetree/bindings/mips/cavium/uctl.txt | 47 ++ .../devicetree/bindings/net/cavium-mdio.txt | 27 + .../devicetree/bindings/net/cavium-mix.txt | 40 ++ .../devicetree/bindings/net/cavium-pip.txt | 98 +++ .../devicetree/bindings/serial/cavium-uart.txt | 19 + arch/mips/cavium-octeon/.gitignore | 2 + arch/mips/cavium-octeon/Makefile | 13 + arch/mips/cavium-octeon/octeon_3xxx.dts | 571 ++++++++++++++++++ arch/mips/cavium-octeon/octeon_68xx.dts | 625 ++++++++++++++++++++ 16 files changed, 1754 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/cavium-compact-flash.txt create mode 100644 Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt create mode 100644 Documentation/devicetree/bindings/i2c/cavium-i2c.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/bootbus.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/ciu2.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/dma-engine.txt create mode 100644 Documentation/devicetree/bindings/mips/cavium/uctl.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mdio.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-mix.txt create mode 100644 Documentation/devicetree/bindings/net/cavium-pip.txt create mode 100644 Documentation/devicetree/bindings/serial/cavium-uart.txt create mode 100644 arch/mips/cavium-octeon/.gitignore create mode 100644 arch/mips/cavium-octeon/octeon_3xxx.dts create mode 100644 arch/mips/cavium-octeon/octeon_68xx.dts diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt new file mode 100644 index 0000000..93986a5 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt @@ -0,0 +1,30 @@ +* Compact Flash + +The Cavium Compact Flash device is connected to the Octeon Boot Bus, +and is thus a child of the Boot Bus device. It can read and write +industry standard compact flash devices. + +Properties: +- compatible: "cavium,ebt3000-compact-flash"; + + Compatibility with many Cavium evaluation boards. + +- reg: The base address of the the CF chip select banks. Depending on + the device configuration, there may be one or two banks. + +- cavium,bus-width: The width of the connection to the CF devices. Valid + values are 8 and 16. + +- cavium,true-ide: Optional, if present the CF connection is in True IDE mode. + +- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected + to this device. + +Example: + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt new file mode 100644 index 0000000..21b989a --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt @@ -0,0 +1,48 @@ +* General Purpose Input Output (GPIO) bus. + +Properties: +- compatible: "cavium,octeon-3860-gpio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the GPIO unit's register bank. + +- gpio-controller: This is a GPIO controller. + +- #gpio-cells: Must be <2>. The first cell is the GPIO pin. + +- interrupt-controller: The GPIO controller is also an interrupt + controller, any of its pins may be configured as an interrupt + source. + +- #interrupt-cells: Must be <2>. The first cell is the GPIO pin + connected to the interrupt source. The second cell is the interrupt + triggering protocol and may have one of four values: + 1 - edge triggered on the rising edge. + 2 - edge triggered on the falling edge + 4 - level triggered active high. + 8 - level triggered active low. + +- interrupts: Interrupt routing for pin 0. The remaining pins are + also routed, but in a manner that can be derived from the pin0 + routing, so they are not specified. + +Example: + + gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>; + }; diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt new file mode 100644 index 0000000..dced82e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt @@ -0,0 +1,34 @@ +* Two Wire Serial Interface (TWSI) / I2C + +- compatible: "cavium,octeon-3860-twsi" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the TWSI/I2C bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. I2C addresses have no size component. + +- interrupts: A single interrupt specifier. + +- clock-frequency: The I2C bus clock rate in Hz. + +Example: + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt new file mode 100644 index 0000000..6581478 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt @@ -0,0 +1,126 @@ +* Boot Bus + +The Octeon Boot Bus is a configurable parallel bus with 8 chip +selects. Each chip select is independently configurable. + +Properties: +- compatible: "cavium,octeon-3860-bootbus" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the Boot Bus' register bank. + +- #address-cells: Must be <2>. The first cell is the chip select + within the bootbus. The second cell is the offset from the chip select. + +- #size-cells: Must be <1>. + +- ranges: There must be one one triplet of (child-bus-address, + parent-bus-address, length) for each active chip select. If the + length element for any triplet is zero, the chip select is disabled, + making it inactive. + +The configuration parameters for each chip select are stored in child +nodes. + +Configuration Properties: +- compatible: "cavium,octeon-3860-bootbus-config" + +- cavium,cs-index: A single cell indicating the chip select that + corresponds to this configuration. + +- cavium,t-adr: A cell specifying the ADR timing (in nS). + +- cavium,t-ce: A cell specifying the CE timing (in nS). + +- cavium,t-oe: A cell specifying the OE timing (in nS). + +- cavium,t-we: A cell specifying the WE timing (in nS). + +- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). + +- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). + +- cavium,t-pause: A cell specifying the PAUSE timing (in nS). + +- cavium,t-wait: A cell specifying the WAIT timing (in nS). + +- cavium,t-page: A cell specifying the PAGE timing (in nS). + +- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). + +- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 + = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). + +- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. + +- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. + +- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of + the bus for this chip select. + +- cavium,ale-mode: Optional. If present, ALE mode is selected. + +- cavium,sam-mode: Optional. If present, SAM mode is selected. + +- cavium,or-mode: Optional. If present, OR mode is selected. + +Example: + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + . + . + . + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + . + . + . + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt new file mode 100644 index 0000000..2c2d074 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt @@ -0,0 +1,26 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-3860-ciu" + + Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value of 0 or 1. The second cell is the bit + within the bank and may have a value between 0 and 63. + +Example: + interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt new file mode 100644 index 0000000..0ec7ba8 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt @@ -0,0 +1,27 @@ +* Central Interrupt Unit + +Properties: +- compatible: "cavium,octeon-6880-ciu2" + + Compatibility with 68XX SOCs. + +- interrupt-controller: This is an interrupt controller. + +- reg: The base address of the CIU's register bank. + +- #interrupt-cells: Must be <2>. The first cell is the bank within + the CIU and may have a value between 0 and 63. The second cell is + the bit within the bank and may also have a value between 0 and 63. + +Example: + interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0..63) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt new file mode 100644 index 0000000..cb4291e --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt @@ -0,0 +1,21 @@ +* DMA Engine. + +The Octeon DMA Engine transfers between the Boot Bus and main memory. +The DMA Engine will be refered to by phandle by any device that is +connected to it. + +Properties: +- compatible: "cavium,octeon-5750-bootbus-dma" + + Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. + +- reg: The base address of the DMA Engine's register bank. + +- interrupts: A single interrupt specifier. + +Example: + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt new file mode 100644 index 0000000..5dabe02 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/uctl.txt @@ -0,0 +1,47 @@ +* UCTL USB controller glue + +Properties: +- compatible: "cavium,octeon-6335-uctl" + + Compatibility with all cn6XXX SOCs. + +- reg: The base address of the UCTL register bank. + +- #address-cells: Must be <2>. + +- #size-cells: Must be <2>. + +- ranges: Empty to signify direct mapping of the children. + +- refclk-frequency: A single cell containing the reference clock + frequency in Hz. + +- refclk-type: A string describing the reference clock connection + either "crystal" or "external". + +Example: + uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <24000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt new file mode 100644 index 0000000..04cb749 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt @@ -0,0 +1,27 @@ +* System Management Interface (SMI) / MDIO + +Properties: +- compatible: "cavium,octeon-3860-mdio" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the MDIO bus controller register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. MDIO addresses have no size component. + +Typically an MDIO bus might have several children. + +Example: + mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + ethernet-phy@0 { + ... + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt new file mode 100644 index 0000000..e4f9d3c --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mix.txt @@ -0,0 +1,40 @@ +* MIX Ethernet controller. + +Properties: +- compatible: "cavium,octeon-5750-mix" + + Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX + devices. + +- reg: The base addresses of four separate register banks. The first + bank contains the MIX registers. The second bank the corresponding + AGL registers. The third bank are the AGL registers shared by all + MIX devices present. The fourth bank is the AGL_PRT_CTL shared by + all MIX devices present. + +- cell-index: A single cell specifying which portion of the shared + register banks corresponds to this MIX device. + +- interrupts: Two interrupt specifiers. The first is the MIX + interrupt routing and the second the routing for the AGL interrupts. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 0f b7 10 63 54 ]; + phy-handle = <&phy1>; + }; + diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt new file mode 100644 index 0000000..d4c53ba --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-pip.txt @@ -0,0 +1,98 @@ +* PIP Ethernet nexus. + +The PIP Ethernet nexus can control several data packet input/output +devices. The devices have a two level grouping scheme. There may be +several interfaces, and each interface may have several ports. These +ports might be an individual Ethernet PHY. + + +Properties for the PIP nexus: +- compatible: "cavium,octeon-3860-pip" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the PIP's register bank. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP interfaces which is a child the PIP nexus: +- compatible: "cavium,octeon-3860-pip-interface" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The interface number. + +- #address-cells: Must be <1>. + +- #size-cells: Must be <0>. + +Properties for PIP port which is a child the PIP interface: +- compatible: "cavium,octeon-3860-pip-port" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The port number within the interface group. + +- mac-address: Optional, the MAC address to assign to the device. + +- local-mac-address: Optional, the MAC address to assign to the device + if mac-address is not specified. + +- phy-handle: Optional, a phandle for the PHY device connected to this device. + +Example: + + pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 60 ]; + phy-handle = <&phy2>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 61 ]; + phy-handle = <&phy3>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 62 ]; + phy-handle = <&phy4>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 63 ]; + phy-handle = <&phy5>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 0f b7 10 63 64 ]; + phy-handle = <&phy6>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt new file mode 100644 index 0000000..87a6c37 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cavium-uart.txt @@ -0,0 +1,19 @@ +* Universal Asynchronous Receiver/Transmitter (UART) + +- compatible: "cavium,octeon-3860-uart" + + Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. + +- reg: The base address of the UART register bank. + +- interrupts: A single interrupt specifier. + +- current-speed: Optional, the current bit rate in bits per second. + +Example: + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + current-speed = <115200>; + interrupts = <0 35>; + }; diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore new file mode 100644 index 0000000..39c9686 --- /dev/null +++ b/arch/mips/cavium-octeon/.gitignore @@ -0,0 +1,2 @@ +*.dtb.S +*.dtb diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 19eb043..5e25dce 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -15,3 +15,16 @@ obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o + +DTS_FILES = octeon_3xxx.dts octeon_68xx.dts +DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) + +obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) + +$(obj)/%.dtb: $(src)/%.dts + $(call cmd,dtc) + +# Let's keep the .dtb files around in case we want to look at them. +.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) + +clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts new file mode 100644 index 0000000..e0fb0e3 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_3xxx.dts @@ -0,0 +1,571 @@ +/dts-v1/; +/* + * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-3860"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>; /* <0 17> <0 18> <0 19> + <0 20> <0 21> <0 22> <0 23> + <0 24> <0 25> <0 26> <0 27> + <0 28> <0 29> <0 30> <0 31>; */ + }; + + smi0: mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + + phy0: ethernet-phy@0 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <1>; + }; + + phy2: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy7: ethernet-phy@7 { + reg = <7>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy9: ethernet-phy@9 { + reg = <9>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000001900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001900 0x0 0x40>; + + phy100: ethernet-phy@1 { + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy101: ethernet-phy@2 { + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy102: ethernet-phy@3 { + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + phy103: ethernet-phy@4 { + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + interrupt-parent = <&gpio>; + interrupts = <12 8>; /* Pin 12, active low */ + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <0 62>, <1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + mix1: ethernet@1070000100800 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ + <0x11800 0xE0000800 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <1>; + interrupts = <1 18>, < 1 46>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + cavium,alt-phy-handle = <&phy100>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + cavium,alt-phy-handle = <&phy101>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + cavium,alt-phy-handle = <&phy102>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy5>; + cavium,alt-phy-handle = <&phy103>; + }; + ethernet@4 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x4>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@5 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x5>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@6 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x6>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@7 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x7>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@8 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x8>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@9 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x9>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@a { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xa>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@b { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xb>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@c { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xc>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@d { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xd>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@e { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xe>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@f { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0xf>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy6>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy7>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy8>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy9>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <0 59>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 34>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 35>; + }; + + uart2: serial@1180000000400 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000400 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <1 16>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + cf0: compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <0 56>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + mix1 = &mix1; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uart2 = &uart2; + flash0 = &flash0; + cf0 = &cf0; + uctl = &uctl; + led0 = &led0; + }; + }; diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts new file mode 100644 index 0000000..bde6b23 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon_68xx.dts @@ -0,0 +1,625 @@ +/dts-v1/; +/* + * OCTEON 68XX device tree skeleton. + * + * This device tree is pruned and patched by early boot code before + * use. Because of this, it contains a super-set of the available + * devices and properties. + */ +/ { + compatible = "cavium,octeon-6880"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu2>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu2: interrupt-controller@1070100000000 { + compatible = "cavium,octeon-6880-ciu2"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 7) + * 2) Bit within the register (0..63) + */ + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x10701 0x00000000 0x0 0x4000000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pins connect to 16 consecutive CUI bits */ + interrupts = <7 0>; /* <7 1> <7 2> <7 3> + <7 4> <7 5> <7 6> <7 7> + <7 8> <7 9> <7 10> <7 11> + <7 12> <7 13> <7 14> <7 15>; */ + }; + + smi0: mdio@1180000003800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003800 0x0 0x40>; + + phy0: ethernet-phy@6 { + compatible = "marvell,88e1118"; + marvell,reg-init = + /* Fix rx and tx clock transition timing */ + <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ + /* Adjust LED drive. */ + <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ + /* irq, blink-activity, blink-link */ + <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ + reg = <6>; + }; + + phy1: ethernet-phy@1 { + cavium,qlm-trim = "4,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy2: ethernet-phy@2 { + cavium,qlm-trim = "4,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy3: ethernet-phy@3 { + cavium,qlm-trim = "4,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy4: ethernet-phy@4 { + cavium,qlm-trim = "4,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi1: mdio@1180000003880 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003880 0x0 0x40>; + + phy41: ethernet-phy@1 { + cavium,qlm-trim = "0,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy42: ethernet-phy@2 { + cavium,qlm-trim = "0,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy43: ethernet-phy@3 { + cavium,qlm-trim = "0,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy44: ethernet-phy@4 { + cavium,qlm-trim = "0,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi2: mdio@1180000003900 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003900 0x0 0x40>; + + phy21: ethernet-phy@1 { + cavium,qlm-trim = "2,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy22: ethernet-phy@2 { + cavium,qlm-trim = "2,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy23: ethernet-phy@3 { + cavium,qlm-trim = "2,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy24: ethernet-phy@4 { + cavium,qlm-trim = "2,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + smi3: mdio@1180000003980 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00003980 0x0 0x40>; + + phy11: ethernet-phy@1 { + cavium,qlm-trim = "3,sgmii"; + reg = <1>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy12: ethernet-phy@2 { + cavium,qlm-trim = "3,sgmii"; + reg = <2>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy13: ethernet-phy@3 { + cavium,qlm-trim = "3,sgmii"; + reg = <3>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + phy14: ethernet-phy@4 { + cavium,qlm-trim = "3,sgmii"; + reg = <4>; + compatible = "marvell,88e1149r"; + marvell,reg-init = <3 0x10 0 0x5777>, + <3 0x11 0 0x00aa>, + <3 0x12 0 0x4105>, + <3 0x13 0 0x0a60>; + }; + }; + + mix0: ethernet@1070000100000 { + compatible = "cavium,octeon-5750-mix"; + reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ + <0x11800 0xE0000000 0x0 0x300>, /* AGL */ + <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ + <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ + cell-index = <0>; + interrupts = <6 40>, <6 32>; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy0>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@4 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy1>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy2>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy3>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy4>; + }; + }; + + interface@3 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy11>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy12>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy13>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy14>; + }; + }; + + interface@2 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy21>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy22>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy23>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy24>; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy41>; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy42>; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy43>; + }; + ethernet@3 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x3>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&phy44>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <3 32>; + clock-frequency = <100000>; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + tmp@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + twsi1: i2c@1180000001200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001200 0x0 0x200>; + interrupts = <3 33>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 36>; + }; + + uart1: serial@1180000000c00 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000c00 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <3 37>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0 0x1d020000 0x10000>, + <5 0 0 0x1d040000 0x10000>, + <6 0 0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <10>; + cavium,t-ce = <50>; + cavium,t-oe = <50>; + cavium,t-we = <35>; + cavium,t-rd-hld = <25>; + cavium,t-wr-hld = <35>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <25>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <0>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <300>; + cavium,t-pause = <0>; + cavium,t-wait = <300>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <0>; + cavium,t-ce = <30>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <310>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0 0x200000>; + read-only; + }; + partition@200000 { + label = "kernel"; + reg = <0x200000 0x200000>; + }; + partition@400000 { + label = "cramfs"; + reg = <0x400000 0x3fe000>; + }; + partition@7fe000 { + label = "environment"; + reg = <0x7fe000 0x2000>; + read-only; + }; + }; + + led0: led-display@4,0 { + compatible = "avago,hdsp-253x"; + reg = <4 0x20 0x20>, <4 0 0x20>; + }; + + compact-flash@5,0 { + compatible = "cavium,ebt3000-compact-flash"; + reg = <5 0 0x10000>, <6 0 0x10000>; + cavium,bus-width = <16>; + cavium,true-ide; + cavium,dma-engine-handle = <&dma0>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + uctl: uctl@118006f000000 { + compatible = "cavium,octeon-6335-uctl"; + reg = <0x11800 0x6f000000 0x0 0x100>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + /* 12MHz, 24MHz and 48MHz allowed */ + refclk-frequency = <12000000>; + /* Either "crystal" or "external" */ + refclk-type = "crystal"; + + ehci@16f0000000000 { + compatible = "cavium,octeon-6335-ehci","usb-ehci"; + reg = <0x16f00 0x00000000 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + ohci@16f0000000400 { + compatible = "cavium,octeon-6335-ohci","usb-ohci"; + reg = <0x16f00 0x00000400 0x0 0x100>; + interrupts = <3 44>; + big-endian-regs; + }; + }; + }; + + aliases { + mix0 = &mix0; + pip = &pip; + smi0 = &smi0; + smi1 = &smi1; + smi2 = &smi2; + smi3 = &smi3; + twsi0 = &twsi0; + twsi1 = &twsi1; + uart0 = &uart0; + uart1 = &uart1; + uctl = &uctl; + led0 = &led0; + flash0 = &flash0; + }; + }; -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/8] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. 2011-11-11 2:21 [PATCH 0/8] of/MIPS/i2c/net: Convert OCTEON to use device-tree ddaney.cavm 2011-11-11 2:21 ` [PATCH 1/8] MIPS: Octeon: Add device tree source files ddaney.cavm @ 2011-11-11 2:21 ` ddaney.cavm [not found] ` <1320978124-13042-4-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> [not found] ` <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> ` (2 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: ddaney.cavm @ 2011-11-11 2:21 UTC (permalink / raw) To: linux-mips, ralf, devicetree-discuss, grant.likely, linux-kernel Cc: David Daney From: David Daney <david.daney@cavium.com> This is needed for Octeon to use the Device Tree. The GPIO interrupts are configured based on Device Tree properties Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/cavium-octeon/octeon-irq.c | 188 +++++++++++++++++++++++++++++++++- 1 files changed, 187 insertions(+), 1 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index ffd4ae6..bb10546 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -8,11 +8,14 @@ #include <linux/interrupt.h> #include <linux/bitops.h> +#include <linux/module.h> #include <linux/percpu.h> +#include <linux/of_irq.h> #include <linux/irq.h> #include <linux/smp.h> #include <asm/octeon/octeon.h> +#include <asm/octeon/cvmx-gpio-defs.h> static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); @@ -58,6 +61,95 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, octeon_irq_ciu_to_irq[line][bit] = irq; } +static unsigned int octeon_irq_gpio_mapping(struct device_node *controller, + const u32 *intspec, + unsigned int intsize) +{ + struct of_irq oirq; + int i; + unsigned int irq = 0; + unsigned int type; + unsigned int ciu = 0, bit = 0; + unsigned int pin = be32_to_cpup(intspec); + unsigned int trigger = be32_to_cpup(intspec + 1); + bool set_edge_handler = false; + + if (pin >= 16) + goto err; + i = of_irq_map_one(controller, 0, &oirq); + if (i) + goto err; + if (oirq.size != 2) + goto err_put; + + ciu = oirq.specifier[0]; + bit = oirq.specifier[1] + pin; + + if (ciu >= 8 || bit >= 64) + goto err_put; + + irq = octeon_irq_ciu_to_irq[ciu][bit]; + if (!irq) + goto err_put; + + switch (trigger & 0xf) { + case 1: + type = IRQ_TYPE_EDGE_RISING; + set_edge_handler = true; + break; + case 2: + type = IRQ_TYPE_EDGE_FALLING; + set_edge_handler = true; + break; + case 4: + type = IRQ_TYPE_LEVEL_HIGH; + break; + case 8: + type = IRQ_TYPE_LEVEL_LOW; + break; + default: + pr_err("Error: Invalid irq trigger specification: %x\n", + trigger); + type = IRQ_TYPE_LEVEL_LOW; + break; + } + + irq_set_irq_type(irq, type); + + if (set_edge_handler) + __irq_set_handler(irq, handle_edge_irq, 0, NULL); + +err_put: + of_node_put(oirq.controller); +err: + return irq; +} + +/* + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# + * + * Octeon irq maps are a pair of indexes. The first selects either + * ciu0 or ciu1, the second is the bit within the ciu register. + */ +unsigned int irq_create_of_mapping(struct device_node *controller, + const u32 *intspec, unsigned int intsize) +{ + unsigned int irq = 0; + unsigned int ciu, bit; + + if (of_device_is_compatible(controller, "cavium,octeon-3860-gpio")) + return octeon_irq_gpio_mapping(controller, intspec, intsize); + + ciu = be32_to_cpup(intspec); + bit = be32_to_cpup(intspec + 1); + + if (ciu < 8 && bit < 64) + irq = octeon_irq_ciu_to_irq[ciu][bit]; + + return irq; +} +EXPORT_SYMBOL_GPL(irq_create_of_mapping); + static int octeon_coreid_for_cpu(int cpu) { #ifdef CONFIG_SMP @@ -505,6 +597,72 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) } } +static void octeon_irq_gpio_setup(struct irq_data *data) +{ + union cvmx_gpio_bit_cfgx cfg; + int bit = data->irq - OCTEON_IRQ_GPIO0; + u32 t = irqd_get_trigger_type(data); + + cfg.u64 = 0; + cfg.s.int_en = 1; + cfg.s.int_type = (t & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) != 0; + cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; + + /* 1 uS glitch filter*/ + cfg.s.fil_cnt = 7; + cfg.s.fil_sel = 3; + + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), cfg.u64); +} + +static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable_v2(data); +} + +static void octeon_irq_ciu_enable_gpio(struct irq_data *data) +{ + octeon_irq_gpio_setup(data); + octeon_irq_ciu_enable(data); +} + +static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t) +{ + u32 current_type = irqd_get_trigger_type(data); + + /* If the type has been set, don't change it */ + if (current_type && current_type != t) + return -EINVAL; + + irqd_set_trigger_type(data, t); + return IRQ_SET_MASK_OK; +} + +static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); + + octeon_irq_ciu_disable_all_v2(data); +} + +static void octeon_irq_ciu_disable_gpio(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); + + octeon_irq_ciu_disable_all(data); +} + +static void octeon_irq_ciu_gpio_ack(struct irq_data *data) +{ + int bit = data->irq - OCTEON_IRQ_GPIO0; + u64 mask = 1ull << bit; + + cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); +} + #ifdef CONFIG_SMP static void octeon_irq_cpu_offline_ciu(struct irq_data *data) @@ -717,6 +875,31 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { .flags = IRQCHIP_ONOFFLINE_ENABLED, }; +static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio_v2, + .irq_disable = octeon_irq_ciu_disable_gpio_v2, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, +#endif +}; + +static struct irq_chip octeon_irq_chip_ciu_gpio = { + .name = "CIU-GPIO", + .irq_enable = octeon_irq_ciu_enable_gpio, + .irq_disable = octeon_irq_ciu_disable_gpio, + .irq_mask = octeon_irq_dummy_mask, + .irq_ack = octeon_irq_ciu_gpio_ack, + .irq_set_type = octeon_irq_ciu_gpio_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, +#endif +}; + /* * Watchdog interrupts are special. They are associated with a single * core, so we hardwire the affinity to that core. @@ -890,6 +1073,7 @@ static void __init octeon_irq_init_ciu(void) struct irq_chip *chip_edge; struct irq_chip *chip_mbox; struct irq_chip *chip_wd; + struct irq_chip *chip_gpio; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; @@ -904,6 +1088,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; + chip_gpio = &octeon_irq_chip_ciu_gpio_v2; } else { octeon_irq_ip2 = octeon_irq_ip2_v1; octeon_irq_ip3 = octeon_irq_ip3_v1; @@ -911,6 +1096,7 @@ static void __init octeon_irq_init_ciu(void) chip_edge = &octeon_irq_chip_ciu_edge; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; + chip_gpio = &octeon_irq_chip_ciu_gpio; } octeon_irq_ip4 = octeon_irq_ip4_mask; @@ -921,7 +1107,7 @@ static void __init octeon_irq_init_ciu(void) for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); for (i = 0; i < 16; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
[parent not found: <1320978124-13042-4-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/8] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. [not found] ` <1320978124-13042-4-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-11 16:08 ` Rob Herring [not found] ` <4EBD4868.7040809-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 14+ messages in thread From: Rob Herring @ 2011-11-11 16:08 UTC (permalink / raw) To: ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA, David Daney, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA, ralf-6z/3iImG2C8G8FEW9MqTrA On 11/10/2011 08:21 PM, ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: > From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> > > This is needed for Octeon to use the Device Tree. > > The GPIO interrupts are configured based on Device Tree properties > > Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> > --- > arch/mips/cavium-octeon/octeon-irq.c | 188 +++++++++++++++++++++++++++++++++- > 1 files changed, 187 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c > index ffd4ae6..bb10546 100644 > --- a/arch/mips/cavium-octeon/octeon-irq.c > +++ b/arch/mips/cavium-octeon/octeon-irq.c > @@ -8,11 +8,14 @@ > > #include <linux/interrupt.h> > #include <linux/bitops.h> > +#include <linux/module.h> > #include <linux/percpu.h> > +#include <linux/of_irq.h> > #include <linux/irq.h> > #include <linux/smp.h> > > #include <asm/octeon/octeon.h> > +#include <asm/octeon/cvmx-gpio-defs.h> > > static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); > static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); > @@ -58,6 +61,95 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, > octeon_irq_ciu_to_irq[line][bit] = irq; > } > > +static unsigned int octeon_irq_gpio_mapping(struct device_node *controller, > + const u32 *intspec, > + unsigned int intsize) > +{ > + struct of_irq oirq; > + int i; > + unsigned int irq = 0; > + unsigned int type; > + unsigned int ciu = 0, bit = 0; > + unsigned int pin = be32_to_cpup(intspec); > + unsigned int trigger = be32_to_cpup(intspec + 1); > + bool set_edge_handler = false; > + > + if (pin >= 16) > + goto err; > + i = of_irq_map_one(controller, 0, &oirq); > + if (i) > + goto err; > + if (oirq.size != 2) > + goto err_put; > + > + ciu = oirq.specifier[0]; > + bit = oirq.specifier[1] + pin; > + > + if (ciu >= 8 || bit >= 64) > + goto err_put; > + > + irq = octeon_irq_ciu_to_irq[ciu][bit]; > + if (!irq) > + goto err_put; > + > + switch (trigger & 0xf) { > + case 1: > + type = IRQ_TYPE_EDGE_RISING; > + set_edge_handler = true; > + break; > + case 2: > + type = IRQ_TYPE_EDGE_FALLING; > + set_edge_handler = true; > + break; > + case 4: > + type = IRQ_TYPE_LEVEL_HIGH; > + break; > + case 8: > + type = IRQ_TYPE_LEVEL_LOW; > + break; > + default: > + pr_err("Error: Invalid irq trigger specification: %x\n", > + trigger); > + type = IRQ_TYPE_LEVEL_LOW; > + break; > + } > + > + irq_set_irq_type(irq, type); > + > + if (set_edge_handler) > + __irq_set_handler(irq, handle_edge_irq, 0, NULL); > + > +err_put: > + of_node_put(oirq.controller); > +err: > + return irq; > +} > + > +/* > + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# > + * > + * Octeon irq maps are a pair of indexes. The first selects either > + * ciu0 or ciu1, the second is the bit within the ciu register. > + */ > +unsigned int irq_create_of_mapping(struct device_node *controller, > + const u32 *intspec, unsigned int intsize) > +{ > + unsigned int irq = 0; > + unsigned int ciu, bit; > + > + if (of_device_is_compatible(controller, "cavium,octeon-3860-gpio")) > + return octeon_irq_gpio_mapping(controller, intspec, intsize); > + > + ciu = be32_to_cpup(intspec); > + bit = be32_to_cpup(intspec + 1); > + > + if (ciu < 8 && bit < 64) > + irq = octeon_irq_ciu_to_irq[ciu][bit]; > + > + return irq; > +} > +EXPORT_SYMBOL_GPL(irq_create_of_mapping); Have you looked at irq_domains (kernel/irq/irqdomain.c)? That is what you should be using for your (gpio) interrupt controller and then use the common irq_create_of_mapping. Rob > + > static int octeon_coreid_for_cpu(int cpu) > { > #ifdef CONFIG_SMP > @@ -505,6 +597,72 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) > } > } > > +static void octeon_irq_gpio_setup(struct irq_data *data) > +{ > + union cvmx_gpio_bit_cfgx cfg; > + int bit = data->irq - OCTEON_IRQ_GPIO0; > + u32 t = irqd_get_trigger_type(data); > + > + cfg.u64 = 0; > + cfg.s.int_en = 1; > + cfg.s.int_type = (t & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) != 0; > + cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; > + > + /* 1 uS glitch filter*/ > + cfg.s.fil_cnt = 7; > + cfg.s.fil_sel = 3; > + > + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), cfg.u64); > +} > + > +static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) > +{ > + octeon_irq_gpio_setup(data); > + octeon_irq_ciu_enable_v2(data); > +} > + > +static void octeon_irq_ciu_enable_gpio(struct irq_data *data) > +{ > + octeon_irq_gpio_setup(data); > + octeon_irq_ciu_enable(data); > +} > + > +static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t) > +{ > + u32 current_type = irqd_get_trigger_type(data); > + > + /* If the type has been set, don't change it */ > + if (current_type && current_type != t) > + return -EINVAL; > + > + irqd_set_trigger_type(data, t); > + return IRQ_SET_MASK_OK; > +} > + > +static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) > +{ > + int bit = data->irq - OCTEON_IRQ_GPIO0; > + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); > + > + octeon_irq_ciu_disable_all_v2(data); > +} > + > +static void octeon_irq_ciu_disable_gpio(struct irq_data *data) > +{ > + int bit = data->irq - OCTEON_IRQ_GPIO0; > + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), 0); > + > + octeon_irq_ciu_disable_all(data); > +} > + > +static void octeon_irq_ciu_gpio_ack(struct irq_data *data) > +{ > + int bit = data->irq - OCTEON_IRQ_GPIO0; > + u64 mask = 1ull << bit; > + > + cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); > +} > + > #ifdef CONFIG_SMP > > static void octeon_irq_cpu_offline_ciu(struct irq_data *data) > @@ -717,6 +875,31 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { > .flags = IRQCHIP_ONOFFLINE_ENABLED, > }; > > +static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { > + .name = "CIU-GPIO", > + .irq_enable = octeon_irq_ciu_enable_gpio_v2, > + .irq_disable = octeon_irq_ciu_disable_gpio_v2, > + .irq_ack = octeon_irq_ciu_gpio_ack, > + .irq_mask = octeon_irq_ciu_disable_local_v2, > + .irq_unmask = octeon_irq_ciu_enable_v2, > + .irq_set_type = octeon_irq_ciu_gpio_set_type, > +#ifdef CONFIG_SMP > + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, > +#endif > +}; > + > +static struct irq_chip octeon_irq_chip_ciu_gpio = { > + .name = "CIU-GPIO", > + .irq_enable = octeon_irq_ciu_enable_gpio, > + .irq_disable = octeon_irq_ciu_disable_gpio, > + .irq_mask = octeon_irq_dummy_mask, > + .irq_ack = octeon_irq_ciu_gpio_ack, > + .irq_set_type = octeon_irq_ciu_gpio_set_type, > +#ifdef CONFIG_SMP > + .irq_set_affinity = octeon_irq_ciu_set_affinity, > +#endif > +}; > + > /* > * Watchdog interrupts are special. They are associated with a single > * core, so we hardwire the affinity to that core. > @@ -890,6 +1073,7 @@ static void __init octeon_irq_init_ciu(void) > struct irq_chip *chip_edge; > struct irq_chip *chip_mbox; > struct irq_chip *chip_wd; > + struct irq_chip *chip_gpio; > > octeon_irq_init_ciu_percpu(); > octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; > @@ -904,6 +1088,7 @@ static void __init octeon_irq_init_ciu(void) > chip_edge = &octeon_irq_chip_ciu_edge_v2; > chip_mbox = &octeon_irq_chip_ciu_mbox_v2; > chip_wd = &octeon_irq_chip_ciu_wd_v2; > + chip_gpio = &octeon_irq_chip_ciu_gpio_v2; > } else { > octeon_irq_ip2 = octeon_irq_ip2_v1; > octeon_irq_ip3 = octeon_irq_ip3_v1; > @@ -911,6 +1096,7 @@ static void __init octeon_irq_init_ciu(void) > chip_edge = &octeon_irq_chip_ciu_edge; > chip_mbox = &octeon_irq_chip_ciu_mbox; > chip_wd = &octeon_irq_chip_ciu_wd; > + chip_gpio = &octeon_irq_chip_ciu_gpio; > } > octeon_irq_ip4 = octeon_irq_ip4_mask; > > @@ -921,7 +1107,7 @@ static void __init octeon_irq_init_ciu(void) > for (i = 0; i < 16; i++) > octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); > for (i = 0; i < 16; i++) > - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); > + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip_gpio, handle_level_irq); > > octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); > octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <4EBD4868.7040809-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/8] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. [not found] ` <4EBD4868.7040809-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-11 19:49 ` David Daney [not found] ` <4EBD7C5D.7080606-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 14+ messages in thread From: David Daney @ 2011-11-11 19:49 UTC (permalink / raw) To: Rob Herring, Thomas Gleixner Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA, David Daney, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA, ralf-6z/3iImG2C8G8FEW9MqTrA On 11/11/2011 08:08 AM, Rob Herring wrote: > On 11/10/2011 08:21 PM, ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: >> From: David Daney<david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >> >> This is needed for Octeon to use the Device Tree. >> >> The GPIO interrupts are configured based on Device Tree properties >> >> Signed-off-by: David Daney<david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >> --- >> arch/mips/cavium-octeon/octeon-irq.c | 188 +++++++++++++++++++++++++++++++++- >> 1 files changed, 187 insertions(+), 1 deletions(-) >> >> diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c >> index ffd4ae6..bb10546 100644 >> --- a/arch/mips/cavium-octeon/octeon-irq.c >> +++ b/arch/mips/cavium-octeon/octeon-irq.c >> @@ -8,11 +8,14 @@ >> >> #include<linux/interrupt.h> >> #include<linux/bitops.h> >> +#include<linux/module.h> >> #include<linux/percpu.h> >> +#include<linux/of_irq.h> >> #include<linux/irq.h> >> #include<linux/smp.h> >> >> #include<asm/octeon/octeon.h> >> +#include<asm/octeon/cvmx-gpio-defs.h> >> >> static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); >> static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); >> @@ -58,6 +61,95 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, >> octeon_irq_ciu_to_irq[line][bit] = irq; >> } >> >> +static unsigned int octeon_irq_gpio_mapping(struct device_node *controller, >> + const u32 *intspec, >> + unsigned int intsize) >> +{ >> + struct of_irq oirq; >> + int i; >> + unsigned int irq = 0; >> + unsigned int type; >> + unsigned int ciu = 0, bit = 0; >> + unsigned int pin = be32_to_cpup(intspec); >> + unsigned int trigger = be32_to_cpup(intspec + 1); >> + bool set_edge_handler = false; >> + >> + if (pin>= 16) >> + goto err; >> + i = of_irq_map_one(controller, 0,&oirq); >> + if (i) >> + goto err; >> + if (oirq.size != 2) >> + goto err_put; >> + >> + ciu = oirq.specifier[0]; >> + bit = oirq.specifier[1] + pin; >> + >> + if (ciu>= 8 || bit>= 64) >> + goto err_put; >> + >> + irq = octeon_irq_ciu_to_irq[ciu][bit]; >> + if (!irq) >> + goto err_put; >> + >> + switch (trigger& 0xf) { >> + case 1: >> + type = IRQ_TYPE_EDGE_RISING; >> + set_edge_handler = true; >> + break; >> + case 2: >> + type = IRQ_TYPE_EDGE_FALLING; >> + set_edge_handler = true; >> + break; >> + case 4: >> + type = IRQ_TYPE_LEVEL_HIGH; >> + break; >> + case 8: >> + type = IRQ_TYPE_LEVEL_LOW; >> + break; >> + default: >> + pr_err("Error: Invalid irq trigger specification: %x\n", >> + trigger); >> + type = IRQ_TYPE_LEVEL_LOW; >> + break; >> + } >> + >> + irq_set_irq_type(irq, type); >> + >> + if (set_edge_handler) >> + __irq_set_handler(irq, handle_edge_irq, 0, NULL); >> + >> +err_put: >> + of_node_put(oirq.controller); >> +err: >> + return irq; >> +} >> + >> +/* >> + * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# >> + * >> + * Octeon irq maps are a pair of indexes. The first selects either >> + * ciu0 or ciu1, the second is the bit within the ciu register. >> + */ >> +unsigned int irq_create_of_mapping(struct device_node *controller, >> + const u32 *intspec, unsigned int intsize) >> +{ >> + unsigned int irq = 0; >> + unsigned int ciu, bit; >> + >> + if (of_device_is_compatible(controller, "cavium,octeon-3860-gpio")) >> + return octeon_irq_gpio_mapping(controller, intspec, intsize); >> + >> + ciu = be32_to_cpup(intspec); >> + bit = be32_to_cpup(intspec + 1); >> + >> + if (ciu< 8&& bit< 64) >> + irq = octeon_irq_ciu_to_irq[ciu][bit]; >> + >> + return irq; >> +} >> +EXPORT_SYMBOL_GPL(irq_create_of_mapping); > > Have you looked at irq_domains (kernel/irq/irqdomain.c)? That is what > you should be using for your (gpio) interrupt controller and then use > the common irq_create_of_mapping. > Unfortunatly, although a good idea, kernel/irq/irqdomain.c makes a bunch of assumptions that don't hold for Octeon. We may be able to improve it so that it flexible enough to suit us. Here are the problems I see: 1) It is assumed that there is some sort of linear correspondence between 'hwirq' and 'irq', and that the range of valid values is contiguous. 2) It is assumed that the concepts of nr_irq, irq_base and hwirq_base have easy to determin values and you can do iteration over their ranges by adding indexes to the bases. I think we can fix this by adding iteration helper functions to struct irq_domain. If these are present, we would just ignore the irq_base, nr_irq and hwirq_base elements of the structure. irq_domain_for_each_hwirq() and irq_domain_for_each_irq() would be modified to use the iteration helper functions. David Daney ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <4EBD7C5D.7080606-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/8] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. [not found] ` <4EBD7C5D.7080606-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-11 20:41 ` Rob Herring [not found] ` <4EBD8867.30205-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 14+ messages in thread From: Rob Herring @ 2011-11-11 20:41 UTC (permalink / raw) To: David Daney Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA, David Daney, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA, ralf-6z/3iImG2C8G8FEW9MqTrA, Thomas Gleixner David, On 11/11/2011 01:49 PM, David Daney wrote: > On 11/11/2011 08:08 AM, Rob Herring wrote: >> On 11/10/2011 08:21 PM, ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: >>> From: David Daney<david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >>> >>> This is needed for Octeon to use the Device Tree. >>> >>> The GPIO interrupts are configured based on Device Tree properties >>> >>> Signed-off-by: David Daney<david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >>> --- >>> arch/mips/cavium-octeon/octeon-irq.c | 188 >>> +++++++++++++++++++++++++++++++++- >>> 1 files changed, 187 insertions(+), 1 deletions(-) >>> >>> diff --git a/arch/mips/cavium-octeon/octeon-irq.c >>> b/arch/mips/cavium-octeon/octeon-irq.c >>> index ffd4ae6..bb10546 100644 >>> --- a/arch/mips/cavium-octeon/octeon-irq.c >>> +++ b/arch/mips/cavium-octeon/octeon-irq.c >>> @@ -8,11 +8,14 @@ >>> >>> #include<linux/interrupt.h> >>> #include<linux/bitops.h> >>> +#include<linux/module.h> >>> #include<linux/percpu.h> >>> +#include<linux/of_irq.h> >>> #include<linux/irq.h> >>> #include<linux/smp.h> >>> >>> #include<asm/octeon/octeon.h> >>> +#include<asm/octeon/cvmx-gpio-defs.h> >>> >>> static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); >>> static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); >>> @@ -58,6 +61,95 @@ static void __init octeon_irq_set_ciu_mapping(int >>> irq, int line, int bit, >>> octeon_irq_ciu_to_irq[line][bit] = irq; >>> } >>> >>> +static unsigned int octeon_irq_gpio_mapping(struct device_node >>> *controller, >>> + const u32 *intspec, >>> + unsigned int intsize) >>> +{ >>> + struct of_irq oirq; >>> + int i; >>> + unsigned int irq = 0; >>> + unsigned int type; >>> + unsigned int ciu = 0, bit = 0; >>> + unsigned int pin = be32_to_cpup(intspec); >>> + unsigned int trigger = be32_to_cpup(intspec + 1); >>> + bool set_edge_handler = false; >>> + >>> + if (pin>= 16) >>> + goto err; >>> + i = of_irq_map_one(controller, 0,&oirq); >>> + if (i) >>> + goto err; >>> + if (oirq.size != 2) >>> + goto err_put; >>> + >>> + ciu = oirq.specifier[0]; >>> + bit = oirq.specifier[1] + pin; >>> + >>> + if (ciu>= 8 || bit>= 64) >>> + goto err_put; >>> + >>> + irq = octeon_irq_ciu_to_irq[ciu][bit]; >>> + if (!irq) >>> + goto err_put; >>> + >>> + switch (trigger& 0xf) { >>> + case 1: >>> + type = IRQ_TYPE_EDGE_RISING; >>> + set_edge_handler = true; >>> + break; >>> + case 2: >>> + type = IRQ_TYPE_EDGE_FALLING; >>> + set_edge_handler = true; >>> + break; >>> + case 4: >>> + type = IRQ_TYPE_LEVEL_HIGH; >>> + break; >>> + case 8: >>> + type = IRQ_TYPE_LEVEL_LOW; >>> + break; >>> + default: >>> + pr_err("Error: Invalid irq trigger specification: %x\n", >>> + trigger); >>> + type = IRQ_TYPE_LEVEL_LOW; >>> + break; >>> + } >>> + >>> + irq_set_irq_type(irq, type); >>> + >>> + if (set_edge_handler) >>> + __irq_set_handler(irq, handle_edge_irq, 0, NULL); >>> + >>> +err_put: >>> + of_node_put(oirq.controller); >>> +err: >>> + return irq; >>> +} >>> + >>> +/* >>> + * irq_create_of_mapping - Hook to resolve OF irq specifier into a >>> Linux irq# >>> + * >>> + * Octeon irq maps are a pair of indexes. The first selects either >>> + * ciu0 or ciu1, the second is the bit within the ciu register. >>> + */ >>> +unsigned int irq_create_of_mapping(struct device_node *controller, >>> + const u32 *intspec, unsigned int intsize) >>> +{ >>> + unsigned int irq = 0; >>> + unsigned int ciu, bit; >>> + >>> + if (of_device_is_compatible(controller, "cavium,octeon-3860-gpio")) >>> + return octeon_irq_gpio_mapping(controller, intspec, intsize); >>> + >>> + ciu = be32_to_cpup(intspec); >>> + bit = be32_to_cpup(intspec + 1); >>> + >>> + if (ciu< 8&& bit< 64) >>> + irq = octeon_irq_ciu_to_irq[ciu][bit]; >>> + >>> + return irq; >>> +} >>> +EXPORT_SYMBOL_GPL(irq_create_of_mapping); >> >> Have you looked at irq_domains (kernel/irq/irqdomain.c)? That is what >> you should be using for your (gpio) interrupt controller and then use >> the common irq_create_of_mapping. >> > > Unfortunatly, although a good idea, kernel/irq/irqdomain.c makes a bunch > of assumptions that don't hold for Octeon. We may be able to improve it > so that it flexible enough to suit us. > > > Here are the problems I see: > > 1) It is assumed that there is some sort of linear correspondence > between 'hwirq' and 'irq', and that the range of valid values is > contiguous. That's not true if you implement .to_irq for your domain. > 2) It is assumed that the concepts of nr_irq, irq_base and hwirq_base > have easy to determin values and you can do iteration over their ranges > by adding indexes to the bases. That's true for hwirq numbering, but not for Linux irq numbering. irq_base is only used if you don't provide .to_irq. hwirq_base is just to allow a linear range that doesn't start with 0. > I think we can fix this by adding iteration helper functions to struct > irq_domain. If these are present, we would just ignore the irq_base, > nr_irq and hwirq_base elements of the structure. > irq_domain_for_each_hwirq() and irq_domain_for_each_irq() would be > modified to use the iteration helper functions. Expanding irqdomain is certainly the intention and right direction. It seems to me you just need something different than an irq. controller with a linear range of irq lines. Perhaps sparsely allocated hwirq's? Can you describe the h/w? Also, you could have a different domain per irqdesc if you really needed to. Rob ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <4EBD8867.30205-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/8] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts. [not found] ` <4EBD8867.30205-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-11 20:45 ` David Daney 0 siblings, 0 replies; 14+ messages in thread From: David Daney @ 2011-11-11 20:45 UTC (permalink / raw) To: Rob Herring Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, David Daney, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, Thomas Gleixner On 11/11/2011 12:41 PM, Rob Herring wrote: > David, > > On 11/11/2011 01:49 PM, David Daney wrote: >> On 11/11/2011 08:08 AM, Rob Herring wrote: >>> On 11/10/2011 08:21 PM, ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: >>>> From: David Daney<david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >>>> >>>> This is needed for Octeon to use the Device Tree. >>>> >>>> The GPIO interrupts are configured based on Device Tree properties >>>> >>>> Signed-off-by: David Daney<david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> >>>> --- >>>> arch/mips/cavium-octeon/octeon-irq.c | 188 >>>> +++++++++++++++++++++++++++++++++- >>>> 1 files changed, 187 insertions(+), 1 deletions(-) >>>> >>>> diff --git a/arch/mips/cavium-octeon/octeon-irq.c >>>> b/arch/mips/cavium-octeon/octeon-irq.c >>>> index ffd4ae6..bb10546 100644 >>>> --- a/arch/mips/cavium-octeon/octeon-irq.c >>>> +++ b/arch/mips/cavium-octeon/octeon-irq.c >>>> @@ -8,11 +8,14 @@ >>>> >>>> #include<linux/interrupt.h> >>>> #include<linux/bitops.h> >>>> +#include<linux/module.h> >>>> #include<linux/percpu.h> >>>> +#include<linux/of_irq.h> >>>> #include<linux/irq.h> >>>> #include<linux/smp.h> >>>> >>>> #include<asm/octeon/octeon.h> >>>> +#include<asm/octeon/cvmx-gpio-defs.h> >>>> >>>> static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); >>>> static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); >>>> @@ -58,6 +61,95 @@ static void __init octeon_irq_set_ciu_mapping(int >>>> irq, int line, int bit, >>>> octeon_irq_ciu_to_irq[line][bit] = irq; >>>> } >>>> >>>> +static unsigned int octeon_irq_gpio_mapping(struct device_node >>>> *controller, >>>> + const u32 *intspec, >>>> + unsigned int intsize) >>>> +{ >>>> + struct of_irq oirq; >>>> + int i; >>>> + unsigned int irq = 0; >>>> + unsigned int type; >>>> + unsigned int ciu = 0, bit = 0; >>>> + unsigned int pin = be32_to_cpup(intspec); >>>> + unsigned int trigger = be32_to_cpup(intspec + 1); >>>> + bool set_edge_handler = false; >>>> + >>>> + if (pin>= 16) >>>> + goto err; >>>> + i = of_irq_map_one(controller, 0,&oirq); >>>> + if (i) >>>> + goto err; >>>> + if (oirq.size != 2) >>>> + goto err_put; >>>> + >>>> + ciu = oirq.specifier[0]; >>>> + bit = oirq.specifier[1] + pin; >>>> + >>>> + if (ciu>= 8 || bit>= 64) >>>> + goto err_put; >>>> + >>>> + irq = octeon_irq_ciu_to_irq[ciu][bit]; >>>> + if (!irq) >>>> + goto err_put; >>>> + >>>> + switch (trigger& 0xf) { >>>> + case 1: >>>> + type = IRQ_TYPE_EDGE_RISING; >>>> + set_edge_handler = true; >>>> + break; >>>> + case 2: >>>> + type = IRQ_TYPE_EDGE_FALLING; >>>> + set_edge_handler = true; >>>> + break; >>>> + case 4: >>>> + type = IRQ_TYPE_LEVEL_HIGH; >>>> + break; >>>> + case 8: >>>> + type = IRQ_TYPE_LEVEL_LOW; >>>> + break; >>>> + default: >>>> + pr_err("Error: Invalid irq trigger specification: %x\n", >>>> + trigger); >>>> + type = IRQ_TYPE_LEVEL_LOW; >>>> + break; >>>> + } >>>> + >>>> + irq_set_irq_type(irq, type); >>>> + >>>> + if (set_edge_handler) >>>> + __irq_set_handler(irq, handle_edge_irq, 0, NULL); >>>> + >>>> +err_put: >>>> + of_node_put(oirq.controller); >>>> +err: >>>> + return irq; >>>> +} >>>> + >>>> +/* >>>> + * irq_create_of_mapping - Hook to resolve OF irq specifier into a >>>> Linux irq# >>>> + * >>>> + * Octeon irq maps are a pair of indexes. The first selects either >>>> + * ciu0 or ciu1, the second is the bit within the ciu register. >>>> + */ >>>> +unsigned int irq_create_of_mapping(struct device_node *controller, >>>> + const u32 *intspec, unsigned int intsize) >>>> +{ >>>> + unsigned int irq = 0; >>>> + unsigned int ciu, bit; >>>> + >>>> + if (of_device_is_compatible(controller, "cavium,octeon-3860-gpio")) >>>> + return octeon_irq_gpio_mapping(controller, intspec, intsize); >>>> + >>>> + ciu = be32_to_cpup(intspec); >>>> + bit = be32_to_cpup(intspec + 1); >>>> + >>>> + if (ciu< 8&& bit< 64) >>>> + irq = octeon_irq_ciu_to_irq[ciu][bit]; >>>> + >>>> + return irq; >>>> +} >>>> +EXPORT_SYMBOL_GPL(irq_create_of_mapping); >>> >>> Have you looked at irq_domains (kernel/irq/irqdomain.c)? That is what >>> you should be using for your (gpio) interrupt controller and then use >>> the common irq_create_of_mapping. >>> >> >> Unfortunatly, although a good idea, kernel/irq/irqdomain.c makes a bunch >> of assumptions that don't hold for Octeon. We may be able to improve it >> so that it flexible enough to suit us. >> >> >> Here are the problems I see: >> >> 1) It is assumed that there is some sort of linear correspondence >> between 'hwirq' and 'irq', and that the range of valid values is >> contiguous. > > That's not true if you implement .to_irq for your domain. It is true. irq_domain_add() iterates. > >> 2) It is assumed that the concepts of nr_irq, irq_base and hwirq_base >> have easy to determin values and you can do iteration over their ranges >> by adding indexes to the bases. > > That's true for hwirq numbering, but not for Linux irq numbering. > irq_base is only used if you don't provide .to_irq. hwirq_base is just > to allow a linear range that doesn't start with 0. > >> I think we can fix this by adding iteration helper functions to struct >> irq_domain. If these are present, we would just ignore the irq_base, >> nr_irq and hwirq_base elements of the structure. >> irq_domain_for_each_hwirq() and irq_domain_for_each_irq() would be >> modified to use the iteration helper functions. > > Expanding irqdomain is certainly the intention and right direction. I have a patch. It should be ready in a couple of hours. > > It seems to me you just need something different than an irq. controller > with a linear range of irq lines. Perhaps sparsely allocated hwirq's? > Can you describe the h/w? > > Also, you could have a different domain per irqdesc if you really needed to. > Too ugly. David Daney ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH 2/8] MIPS: Prune some target specific code out of prom.c [not found] ` <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-11 2:21 ` ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 2011-11-11 2:22 ` [PATCH 4/8] MIPS: Octeon: Initialize and fixup device tree ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w ` (2 subsequent siblings) 3 siblings, 0 replies; 14+ messages in thread From: ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w @ 2011-11-11 2:21 UTC (permalink / raw) To: linux-mips-6z/3iImG2C8G8FEW9MqTrA, ralf-6z/3iImG2C8G8FEW9MqTrA, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, grant.likely-s3s/WqlpOiPyB63q8FvJNQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: David Daney From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> This code is not common enough to be in a shared file. It is also not used by any existing boards, so just remove it. Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> --- arch/mips/kernel/prom.c | 50 ----------------------------------------------- 1 files changed, 0 insertions(+), 50 deletions(-) diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c index 6b8b420..04bf462 100644 --- a/arch/mips/kernel/prom.c +++ b/arch/mips/kernel/prom.c @@ -59,53 +59,3 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start, initrd_below_start_ok = 1; } #endif - -/* - * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq# - * - * Currently the mapping mechanism is trivial; simple flat hwirq numbers are - * mapped 1:1 onto Linux irq numbers. Cascaded irq controllers are not - * supported. - */ -unsigned int irq_create_of_mapping(struct device_node *controller, - const u32 *intspec, unsigned int intsize) -{ - return intspec[0]; -} -EXPORT_SYMBOL_GPL(irq_create_of_mapping); - -void __init early_init_devtree(void *params) -{ - /* Setup flat device-tree pointer */ - initial_boot_params = params; - - /* Retrieve various informations from the /chosen node of the - * device-tree, including the platform type, initrd location and - * size, and more ... - */ - of_scan_flat_dt(early_init_dt_scan_chosen, arcs_cmdline); - - - /* Scan memory nodes */ - of_scan_flat_dt(early_init_dt_scan_root, NULL); - of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); -} - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_mem_mach(base, size); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_mem_mach(base, size); -} -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/8] MIPS: Octeon: Initialize and fixup device tree. [not found] ` <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2011-11-11 2:21 ` [PATCH 2/8] MIPS: Prune some target specific code out of prom.c ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w @ 2011-11-11 2:22 ` ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 2011-11-11 2:22 ` [PATCH 5/8] i2c: Convert i2c-octeon.c to use " ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 2011-11-11 2:22 ` [PATCH 6/8] netdev: mdio-octeon.c: Convert " ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 3 siblings, 0 replies; 14+ messages in thread From: ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w @ 2011-11-11 2:22 UTC (permalink / raw) To: linux-mips-6z/3iImG2C8G8FEW9MqTrA, ralf-6z/3iImG2C8G8FEW9MqTrA, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, grant.likely-s3s/WqlpOiPyB63q8FvJNQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: David Daney From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> --- arch/mips/Kconfig | 1 + arch/mips/cavium-octeon/Makefile | 3 + arch/mips/cavium-octeon/octeon-platform.c | 523 ++++++++++++++++++++++++++++- arch/mips/cavium-octeon/setup.c | 45 +++ 4 files changed, 571 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d46f1da..7b6b7ba 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1404,6 +1404,7 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES + select LIBFDT help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 5e25dce..17e3710 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -9,6 +9,9 @@ # Copyright (C) 2005-2009 Cavium Networks # +CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt +CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt + obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index cd61d72..2754bc2 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2010 Cavium Networks + * Copyright (C) 2004-2011 Cavium Networks * Copyright (C) 2008 Wind River Systems */ @@ -13,10 +13,16 @@ #include <linux/usb.h> #include <linux/dma-mapping.h> #include <linux/module.h> +#include <linux/slab.h> #include <linux/platform_device.h> +#include <linux/of_platform.h> +#include <linux/of_fdt.h> +#include <linux/libfdt.h> #include <asm/octeon/octeon.h> #include <asm/octeon/cvmx-rnm-defs.h> +#include <asm/octeon/cvmx-helper.h> +#include <asm/octeon/cvmx-helper-board.h> static struct octeon_cf_data octeon_cf_data; @@ -440,6 +446,521 @@ device_initcall(octeon_ohci_device_init); #endif /* CONFIG_USB */ +static struct of_device_id __initdata octeon_ids[] = { + { .compatible = "simple-bus", }, + { .compatible = "cavium,octeon-6335-uctl", }, + { .compatible = "cavium,octeon-3860-bootbus", }, + { .compatible = "cavium,mdio-mux", }, + { .compatible = "gpio-leds", }, + {}, +}; + +static bool __init octeon_has_88e1145(void) +{ + return !OCTEON_IS_MODEL(OCTEON_CN52XX) && + !OCTEON_IS_MODEL(OCTEON_CN6XXX) && + !OCTEON_IS_MODEL(OCTEON_CN56XX); +} + +static void __init octeon_fdt_set_phy(int eth, int phy_addr) +{ + const __be32 *phy_handle; + const __be32 *alt_phy_handle; + const __be32 *reg; + u32 phandle; + int phy; + int alt_phy; + const char *p; + int current_len; + char new_name[20]; + + phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); + if (!phy_handle) + return; + + phandle = be32_to_cpup(phy_handle); + phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); + + alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); + if (alt_phy_handle) { + u32 alt_phandle = be32_to_cpup(alt_phy_handle); + alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); + } else { + alt_phy = -1; + } + + if (phy_addr < 0 || phy < 0) { + /* Delete the PHY things */ + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + /* This one may fail */ + fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); + if (phy >= 0) + fdt_nop_node(initial_boot_params, phy); + if (alt_phy >= 0) + fdt_nop_node(initial_boot_params, alt_phy); + return; + } + + if (phy_addr >= 256 && alt_phy > 0) { + const struct fdt_property *phy_prop; + struct fdt_property *alt_prop; + u32 phy_handle_name; + + /* Use the alt phy node instead.*/ + phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); + phy_handle_name = phy_prop->nameoff; + fdt_nop_node(initial_boot_params, phy); + fdt_nop_property(initial_boot_params, eth, "phy-handle"); + alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); + alt_prop->nameoff = phy_handle_name; + phy = alt_phy; + } + + phy_addr &= 0xff; + + if (octeon_has_88e1145()) { + fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); + memset(new_name, 0, sizeof(new_name)); + strcpy(new_name, "marvell,88e1145"); + p = fdt_getprop(initial_boot_params, phy, "compatible", + ¤t_len); + if (p && current_len >= strlen(new_name)) + fdt_setprop_inplace(initial_boot_params, phy, + "compatible", new_name, current_len); + } + + reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); + if (phy_addr == be32_to_cpup(reg)) + return; + + fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); + + snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); + + p = fdt_get_name(initial_boot_params, phy, ¤t_len); + if (p && current_len == strlen(new_name)) + fdt_set_name(initial_boot_params, phy, new_name); + else + pr_err("Error: could not rename ethernet phy: <%s>", p); +} + +static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) +{ + u8 new_mac[6]; + u64 mac = *pmac; + int r; + + new_mac[0] = (mac >> 40) & 0xff; + new_mac[1] = (mac >> 32) & 0xff; + new_mac[2] = (mac >> 24) & 0xff; + new_mac[3] = (mac >> 16) & 0xff; + new_mac[4] = (mac >> 8) & 0xff; + new_mac[5] = mac & 0xff; + + r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", + new_mac, sizeof(new_mac)); + + if (r) { + pr_err("Setting \"local-mac-address\" failed %d", r); + return; + } + *pmac = mac + 1; +} + +static void __init octeon_fdt_rm_ethernet(int node) +{ + const __be32 *phy_handle; + + phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); + if (phy_handle) { + u32 ph = be32_to_cpup(phy_handle); + int p = fdt_node_offset_by_phandle(initial_boot_params, ph); + if (p >= 0) + fdt_nop_node(initial_boot_params, p); + } + fdt_nop_node(initial_boot_params, node); +} + +static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac) +{ + char name_buffer[20]; + int eth; + int phy_addr; + int ipd_port; + + snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); + eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); + if (eth < 0) + return; + if (p > max) { + pr_debug("Deleting port %x:%x\n", i, p); + octeon_fdt_rm_ethernet(eth); + return; + } + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + ipd_port = (0x100 * i) + (0x10 * p) + 0x800; + else + ipd_port = 16 * i + p; + + phy_addr = cvmx_helper_board_get_mii_address(ipd_port); + octeon_fdt_set_phy(eth, phy_addr); + octeon_fdt_set_mac_addr(eth, pmac); +} + +static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) +{ + char name_buffer[20]; + int iface; + int p; + int count; + + count = cvmx_helper_interface_enumerate(idx); + + snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); + iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); + if (iface < 0) + return; + + for (p = 0; p < 16; p++) + octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); +} + +int __init octeon_prune_device_tree(void) +{ + int i, max_port, uart_mask; + const char *pip_path; + const char *alias_prop; + char name_buffer[20]; + int aliases; + u64 mac_addr_base; + + if (fdt_check_header(initial_boot_params)) + panic("Corrupt Device Tree."); + + aliases = fdt_path_offset(initial_boot_params, "/aliases"); + if (aliases < 0) { + pr_err("Error: No /aliases node in device tree."); + return -EINVAL; + } + + + mac_addr_base = + ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | + ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | + ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | + ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | + ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | + (octeon_bootinfo->mac_addr_base[5] & 0xffull); + + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) + max_port = 2; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) + max_port = 1; + else + max_port = 0; + + if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) + max_port = 0; + + for (i = 0; i < 2; i++) { + int mgmt; + snprintf(name_buffer, sizeof(name_buffer), + "mix%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + if (alias_prop) { + mgmt = fdt_path_offset(initial_boot_params, alias_prop); + if (mgmt < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting mix%d\n", i); + octeon_fdt_rm_ethernet(mgmt); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } else { + int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); + octeon_fdt_set_phy(mgmt, phy_addr); + octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); + } + } + } + + pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); + if (pip_path) { + int pip = fdt_path_offset(initial_boot_params, pip_path); + if (pip >= 0) + for (i = 0; i <= 4; i++) + octeon_fdt_pip_iface(pip, i, &mac_addr_base); + } + + /* I2C */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN68XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "twsi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting twsi%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + } + + /* SMI/MDIO */ + if (OCTEON_IS_MODEL(OCTEON_CN68XX)) + max_port = 4; + else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || + OCTEON_IS_MODEL(OCTEON_CN63XX) || + OCTEON_IS_MODEL(OCTEON_CN56XX)) + max_port = 2; + else + max_port = 1; + + for (i = 0; i < 2; i++) { + int i2c; + snprintf(name_buffer, sizeof(name_buffer), + "smi%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + i2c = fdt_path_offset(initial_boot_params, alias_prop); + if (i2c < 0) + continue; + if (i >= max_port) { + pr_debug("Deleting smi%d\n", i); + fdt_nop_node(initial_boot_params, i2c); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + } + + /* Serial */ + uart_mask = 3; + + /* Right now CN52XX is the only chip with a third uart */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) + uart_mask |= 4; /* uart2 */ + + for (i = 0; i < 3; i++) { + int uart; + snprintf(name_buffer, sizeof(name_buffer), + "uart%d", i); + alias_prop = fdt_getprop(initial_boot_params, aliases, + name_buffer, NULL); + + if (alias_prop) { + uart = fdt_path_offset(initial_boot_params, alias_prop); + if (uart_mask & (1 << i)) + continue; + pr_debug("Deleting uart%d\n", i); + fdt_nop_node(initial_boot_params, uart); + fdt_nop_property(initial_boot_params, aliases, + name_buffer); + } + } + + /* Compact Flash */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "cf0", NULL); + if (alias_prop) { + union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; + unsigned long base_ptr, region_base, region_size; + unsigned long region1_base = 0; + unsigned long region1_size = 0; + int cs, bootbus; + bool is_16bit = false; + bool is_true_ide = false; + __be32 new_reg[6]; + __be32 *ranges; + int len; + + int cf = fdt_path_offset(initial_boot_params, alias_prop); + base_ptr = 0; + if (octeon_bootinfo->major_version == 1 + && octeon_bootinfo->minor_version >= 1) { + if (octeon_bootinfo->compact_flash_common_base_addr) + base_ptr = octeon_bootinfo->compact_flash_common_base_addr; + } else { + base_ptr = 0x1d000800; + } + + if (!base_ptr) + goto no_cf; + + /* Find CS0 region. */ + for (cs = 0; cs < 8; cs++) { + mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (mio_boot_reg_cfg.s.en && base_ptr >= region_base + && base_ptr < region_base + region_size) { + is_16bit = mio_boot_reg_cfg.s.width; + break; + } + } + if (cs >= 7) { + /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ + goto no_cf; + } + + if (!(base_ptr & 0xfffful)) { + /* + * Boot loader signals availability of DMA (true_ide + * mode) by setting low order bits of base_ptr to + * zero. + */ + + /* Asume that CS1 immediately follows. */ + mio_boot_reg_cfg.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); + region1_base = mio_boot_reg_cfg.s.base << 16; + region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (!mio_boot_reg_cfg.s.en) + goto no_cf; + is_true_ide = true; + + } else { + fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); + fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); + if (!is_16bit) { + __be32 width = cpu_to_be32(8); + fdt_setprop_inplace(initial_boot_params, cf, + "cavium,bus-width", &width, sizeof(width)); + } + } + new_reg[0] = cpu_to_be32(cs); + new_reg[1] = cpu_to_be32(0); + new_reg[2] = cpu_to_be32(0x10000); + new_reg[3] = cpu_to_be32(cs + 1); + new_reg[4] = cpu_to_be32(0); + new_reg[5] = cpu_to_be32(0x10000); + fdt_setprop_inplace(initial_boot_params, cf, + "reg", new_reg, sizeof(new_reg)); + + bootbus = fdt_parent_offset(initial_boot_params, cf); + if (bootbus < 0) + goto no_cf; + ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); + if (!ranges || len < (5 * 8 * sizeof(__be32))) + goto no_cf; + + ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region_size); + if (is_true_ide) { + cs++; + ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); + } + goto end_cf; +no_cf: + fdt_nop_node(initial_boot_params, cf); + +end_cf: + ; + } + + /* 8 char LED */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "led0", NULL); + if (alias_prop) { + union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; + unsigned long base_ptr, region_base, region_size; + int cs, bootbus; + __be32 new_reg[6]; + __be32 *ranges; + int len; + int led = fdt_path_offset(initial_boot_params, alias_prop); + + base_ptr = octeon_bootinfo->led_display_base_addr; + if (base_ptr == 0) + goto no_led; + /* Find CS0 region. */ + for (cs = 0; cs < 8; cs++) { + mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (mio_boot_reg_cfg.s.en && base_ptr >= region_base + && base_ptr < region_base + region_size) + break; + } + + if (cs > 7) + goto no_led; + + new_reg[0] = cpu_to_be32(cs); + new_reg[1] = cpu_to_be32(0x20); + new_reg[2] = cpu_to_be32(0x20); + new_reg[3] = cpu_to_be32(cs); + new_reg[4] = cpu_to_be32(0); + new_reg[5] = cpu_to_be32(0x20); + fdt_setprop_inplace(initial_boot_params, led, + "reg", new_reg, sizeof(new_reg)); + + bootbus = fdt_parent_offset(initial_boot_params, led); + if (bootbus < 0) + goto no_led; + ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); + if (!ranges || len < (5 * 8 * sizeof(__be32))) + goto no_led; + + ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); + ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); + ranges[(cs * 5) + 4] = cpu_to_be32(region_size); + goto end_led; + +no_led: + fdt_nop_node(initial_boot_params, led); +end_led: + ; + } + + /* OHCI/UHCI USB */ + alias_prop = fdt_getprop(initial_boot_params, aliases, + "uctl", NULL); + if (alias_prop) { + int uctl = fdt_path_offset(initial_boot_params, alias_prop); + + if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || + octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { + pr_debug("Deleting uctl\n"); + fdt_nop_node(initial_boot_params, uctl); + fdt_nop_property(initial_boot_params, aliases, "uctl"); + } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || + octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { + /* Missing "refclk-type" defaults to crystal. */ + fdt_nop_property(initial_boot_params, uctl, "refclk-type"); + } + } + + return 0; +} + +static int __init octeon_publish_devices(void) +{ + return of_platform_bus_probe(NULL, octeon_ids, NULL); +} +device_initcall(octeon_publish_devices); + MODULE_AUTHOR("David Daney <ddaney-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>"); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 36221b3..d9f20c4 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -20,6 +20,8 @@ #include <linux/platform_device.h> #include <linux/serial_core.h> #include <linux/serial_8250.h> +#include <linux/of_fdt.h> +#include <linux/libfdt.h> #ifdef CONFIG_BLK_DEV_INITRD #include <linux/initrd.h> #endif @@ -797,3 +799,46 @@ void prom_free_prom_memory(void) } #endif } + +int octeon_prune_device_tree(void); + +extern const char __dtb_octeon_3xxx_begin; +extern const char __dtb_octeon_3xxx_end; +extern const char __dtb_octeon_68xx_begin; +extern const char __dtb_octeon_68xx_end; +void __init device_tree_init(void) +{ + int dt_size; + struct boot_param_header *fdt; + bool do_prune; + + if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { + fdt = phys_to_virt(octeon_bootinfo->fdt_addr); + if (fdt_check_header(fdt)) + panic("Corrupt Device Tree passed to kernel."); + dt_size = be32_to_cpu(fdt->totalsize); + do_prune = false; + } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { + fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; + dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; + do_prune = true; + } else { + fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; + dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; + do_prune = true; + } + + /* Copy the default tree from init memory. */ + initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); + if (initial_boot_params == NULL) + panic("Could not allocate initial_boot_params\n"); + memcpy(initial_boot_params, fdt, dt_size); + + if (do_prune) { + octeon_prune_device_tree(); + pr_info("Using internal Device Tree.\n"); + } else { + pr_info("Using passed Device Tree.\n"); + } + unflatten_device_tree(); +} -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/8] i2c: Convert i2c-octeon.c to use device tree. [not found] ` <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2011-11-11 2:21 ` [PATCH 2/8] MIPS: Prune some target specific code out of prom.c ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 2011-11-11 2:22 ` [PATCH 4/8] MIPS: Octeon: Initialize and fixup device tree ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w @ 2011-11-11 2:22 ` ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 2011-11-11 2:22 ` [PATCH 6/8] netdev: mdio-octeon.c: Convert " ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 3 siblings, 0 replies; 14+ messages in thread From: ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w @ 2011-11-11 2:22 UTC (permalink / raw) To: linux-mips-6z/3iImG2C8G8FEW9MqTrA, ralf-6z/3iImG2C8G8FEW9MqTrA, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, grant.likely-s3s/WqlpOiPyB63q8FvJNQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: Jean Delvare (PC drivers, core), linux-i2c-u79uwXL29TY76Z2rM5mHXA, Ben Dooks (embedded platforms), David Daney From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> Cc: "Jean Delvare (PC drivers, core)" <khali-PUYAD+kWke1g9hUCZPvPmw@public.gmane.org> Cc: "Ben Dooks (embedded platforms)" <ben-linux-elnMNo+KYs3YtjvyW6yDsg@public.gmane.org> Cc: linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> --- arch/mips/cavium-octeon/octeon-platform.c | 84 ------------------------- arch/mips/include/asm/octeon/octeon.h | 5 -- drivers/i2c/busses/i2c-octeon.c | 94 ++++++++++++++++------------- 3 files changed, 52 insertions(+), 131 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 2754bc2..f62a40f 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,90 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -static struct i2c_board_info __initdata octeon_i2c_devices[] = { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static int __init octeon_i2c_devices_init(void) -{ - return i2c_register_board_info(0, octeon_i2c_devices, - ARRAY_SIZE(octeon_i2c_devices)); -} -arch_initcall(octeon_i2c_devices_init); - -#define OCTEON_I2C_IO_BASE 0x1180000001000ull -#define OCTEON_I2C_IO_UNIT_OFFSET 0x200 - -static struct octeon_i2c_data octeon_i2c_data[2]; - -static int __init octeon_i2c_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource i2c_resources[] = { - { - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, - } - }; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) - num_ports = 2; - else - num_ports = 1; - - for (port = 0; port < num_ports; port++) { - octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate(); - /*FIXME: should be examined. At the moment is set for 100Khz */ - octeon_i2c_data[port].i2c_freq = 100000; - - pd = platform_device_alloc("i2c-octeon", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - pd->dev.platform_data = octeon_i2c_data + port; - - i2c_resources[0].start = - OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET); - i2c_resources[0].end = i2c_resources[0].start + 0x1f; - switch (port) { - case 0: - i2c_resources[1].start = OCTEON_IRQ_TWSI; - i2c_resources[1].end = OCTEON_IRQ_TWSI; - break; - case 1: - i2c_resources[1].start = OCTEON_IRQ_TWSI2; - i2c_resources[1].end = OCTEON_IRQ_TWSI2; - break; - default: - BUG(); - } - - ret = platform_device_add_resources(pd, - i2c_resources, - ARRAY_SIZE(i2c_resources)); - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); -out: - return ret; -} -device_initcall(octeon_i2c_device_init); - /* Octeon SMI/MDIO interface. */ static int __init octeon_mdiobus_device_init(void) { diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h index f72f768..1e2486e 100644 --- a/arch/mips/include/asm/octeon/octeon.h +++ b/arch/mips/include/asm/octeon/octeon.h @@ -215,11 +215,6 @@ struct octeon_cf_data { int dma_engine; /* -1 for no DMA */ }; -struct octeon_i2c_data { - unsigned int sys_freq; - unsigned int i2c_freq; -}; - extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); extern int octeon_get_boot_debug_flag(void); diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c index 56dbe54..e211c0b 100644 --- a/drivers/i2c/busses/i2c-octeon.c +++ b/drivers/i2c/busses/i2c-octeon.c @@ -2,7 +2,7 @@ * (C) Copyright 2009-2010 * Nokia Siemens Networks, michael.lawnick.ext-OYasijW0DpE@public.gmane.org * - * Portions Copyright (C) 2010 Cavium Networks, Inc. + * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc. * * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors. * @@ -11,17 +11,18 @@ * warranty of any kind, whether express or implied. */ +#include <linux/platform_device.h> +#include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of_i2c.h> +#include <linux/delay.h> #include <linux/sched.h> #include <linux/slab.h> #include <linux/init.h> - -#include <linux/io.h> #include <linux/i2c.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/of.h> #include <asm/octeon/octeon.h> @@ -121,10 +122,8 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) */ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) { - u64 tmp; - __raw_writeq(data, i2c->twsi_base + TWSI_INT); - tmp = __raw_readq(i2c->twsi_base + TWSI_INT); + __raw_readq(i2c->twsi_base + TWSI_INT); } /** @@ -515,94 +514,101 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) { int irq, result = 0; struct octeon_i2c *i2c; - struct octeon_i2c_data *i2c_data; struct resource *res_mem; + const __be32 *data; + int len; /* All adaptors have an irq. */ irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; - i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); if (!i2c) { dev_err(&pdev->dev, "kzalloc failed\n"); result = -ENOMEM; goto out; } i2c->dev = &pdev->dev; - i2c_data = pdev->dev.platform_data; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res_mem == NULL) { dev_err(i2c->dev, "found no memory resource\n"); result = -ENXIO; - goto fail_region; + goto out; } + i2c->twsi_phys = res_mem->start; + i2c->regsize = resource_size(res_mem); - if (i2c_data == NULL) { - dev_err(i2c->dev, "no I2C frequency data\n"); + /* + * "clock-rate" is a legacy binding, the official binding is + * "clock-frequency". Try the official one first and then + * fall back if it doesn't exist. + */ + data = of_get_property(pdev->dev.of_node, "clock-frequency", &len); + if (!data || len != sizeof(*data)) + data = of_get_property(pdev->dev.of_node, "clock-rate", &len); + if (data && len == sizeof(*data)) { + i2c->twsi_freq = be32_to_cpup(data); + } else { + dev_err(i2c->dev, + "no I2C 'clock-rate' or 'clock-frequency' property\n"); result = -ENXIO; - goto fail_region; + goto out; } - i2c->twsi_phys = res_mem->start; - i2c->regsize = resource_size(res_mem); - i2c->twsi_freq = i2c_data->i2c_freq; - i2c->sys_freq = i2c_data->sys_freq; + i2c->sys_freq = octeon_get_io_clock_rate(); - if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) { + if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize, + res_mem->name)) { dev_err(i2c->dev, "request_mem_region failed\n"); - goto fail_region; + goto out; } - i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize); + i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize); init_waitqueue_head(&i2c->queue); i2c->irq = irq; - result = request_irq(i2c->irq, octeon_i2c_isr, 0, DRV_NAME, i2c); + result = devm_request_irq(&pdev->dev, i2c->irq, + octeon_i2c_isr, 0, DRV_NAME, i2c); if (result < 0) { dev_err(i2c->dev, "failed to attach interrupt\n"); - goto fail_irq; + goto out; } result = octeon_i2c_initlowlevel(i2c); if (result) { dev_err(i2c->dev, "init low level failed\n"); - goto fail_add; + goto out; } result = octeon_i2c_setclock(i2c); if (result) { dev_err(i2c->dev, "clock init failed\n"); - goto fail_add; + goto out; } i2c->adap = octeon_i2c_ops; i2c->adap.dev.parent = &pdev->dev; - i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0; + i2c->adap.dev.of_node = pdev->dev.of_node; i2c_set_adapdata(&i2c->adap, i2c); platform_set_drvdata(pdev, i2c); - result = i2c_add_numbered_adapter(&i2c->adap); + result = i2c_add_adapter(&i2c->adap); if (result < 0) { dev_err(i2c->dev, "failed to add adapter\n"); goto fail_add; } - dev_info(i2c->dev, "version %s\n", DRV_VERSION); - return result; + of_i2c_register_devices(&i2c->adap); + + return 0; fail_add: platform_set_drvdata(pdev, NULL); - free_irq(i2c->irq, i2c); -fail_irq: - iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); -fail_region: - kfree(i2c); out: return result; }; @@ -613,19 +619,24 @@ static int __devexit octeon_i2c_remove(struct platform_device *pdev) i2c_del_adapter(&i2c->adap); platform_set_drvdata(pdev, NULL); - free_irq(i2c->irq, i2c); - iounmap(i2c->twsi_base); - release_mem_region(i2c->twsi_phys, i2c->regsize); - kfree(i2c); return 0; }; +static struct of_device_id octeon_i2c_match[] = { + { + .compatible = "cavium,octeon-3860-twsi", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_i2c_match); + static struct platform_driver octeon_i2c_driver = { .probe = octeon_i2c_probe, .remove = __devexit_p(octeon_i2c_remove), .driver = { .owner = THIS_MODULE, .name = DRV_NAME, + .of_match_table = octeon_i2c_match, }, }; @@ -646,7 +657,6 @@ MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext-OYasijW0DpE@public.gmane.org>"); MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_VERSION); -MODULE_ALIAS("platform:" DRV_NAME); module_init(octeon_i2c_init); module_exit(octeon_i2c_exit); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/8] netdev: mdio-octeon.c: Convert to use device tree. [not found] ` <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> ` (2 preceding siblings ...) 2011-11-11 2:22 ` [PATCH 5/8] i2c: Convert i2c-octeon.c to use " ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w @ 2011-11-11 2:22 ` ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w 3 siblings, 0 replies; 14+ messages in thread From: ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w @ 2011-11-11 2:22 UTC (permalink / raw) To: linux-mips-6z/3iImG2C8G8FEW9MqTrA, ralf-6z/3iImG2C8G8FEW9MqTrA, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ, grant.likely-s3s/WqlpOiPyB63q8FvJNQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA Cc: netdev-u79uwXL29TY76Z2rM5mHXA, David S. Miller, David Daney From: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> Get the MDIO bus controller addresses from the device tree. Cc: "David S. Miller" <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org> Cc: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Acked-by: David S. Miller <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org> Signed-off-by: David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> --- arch/mips/cavium-octeon/octeon-platform.c | 30 ---------- drivers/net/phy/mdio-octeon.c | 89 +++++++++++++++++++---------- 2 files changed, 58 insertions(+), 61 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index f62a40f..66cabc2 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,36 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon SMI/MDIO interface. */ -static int __init octeon_mdiobus_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - - if (octeon_is_simulation()) - return 0; /* No mdio in the simulator. */ - - /* The bus number is the platform_device id. */ - pd = platform_device_alloc("mdio-octeon", 0); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - ret = platform_device_add(pd); - if (ret) - goto fail; - - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mdiobus_device_init); - /* Octeon mgmt port Ethernet interface. */ static int __init octeon_mgmt_device_init(void) { diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index bd12ba9..b18b8c5 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -3,14 +3,17 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2009 Cavium Networks + * Copyright (C) 2009, 2010, 2011 Cavium Networks */ -#include <linux/gfp.h> -#include <linux/init.h> -#include <linux/module.h> #include <linux/platform_device.h> +#include <linux/of_mdio.h> +#include <linux/delay.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/gfp.h> #include <linux/phy.h> +#include <linux/io.h> #include <asm/octeon/octeon.h> #include <asm/octeon/cvmx-smix-defs.h> @@ -18,9 +21,17 @@ #define DRV_VERSION "1.0" #define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver" +#define SMI_CMD 0x0 +#define SMI_WR_DAT 0x8 +#define SMI_RD_DAT 0x10 +#define SMI_CLK 0x18 +#define SMI_EN 0x20 + struct octeon_mdiobus { struct mii_bus *mii_bus; - int unit; + u64 register_base; + resource_size_t mdio_phys; + resource_size_t regsize; int phy_irq[PHY_MAX_ADDR]; }; @@ -35,15 +46,15 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum) smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit)); + __delay(1000); + smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT); } while (smi_rd.s.pending && --timeout); if (smi_rd.s.val) @@ -62,21 +73,21 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, smi_wr.u64 = 0; smi_wr.s.dat = val; - cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64); + cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64); smi_cmd.u64 = 0; smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); + cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - cvmx_wait(1000); - smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit)); + __delay(1000); + smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT); } while (smi_wr.s.pending && --timeout); if (timeout <= 0) @@ -88,8 +99,8 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) { struct octeon_mdiobus *bus; + struct resource *res_mem; union cvmx_smix_en smi_en; - int i; int err = -ENOENT; bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); @@ -97,28 +108,37 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) return -ENOMEM; /* The platform_device id is our unit number. */ - bus->unit = pdev->id; + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (res_mem == NULL) { + dev_err(&pdev->dev, "found no memory resource\n"); + err = -ENXIO; + goto fail; + } + bus->mdio_phys = res_mem->start; + bus->regsize = resource_size(res_mem); + if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize, + res_mem->name)) { + dev_err(&pdev->dev, "request_mem_region failed\n"); + goto fail; + } + bus->register_base = + (u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize); bus->mii_bus = mdiobus_alloc(); if (!bus->mii_bus) - goto err; + goto fail; smi_en.u64 = 0; smi_en.s.en = 1; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); - /* - * Standard Octeon evaluation boards don't support phy - * interrupts, we need to poll. - */ - for (i = 0; i < PHY_MAX_ADDR; i++) - bus->phy_irq[i] = PHY_POLL; bus->mii_bus->priv = bus; bus->mii_bus->irq = bus->phy_irq; bus->mii_bus->name = "mdio-octeon"; - snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%x", bus->unit); + snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base); bus->mii_bus->parent = &pdev->dev; bus->mii_bus->read = octeon_mdiobus_read; @@ -126,20 +146,18 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, bus); - err = mdiobus_register(bus->mii_bus); + err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node); if (err) - goto err_register; + goto fail_register; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; -err_register: +fail_register: mdiobus_free(bus->mii_bus); - -err: - devm_kfree(&pdev->dev, bus); +fail: smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); return err; } @@ -153,14 +171,23 @@ static int __devexit octeon_mdiobus_remove(struct platform_device *pdev) mdiobus_unregister(bus->mii_bus); mdiobus_free(bus->mii_bus); smi_en.u64 = 0; - cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); return 0; } +static struct of_device_id octeon_mdiobus_match[] = { + { + .compatible = "cavium,octeon-3860-mdio", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mdiobus_match); + static struct platform_driver octeon_mdiobus_driver = { .driver = { .name = "mdio-octeon", .owner = THIS_MODULE, + .of_match_table = octeon_mdiobus_match, }, .probe = octeon_mdiobus_probe, .remove = __devexit_p(octeon_mdiobus_remove), -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 7/8] netdev: octeon_mgmt: Convert to use device tree. 2011-11-11 2:21 [PATCH 0/8] of/MIPS/i2c/net: Convert OCTEON to use device-tree ddaney.cavm ` (2 preceding siblings ...) [not found] ` <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2011-11-11 2:22 ` ddaney.cavm 2011-11-11 2:22 ` [PATCH 8/8] staging: octeon_ethernet: " ddaney.cavm 4 siblings, 0 replies; 14+ messages in thread From: ddaney.cavm @ 2011-11-11 2:22 UTC (permalink / raw) To: linux-mips, ralf, devicetree-discuss, grant.likely, linux-kernel Cc: David Daney, David S. Miller, netdev From: David Daney <david.daney@cavium.com> The device tree will supply the register bank base addresses, make register addressing relative to those. PHY connection is now described by the device tree. Cc: "David S. Miller" <davem@davemloft.net> Cc: netdev@vger.kernel.org Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: David Daney <david.daney@cavium.com> --- arch/mips/cavium-octeon/octeon-platform.c | 62 ------ drivers/net/ethernet/octeon/octeon_mgmt.c | 312 +++++++++++++++++++---------- 2 files changed, 207 insertions(+), 167 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 66cabc2..0938df1 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -168,68 +168,6 @@ out: } device_initcall(octeon_rng_device_init); -/* Octeon mgmt port Ethernet interface. */ -static int __init octeon_mgmt_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource mgmt_port_resource = { - .flags = IORESOURCE_IRQ, - .start = -1, - .end = -1 - }; - - if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX)) - return 0; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - num_ports = 1; - else - num_ports = 2; - - for (port = 0; port < num_ports; port++) { - pd = platform_device_alloc("octeon_mgmt", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - /* No DMA restrictions */ - pd->dev.coherent_dma_mask = DMA_BIT_MASK(64); - pd->dev.dma_mask = &pd->dev.coherent_dma_mask; - - switch (port) { - case 0: - mgmt_port_resource.start = OCTEON_IRQ_MII0; - break; - case 1: - mgmt_port_resource.start = OCTEON_IRQ_MII1; - break; - default: - BUG(); - } - mgmt_port_resource.end = mgmt_port_resource.start; - - ret = platform_device_add_resources(pd, &mgmt_port_resource, 1); - - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mgmt_device_init); - #ifdef CONFIG_USB static int __init octeon_ehci_device_init(void) diff --git a/drivers/net/ethernet/octeon/octeon_mgmt.c b/drivers/net/ethernet/octeon/octeon_mgmt.c index 212f43b..c42bbb1 100644 --- a/drivers/net/ethernet/octeon/octeon_mgmt.c +++ b/drivers/net/ethernet/octeon/octeon_mgmt.c @@ -6,19 +6,21 @@ * Copyright (C) 2009 Cavium Networks */ -#include <linux/capability.h> +#include <linux/platform_device.h> #include <linux/dma-mapping.h> -#include <linux/init.h> -#include <linux/module.h> +#include <linux/etherdevice.h> +#include <linux/capability.h> #include <linux/interrupt.h> -#include <linux/platform_device.h> #include <linux/netdevice.h> -#include <linux/etherdevice.h> -#include <linux/if.h> +#include <linux/spinlock.h> #include <linux/if_vlan.h> +#include <linux/of_mdio.h> +#include <linux/module.h> +#include <linux/of_net.h> +#include <linux/init.h> #include <linux/slab.h> #include <linux/phy.h> -#include <linux/spinlock.h> +#include <linux/io.h> #include <asm/octeon/octeon.h> #include <asm/octeon/cvmx-mixx-defs.h> @@ -58,8 +60,56 @@ union mgmt_port_ring_entry { } s; }; +#define MIX_ORING1 0x0 +#define MIX_ORING2 0x8 +#define MIX_IRING1 0x10 +#define MIX_IRING2 0x18 +#define MIX_CTL 0x20 +#define MIX_IRHWM 0x28 +#define MIX_IRCNT 0x30 +#define MIX_ORHWM 0x38 +#define MIX_ORCNT 0x40 +#define MIX_ISR 0x48 +#define MIX_INTENA 0x50 +#define MIX_REMCNT 0x58 +#define MIX_BIST 0x78 + +#define AGL_GMX_PRT_CFG 0x10 +#define AGL_GMX_RX_FRM_CTL 0x18 +#define AGL_GMX_RX_FRM_MAX 0x30 +#define AGL_GMX_RX_JABBER 0x38 +#define AGL_GMX_RX_STATS_CTL 0x50 + +#define AGL_GMX_RX_STATS_PKTS_DRP 0xb0 +#define AGL_GMX_RX_STATS_OCTS_DRP 0xb8 +#define AGL_GMX_RX_STATS_PKTS_BAD 0xc0 + +#define AGL_GMX_RX_ADR_CTL 0x100 +#define AGL_GMX_RX_ADR_CAM_EN 0x108 +#define AGL_GMX_RX_ADR_CAM0 0x180 +#define AGL_GMX_RX_ADR_CAM1 0x188 +#define AGL_GMX_RX_ADR_CAM2 0x190 +#define AGL_GMX_RX_ADR_CAM3 0x198 +#define AGL_GMX_RX_ADR_CAM4 0x1a0 +#define AGL_GMX_RX_ADR_CAM5 0x1a8 + +#define AGL_GMX_TX_STATS_CTL 0x268 +#define AGL_GMX_TX_CTL 0x270 +#define AGL_GMX_TX_STAT0 0x280 +#define AGL_GMX_TX_STAT1 0x288 +#define AGL_GMX_TX_STAT2 0x290 +#define AGL_GMX_TX_STAT3 0x298 +#define AGL_GMX_TX_STAT4 0x2a0 +#define AGL_GMX_TX_STAT5 0x2a8 +#define AGL_GMX_TX_STAT6 0x2b0 +#define AGL_GMX_TX_STAT7 0x2b8 +#define AGL_GMX_TX_STAT8 0x2c0 +#define AGL_GMX_TX_STAT9 0x2c8 + struct octeon_mgmt { struct net_device *netdev; + u64 mix; + u64 agl; int port; int irq; u64 *tx_ring; @@ -85,31 +135,34 @@ struct octeon_mgmt { struct napi_struct napi; struct tasklet_struct tx_clean_tasklet; struct phy_device *phydev; + struct device_node *phy_np; + resource_size_t mix_phys; + resource_size_t mix_size; + resource_size_t agl_phys; + resource_size_t agl_size; }; static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.ithena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) { - int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); + mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); mix_intena.s.othena = enable ? 1 : 0; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -146,7 +199,6 @@ static unsigned int ring_size_to_bytes(unsigned int ring_size) static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { unsigned int size; @@ -177,24 +229,23 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; p->rx_current_fill++; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); + cvmx_write_csr(p->mix + MIX_IRING2, 1); } } static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) { - int port = p->port; union cvmx_mixx_orcnt mix_orcnt; union mgmt_port_ring_entry re; struct sk_buff *skb; int cleaned = 0; unsigned long flags; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); while (mix_orcnt.s.orcnt) { spin_lock_irqsave(&p->tx_list.lock, flags); - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); if (mix_orcnt.s.orcnt == 0) { spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -214,7 +265,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) mix_orcnt.s.orcnt = 1; /* Acknowledge to hardware that we have the buffer. */ - cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64); + cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); p->tx_current_fill--; spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -224,7 +275,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) dev_kfree_skb_any(skb); cleaned++; - mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); + mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); } if (cleaned && netif_queue_stopped(p->netdev)) @@ -241,13 +292,12 @@ static void octeon_mgmt_clean_tx_tasklet(unsigned long arg) static void octeon_mgmt_update_rx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; u64 drop, bad; /* These reads also clear the count registers. */ - drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port)); - bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port)); + drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); + bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); if (drop || bad) { /* Do an atomic update. */ @@ -261,15 +311,14 @@ static void octeon_mgmt_update_rx_stats(struct net_device *netdev) static void octeon_mgmt_update_tx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; unsigned long flags; union cvmx_agl_gmx_txx_stat0 s0; union cvmx_agl_gmx_txx_stat1 s1; /* These reads also clear the count registers. */ - s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port)); - s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port)); + s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); + s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { /* Do an atomic update. */ @@ -308,7 +357,6 @@ static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p, static int octeon_mgmt_receive_one(struct octeon_mgmt *p) { - int port = p->port; struct net_device *netdev = p->netdev; union cvmx_mixx_ircnt mix_ircnt; union mgmt_port_ring_entry re; @@ -381,18 +429,17 @@ done: /* Tell the hardware we processed a packet. */ mix_ircnt.u64 = 0; mix_ircnt.s.ircnt = 1; - cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64); + cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); return rc; } static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) { - int port = p->port; unsigned int work_done = 0; union cvmx_mixx_ircnt mix_ircnt; int rc; - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); while (work_done < budget && mix_ircnt.s.ircnt) { rc = octeon_mgmt_receive_one(p); @@ -400,7 +447,7 @@ static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) work_done++; /* Check for more packets. */ - mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); + mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); } octeon_mgmt_rx_fill_ring(p->netdev); @@ -434,16 +481,16 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) union cvmx_agl_gmx_bist agl_gmx_bist; mix_ctl.u64 = 0; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.busy); mix_ctl.s.reset = 1; - cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); - cvmx_read_csr(CVMX_MIXX_CTL(p->port)); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); + cvmx_read_csr(p->mix + MIX_CTL); cvmx_wait(64); - mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port)); + mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); if (mix_bist.u64) dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", (unsigned long long)mix_bist.u64); @@ -474,7 +521,6 @@ static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs, static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; unsigned long flags; @@ -520,29 +566,29 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) spin_lock_irqsave(&p->lock, flags); /* Disable packet I/O. */ - agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prev_packet_enable = agl_gmx_prtx.s.en; agl_gmx_prtx.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); adr_ctl.u64 = 0; adr_ctl.s.cam_mode = cam_mode; adr_ctl.s.mcst = multicast_mode; adr_ctl.s.bcst = 1; /* Allow broadcast */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]); - cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); + cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); /* Restore packet I/O. */ agl_gmx_prtx.s.en = prev_packet_enable; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -564,7 +610,6 @@ static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; /* @@ -580,8 +625,8 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) netdev->mtu = new_mtu; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs); - cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs); + cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, (size_without_fcs + 7) & 0xfff8); return 0; @@ -591,14 +636,13 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) { struct net_device *netdev = dev_id; struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_mixx_isr mixx_isr; - mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port)); + mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64); - cvmx_read_csr(CVMX_MIXX_ISR(port)); + cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); + cvmx_read_csr(p->mix + MIX_ISR); if (mixx_isr.s.irthresh) { octeon_mgmt_disable_rx_irq(p); @@ -629,7 +673,6 @@ static int octeon_mgmt_ioctl(struct net_device *netdev, static void octeon_mgmt_adjust_link(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union cvmx_agl_gmx_prtx_cfg prtx_cfg; unsigned long flags; int link_changed = 0; @@ -640,11 +683,9 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) link_changed = 1; if (p->last_duplex != p->phydev->duplex) { p->last_duplex = p->phydev->duplex; - prtx_cfg.u64 = - cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.duplex = p->phydev->duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), - prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); } } else { if (p->last_link) @@ -670,18 +711,16 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) static int octeon_mgmt_init_phy(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - char phy_id[20]; - if (octeon_is_simulation()) { + if (octeon_is_simulation() || p->phy_np == NULL) { /* No PHYs in the simulator. */ netif_carrier_on(netdev); return 0; } - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", p->port); - - p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0, - PHY_INTERFACE_MODE_MII); + p->phydev = of_phy_connect(netdev, p->phy_np, + octeon_mgmt_adjust_link, 0, + PHY_INTERFACE_MODE_MII); if (IS_ERR(p->phydev)) { p->phydev = NULL; @@ -737,14 +776,14 @@ static int octeon_mgmt_open(struct net_device *netdev) octeon_mgmt_reset_hw(p); - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); /* Bring it out of reset if needed. */ if (mix_ctl.s.reset) { mix_ctl.s.reset = 0; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); + mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); } while (mix_ctl.s.reset); } @@ -755,17 +794,17 @@ static int octeon_mgmt_open(struct net_device *netdev) oring1.u64 = 0; oring1.s.obase = p->tx_ring_handle >> 3; oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); + cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); iring1.u64 = 0; iring1.s.ibase = p->rx_ring_handle >> 3; iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; - cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64); + cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); /* Disable packet I/O. */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.en = 0; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); octeon_mgmt_set_mac_address(netdev, &sa); @@ -782,7 +821,7 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_ctl.s.nbtarb = 0; /* Arbitration mode */ /* MII CB-request FIFO programmable high watermark */ mix_ctl.s.mrq_hwm = 1; - cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); + cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { @@ -809,16 +848,16 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Clear statistics. */ /* Clear on read. */ - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); + cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0); - cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); + cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); /* Clear any pending interrupts */ - cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port))); + cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, netdev)) { @@ -829,18 +868,18 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Interrupt every single RX packet */ mix_irhwm.u64 = 0; mix_irhwm.s.irhwm = 0; - cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64); + cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); /* Interrupt when we have 1 or more packets to clean. */ mix_orhwm.u64 = 0; mix_orhwm.s.orhwm = 1; - cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64); + cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); /* Enable receive and transmit interrupts */ mix_intena.u64 = 0; mix_intena.s.ithena = 1; mix_intena.s.othena = 1; - cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); + cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); /* Enable packet I/O. */ @@ -871,7 +910,7 @@ static int octeon_mgmt_open(struct net_device *netdev) * frame. GMX checks that the PREAMBLE is sent correctly. */ rxx_frm_ctl.s.pre_chk = 1; - cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); + cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); /* Enable the AGL block */ agl_gmx_inf_mode.u64 = 0; @@ -879,13 +918,13 @@ static int octeon_mgmt_open(struct net_device *netdev) cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); /* Configure the port duplex and enables */ - prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); + prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); prtx_cfg.s.tx_en = 1; prtx_cfg.s.rx_en = 1; prtx_cfg.s.en = 1; p->last_duplex = 1; prtx_cfg.s.duplex = p->last_duplex; - cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); + cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); p->last_link = 0; netif_carrier_off(netdev); @@ -949,7 +988,6 @@ static int octeon_mgmt_stop(struct net_device *netdev) static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); - int port = p->port; union mgmt_port_ring_entry re; unsigned long flags; int rv = NETDEV_TX_BUSY; @@ -993,7 +1031,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) netdev->stats.tx_bytes += skb->len; /* Ring the bell. */ - cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); + cvmx_write_csr(p->mix + MIX_ORING2, 1); rv = NETDEV_TX_OK; out: @@ -1071,10 +1109,14 @@ static const struct net_device_ops octeon_mgmt_ops = { static int __devinit octeon_mgmt_probe(struct platform_device *pdev) { - struct resource *res_irq; struct net_device *netdev; struct octeon_mgmt *p; - int i; + const __be32 *data; + const u8 *mac; + struct resource *res_mix; + struct resource *res_agl; + int len; + int result; netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); if (netdev == NULL) @@ -1088,14 +1130,63 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) p->netdev = netdev; p->dev = &pdev->dev; - p->port = pdev->id; + data = of_get_property(pdev->dev.of_node, "cell-index", &len); + if (data && len == sizeof(*data)) { + p->port = be32_to_cpup(data); + } else { + dev_err(&pdev->dev, "no 'cell-index' property\n"); + result = -ENXIO; + goto err; + } + snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_irq) + result = platform_get_irq(pdev, 0); + if (result < 0) + goto err; + + p->irq = result; + + res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_mix == NULL) { + dev_err(&pdev->dev, "no 'reg' resource\n"); + result = -ENXIO; + goto err; + } + + res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res_agl == NULL) { + dev_err(&pdev->dev, "no 'reg' resource\n"); + result = -ENXIO; + goto err; + } + + p->mix_phys = res_mix->start; + p->mix_size = resource_size(res_mix); + p->agl_phys = res_agl->start; + p->agl_size = resource_size(res_agl); + + + if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, + res_mix->name)) { + dev_err(&pdev->dev, "request_mem_region (%s) failed\n", + res_mix->name); + result = -ENXIO; + goto err; + } + + if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size, + res_agl->name)) { + result = -ENXIO; + dev_err(&pdev->dev, "request_mem_region (%s) failed\n", + res_agl->name); goto err; + } + + + p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size); + p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size); - p->irq = res_irq->start; spin_lock_init(&p->lock); skb_queue_head_init(&p->tx_list); @@ -1108,24 +1199,26 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) netdev->netdev_ops = &octeon_mgmt_ops; netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; - /* The mgmt ports get the first N MACs. */ - for (i = 0; i < 6; i++) - netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i]; - netdev->dev_addr[5] += p->port; + mac = of_get_mac_address(pdev->dev.of_node); + + if (mac) + memcpy(netdev->dev_addr, mac, 6); - if (p->port >= octeon_bootinfo->mac_addr_count) - dev_err(&pdev->dev, - "Error %s: Using MAC outside of the assigned range: %pM\n", - netdev->name, netdev->dev_addr); + p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); - if (register_netdev(netdev)) + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + + result = register_netdev(netdev); + if (result) goto err; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; + err: free_netdev(netdev); - return -ENOENT; + return result; } static int __devexit octeon_mgmt_remove(struct platform_device *pdev) @@ -1137,10 +1230,19 @@ static int __devexit octeon_mgmt_remove(struct platform_device *pdev) return 0; } +static struct of_device_id octeon_mgmt_match[] = { + { + .compatible = "cavium,octeon-5750-mix", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, octeon_mgmt_match); + static struct platform_driver octeon_mgmt_driver = { .driver = { .name = "octeon_mgmt", .owner = THIS_MODULE, + .of_match_table = octeon_mgmt_match, }, .probe = octeon_mgmt_probe, .remove = __devexit_p(octeon_mgmt_remove), -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 8/8] staging: octeon_ethernet: Convert to use device tree. 2011-11-11 2:21 [PATCH 0/8] of/MIPS/i2c/net: Convert OCTEON to use device-tree ddaney.cavm ` (3 preceding siblings ...) 2011-11-11 2:22 ` [PATCH 7/8] netdev: octeon_mgmt: " ddaney.cavm @ 2011-11-11 2:22 ` ddaney.cavm 2011-11-27 2:04 ` Greg KH 4 siblings, 1 reply; 14+ messages in thread From: ddaney.cavm @ 2011-11-11 2:22 UTC (permalink / raw) To: linux-mips, ralf, devicetree-discuss, grant.likely, linux-kernel Cc: David Daney, David S. Miller, netdev, Greg Kroah-Hartman, devel From: David Daney <david.daney@cavium.com> Get MAC address and PHY connection from the device tree. Cc: "David S. Miller" <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: devel@driverdev.osuosl.org Signed-off-by: David Daney <david.daney@cavium.com> --- drivers/staging/octeon/ethernet-mdio.c | 28 +++++---- drivers/staging/octeon/ethernet.c | 91 ++++++++++++++++++------------ drivers/staging/octeon/octeon-ethernet.h | 3 + 3 files changed, 72 insertions(+), 50 deletions(-) diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 63800ba..f15b31b 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -28,6 +28,7 @@ #include <linux/ethtool.h> #include <linux/phy.h> #include <linux/ratelimit.h> +#include <linux/of_mdio.h> #include <net/dst.h> @@ -161,22 +162,23 @@ static void cvm_oct_adjust_link(struct net_device *dev) int cvm_oct_phy_setup_device(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); + struct device_node *phy_node; - int phy_addr = cvmx_helper_board_get_mii_address(priv->port); - if (phy_addr != -1) { - char phy_id[20]; + if (!priv->of_node) + return 0; - snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "0", phy_addr); + phy_node = of_parse_phandle(priv->of_node, "phy-handle", 0); + if (!phy_node) + return 0; - priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, - PHY_INTERFACE_MODE_GMII); + priv->phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0, + PHY_INTERFACE_MODE_GMII); + + if (priv->phydev == NULL) + return -ENODEV; + + priv->last_link = 0; + phy_start_aneg(priv->phydev); - if (IS_ERR(priv->phydev)) { - priv->phydev = NULL; - return -1; - } - priv->last_link = 0; - phy_start_aneg(priv->phydev); - } return 0; } diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 9112cd8..5e96da6 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -31,6 +31,7 @@ #include <linux/etherdevice.h> #include <linux/phy.h> #include <linux/slab.h> +#include <linux/of_net.h> #include <net/dst.h> @@ -112,15 +113,6 @@ int rx_napi_weight = 32; module_param(rx_napi_weight, int, 0444); MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); -/* - * The offset from mac_addr_base that should be used for the next port - * that is configured. By convention, if any mgmt ports exist on the - * chip, they get the first mac addresses, The ports controlled by - * this driver are numbered sequencially following any mgmt addresses - * that may exist. - */ -static unsigned int cvm_oct_mac_addr_offset; - /** * cvm_oct_poll_queue - Workqueue for polling operations. */ @@ -447,26 +439,16 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) int cvm_oct_common_init(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); - struct sockaddr sa; - u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) | - ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) | - ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) | - ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) | - ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) | - (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff); - - mac += cvm_oct_mac_addr_offset; - sa.sa_data[0] = (mac >> 40) & 0xff; - sa.sa_data[1] = (mac >> 32) & 0xff; - sa.sa_data[2] = (mac >> 24) & 0xff; - sa.sa_data[3] = (mac >> 16) & 0xff; - sa.sa_data[4] = (mac >> 8) & 0xff; - sa.sa_data[5] = mac & 0xff; - - if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count) - printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:" - " %pM\n", dev->name, sa.sa_data); - cvm_oct_mac_addr_offset++; + struct sockaddr sa = {0}; + const u8 *mac = NULL; + + if (priv->of_node) + mac = of_get_mac_address(priv->of_node); + + if (mac) + memcpy(sa.sa_data, mac, ETH_ALEN); + else + dev_hw_addr_random(dev, sa.sa_data); /* * Force the interface to use the POW send if always_use_pow @@ -594,22 +576,55 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = { extern void octeon_mdiobus_force_mod_depencency(void); +static struct device_node * __init cvm_oct_of_get_child(const struct device_node *parent, + int reg_val) +{ + struct device_node *node = NULL; + int size; + const __be32 *addr; + + for (;;) { + node = of_get_next_child(parent, node); + if (!node) + break; + addr = of_get_property(node, "reg", &size); + if (addr && (be32_to_cpu(*addr) == reg_val)) + break; + } + return node; +} + +static struct device_node * __init cvm_oct_node_for_port(struct device_node *pip, + int interface, int port) +{ + struct device_node *ni, *np; + + ni = cvm_oct_of_get_child(pip, interface); + if (!ni) + return NULL; + + np = cvm_oct_of_get_child(ni, port); + of_node_put(ni); + + return np; +} + static int __init cvm_oct_init_module(void) { int num_interfaces; int interface; int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; int qos; + struct device_node *pip; octeon_mdiobus_force_mod_depencency(); pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) - cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */ - else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */ - else - cvm_oct_mac_addr_offset = 0; + pip = of_find_node_by_path("pip"); + if (!pip) { + pr_err("Error: No 'pip' in /aliases\n"); + return -EINVAL; + } cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet"); if (cvm_oct_poll_queue == NULL) { @@ -688,10 +703,11 @@ static int __init cvm_oct_init_module(void) cvmx_helper_interface_get_mode(interface); int num_ports = cvmx_helper_ports_on_interface(interface); int port; + int port_index; - for (port = cvmx_helper_get_ipd_port(interface, 0); + for (port_index = 0, port = cvmx_helper_get_ipd_port(interface, 0); port < cvmx_helper_get_ipd_port(interface, num_ports); - port++) { + port_index++, port++) { struct octeon_ethernet *priv; struct net_device *dev = alloc_etherdev(sizeof(struct octeon_ethernet)); @@ -702,6 +718,7 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ priv = netdev_priv(dev); + priv->of_node = cvm_oct_node_for_port(pip, interface, port_index); INIT_DELAYED_WORK(&priv->port_periodic_work, cvm_oct_periodic_worker); diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index d581925..9360e22 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -31,6 +31,8 @@ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H +#include <linux/of.h> + /** * This is the definition of the Ethernet driver's private * driver state stored in netdev_priv(dev). @@ -59,6 +61,7 @@ struct octeon_ethernet { void (*poll) (struct net_device *dev); struct delayed_work port_periodic_work; struct work_struct port_work; /* may be unused. */ + struct device_node *of_node; }; int cvm_oct_free_work(void *work_queue_entry); -- 1.7.2.3 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 8/8] staging: octeon_ethernet: Convert to use device tree. 2011-11-11 2:22 ` [PATCH 8/8] staging: octeon_ethernet: " ddaney.cavm @ 2011-11-27 2:04 ` Greg KH 0 siblings, 0 replies; 14+ messages in thread From: Greg KH @ 2011-11-27 2:04 UTC (permalink / raw) To: ddaney.cavm Cc: linux-mips, ralf, devicetree-discuss, grant.likely, linux-kernel, David Daney, David S. Miller, netdev, Greg Kroah-Hartman, devel On Thu, Nov 10, 2011 at 06:22:04PM -0800, ddaney.cavm@gmail.com wrote: > From: David Daney <david.daney@cavium.com> > > Get MAC address and PHY connection from the device tree. > > Cc: "David S. Miller" <davem@davemloft.net> > Cc: netdev@vger.kernel.org > Cc: Greg Kroah-Hartman <gregkh@suse.de> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> This usually goes through the MIPS tree, so I'll let Ralf take it. thanks, greg k-h ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2011-11-27 2:04 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2011-11-11 2:21 [PATCH 0/8] of/MIPS/i2c/net: Convert OCTEON to use device-tree ddaney.cavm
2011-11-11 2:21 ` [PATCH 1/8] MIPS: Octeon: Add device tree source files ddaney.cavm
2011-11-11 2:21 ` [PATCH 3/8] MIPS: Octeon: Add irq_create_of_mapping() and GPIO interrupts ddaney.cavm
[not found] ` <1320978124-13042-4-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-11 16:08 ` Rob Herring
[not found] ` <4EBD4868.7040809-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-11 19:49 ` David Daney
[not found] ` <4EBD7C5D.7080606-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-11 20:41 ` Rob Herring
[not found] ` <4EBD8867.30205-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-11 20:45 ` David Daney
[not found] ` <1320978124-13042-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2011-11-11 2:21 ` [PATCH 2/8] MIPS: Prune some target specific code out of prom.c ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w
2011-11-11 2:22 ` [PATCH 4/8] MIPS: Octeon: Initialize and fixup device tree ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w
2011-11-11 2:22 ` [PATCH 5/8] i2c: Convert i2c-octeon.c to use " ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w
2011-11-11 2:22 ` [PATCH 6/8] netdev: mdio-octeon.c: Convert " ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w
2011-11-11 2:22 ` [PATCH 7/8] netdev: octeon_mgmt: " ddaney.cavm
2011-11-11 2:22 ` [PATCH 8/8] staging: octeon_ethernet: " ddaney.cavm
2011-11-27 2:04 ` Greg KH
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