[PATCH v3 0/4] ARM: OMAP2+: Interrupt controllers adaptation to DT

[PATCH v3 0/4] ARM: OMAP2+: Interrupt controllers adaptation to DT

[Benoit Cousson]

Hi Tony and Rob,

Here is a small update of the INTC controller series that was already
acked-by in the v2 [1].
This version is just updating the #2 patch to take advantage of the new
irq_domain_add_legacy API introduced by Grant.

Please note that in the near future that code can even be simplier with
the introduction of the domain support inside generic irq chip.

This series is based on lo/master + for_3.4/dt_base branch to get the needed
cleanup and fixes for OMAP.
It requires as well Grant's irq_domain generalization and refinement
series available at:
  git://git.secretlab.ca/git/linux-2.6 irqdomain/next

The series is available here for reference:
git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt.git for_3.4/dt_irq_domain

Regards,
Benoit


[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/079467.html


Benoit Cousson (4):
  arm/dts: OMAP4: Update DTS file with new GIC bindings
  ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
  arm/dts: OMAP3: Add interrupt-controller bindings for INTC
  ARM: OMAP2+: board-generic: Use of_irq_init API

 .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++
 arch/arm/boot/dts/omap3.dtsi                       |    6 +-
 arch/arm/boot/dts/omap4.dtsi                       |    2 +-
 arch/arm/mach-omap2/board-generic.c                |   30 +++++-----
 arch/arm/mach-omap2/common.h                       |   10 +++
 arch/arm/mach-omap2/irq.c                          |   59 ++++++++++++++++---
 6 files changed, 107 insertions(+), 27 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

[PATCH v3 1/4] arm/dts: OMAP4: Update DTS file with new GIC bindings

[Benoit Cousson]

The GIC binding was updated in 3.2 and expects 3 interrupt-cells.
- Update the #interrupt-cells

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
---
 arch/arm/boot/dts/omap4.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index e8fe75f..70a44f6 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -99,7 +99,7 @@
 		gic: interrupt-controller@48241000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
-			#interrupt-cells = <1>;
+			#interrupt-cells = <3>;
 			reg = <0x48241000 0x1000>,
 			      <0x48240100 0x0100>;
 		};
-- 
1.7.0.4

[PATCH v3 2/4] ARM: OMAP2/3: intc: Add DT support for TI interrupt controller

[Benoit Cousson]

Add a function to initialize the OMAP2/3 interrupt controller (INTC)
using a device tree node.

This version take advantage of the new irq_domain_add_legacy API.

Replace some printk() with the proper pr_ macro.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
---
 .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++
 arch/arm/mach-omap2/common.h                       |   10 +++
 arch/arm/mach-omap2/irq.c                          |   59 ++++++++++++++++---
 3 files changed, 86 insertions(+), 10 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

diff --git a/Documentation/devicetree/bindings/arm/omap/intc.txt b/Documentation/devicetree/bindings/arm/omap/intc.txt
new file mode 100644
index 0000000..f2583e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/intc.txt
@@ -0,0 +1,27 @@
+* OMAP Interrupt Controller
+
+OMAP2/3 are using a TI interrupt controller that can support several
+configurable number of interrupts.
+
+Main node required properties:
+
+- compatible : should be:
+	"ti,omap2-intc"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 1.
+
+  The cell contains the interrupt number in the range [0-128].
+- ti,intc-size: Number of interrupts handled by the interrupt controller.
+- reg: physical base address and size of the intc registers map.
+
+Example:
+
+	intc: interrupt-controller@1 {
+		compatible = "ti,omap2-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		ti,intc-size = <96>;
+		reg = <0x48200000 0x1000>;
+	};
+
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index febffde..a87ce52 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -174,6 +174,16 @@ void omap3_intc_handle_irq(struct pt_regs *regs);
 extern void __iomem *omap4_get_l2cache_base(void);
 #endif
 
+struct device_node;
+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node *parent);
+#else
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_SMP
 extern void __iomem *omap4_get_scu_base(void);
 #else
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 1fef061..e2d0f33 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -11,12 +11,16 @@
  * for more details.
  */
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 
 /* selected INTC register offsets */
@@ -57,6 +61,8 @@ static struct omap_irq_bank {
 	},
 };
 
+static struct irq_domain *domain;
+
 /* Structure to save interrupt controller context */
 struct omap3_intc_regs {
 	u32 sysconfig;
@@ -147,17 +153,27 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 }
 
-static void __init omap_init_irq(u32 base, int nr_irqs)
+static void __init omap_init_irq(u32 base, int nr_irqs,
+				 struct device_node *node)
 {
 	void __iomem *omap_irq_base;
 	unsigned long nr_of_irqs = 0;
 	unsigned int nr_banks = 0;
-	int i, j;
+	int i, j, irq_base;
 
 	omap_irq_base = ioremap(base, SZ_4K);
 	if (WARN_ON(!omap_irq_base))
 		return;
 
+	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+	if (irq_base < 0) {
+		pr_warn("Couldn't allocate IRQ numbers\n");
+		irq_base = 0;
+	}
+
+	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
+				       &irq_domain_simple_ops, NULL);
+
 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 		struct omap_irq_bank *bank = irq_banks + i;
 
@@ -166,36 +182,36 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 		/* Static mapping, never released */
 		bank->base_reg = ioremap(base, SZ_4K);
 		if (!bank->base_reg) {
-			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+			pr_err("Could not ioremap irq bank%i\n", i);
 			continue;
 		}
 
 		omap_irq_bank_init_one(bank);
 
 		for (j = 0; j < bank->nr_irqs; j += 32)
-			omap_alloc_gc(bank->base_reg + j, j, 32);
+			omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
 
 		nr_of_irqs += bank->nr_irqs;
 		nr_banks++;
 	}
 
-	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+	pr_info("Total of %ld interrupts on %d active controller%s\n",
+		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 }
 
 void __init omap2_init_irq(void)
 {
-	omap_init_irq(OMAP24XX_IC_BASE, 96);
+	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
 }
 
 void __init omap3_init_irq(void)
 {
-	omap_init_irq(OMAP34XX_IC_BASE, 96);
+	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
 }
 
 void __init ti81xx_init_irq(void)
 {
-	omap_init_irq(OMAP34XX_IC_BASE, 128);
+	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
 }
 
 static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
@@ -225,8 +241,10 @@ out:
 		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
 		irqnr &= ACTIVEIRQ_MASK;
 
-		if (irqnr)
+		if (irqnr) {
+			irqnr = irq_find_mapping(domain, irqnr);
 			handle_IRQ(irqnr, regs);
+		}
 	} while (irqnr);
 }
 
@@ -236,6 +254,27 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
 	omap_intc_handle_irq(base_addr, regs);
 }
 
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+	u32 nr_irqs = 96;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	if (of_address_to_resource(node, 0, &res)) {
+		WARN(1, "unable to get intc registers\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
+		pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
+
+	omap_init_irq(res.start, nr_irqs, of_node_get(node));
+
+	return 0;
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
-- 
1.7.0.4

[PATCH v3 3/4] arm/dts: OMAP3: Add interrupt-controller bindings for INTC

[Benoit Cousson]

Update the DTS with the proper information required by the
INTC bindings.

- Add the number of interrupt lines
- Add the reg and the compatible entries.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
---
 arch/arm/boot/dts/omap3.dtsi |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 216c331..34cce6d 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,10 +61,12 @@
 		ranges;
 		ti,hwmods = "l3_main";
 
-		intc: interrupt-controller@1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller@48200000 {
+			compatible = "ti,omap2-intc";
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			ti,intc-size = <96>;
+			reg = <0x48200000 0x1000>;
 		};
 
 		uart1: serial@0x4806a000 {
-- 
1.7.0.4

[PATCH v3 4/4] ARM: OMAP2+: board-generic: Use of_irq_init API

[Benoit Cousson]

Use the of_irq_init API introduced in 3.2 to handle
interrupt-controller with DT.
Update the irq_match table to map the proper XXX_of_init
functions for INTC and GIC drivers.

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
---
 arch/arm/mach-omap2/board-generic.c |   30 ++++++++++++++++--------------
 1 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 02d7e82..cf08921 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/io.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>
@@ -24,6 +25,17 @@
 #include "common.h"
 #include "common-board-devices.h"
 
+static struct of_device_id irq_match[] __initdata = {
+	{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ }
+};
+
+static void __init omap_init_irq(void)
+{
+	of_irq_init(irq_match);
+}
+
 /*
  * XXX: Still needed to boot until the i2c & twl driver is adapted to
  * device-tree
@@ -58,18 +70,8 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
 	{ }
 };
 
-static struct of_device_id intc_match[] __initdata = {
-	{ .compatible = "ti,omap3-intc", },
-	{ .compatible = "arm,cortex-a9-gic", },
-	{ }
-};
-
 static void __init omap_generic_init(void)
 {
-	struct device_node *node = of_find_matching_node(NULL, intc_match);
-	if (node)
-		irq_domain_add_legacy(node, 32, 0, 0, &irq_domain_simple_ops, NULL);
-
 	omap_sdrc_init(NULL, NULL);
 
 	of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
@@ -101,7 +103,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
-	.init_irq	= omap2_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,
@@ -120,7 +122,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap243x_map_io,
 	.init_early	= omap2430_init_early,
-	.init_irq	= omap2_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,
@@ -139,7 +141,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
-	.init_irq	= omap3_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_init,
 	.timer		= &omap3_timer,
@@ -158,7 +160,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap4_map_io,
 	.init_early	= omap4430_init_early,
-	.init_irq	= gic_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap4_init,
 	.timer		= &omap4_timer,
-- 
1.7.0.4

Re: [PATCH v3 2/4] ARM: OMAP2/3: intc: Add DT support for TI interrupt controller

[Rob Herring]

On 02/14/2012 11:56 AM, Benoit Cousson wrote:
> Add a function to initialize the OMAP2/3 interrupt controller (INTC)
> using a device tree node.
> 
> This version take advantage of the new irq_domain_add_legacy API.
> 
> Replace some printk() with the proper pr_ macro.
> 
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>

Given that you plan to do gen irqchip:

Acked-by: Rob Herring <rob.herring@calxeda.com>

Rob

> ---
>  .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++
>  arch/arm/mach-omap2/common.h                       |   10 +++
>  arch/arm/mach-omap2/irq.c                          |   59 ++++++++++++++++---
>  3 files changed, 86 insertions(+), 10 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/omap/intc.txt b/Documentation/devicetree/bindings/arm/omap/intc.txt
> new file mode 100644
> index 0000000..f2583e6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/omap/intc.txt
> @@ -0,0 +1,27 @@
> +* OMAP Interrupt Controller
> +
> +OMAP2/3 are using a TI interrupt controller that can support several
> +configurable number of interrupts.
> +
> +Main node required properties:
> +
> +- compatible : should be:
> +	"ti,omap2-intc"
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> +  interrupt source. The type shall be a <u32> and the value shall be 1.
> +
> +  The cell contains the interrupt number in the range [0-128].
> +- ti,intc-size: Number of interrupts handled by the interrupt controller.
> +- reg: physical base address and size of the intc registers map.
> +
> +Example:
> +
> +	intc: interrupt-controller@1 {
> +		compatible = "ti,omap2-intc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		ti,intc-size = <96>;
> +		reg = <0x48200000 0x1000>;
> +	};
> +
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index febffde..a87ce52 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -174,6 +174,16 @@ void omap3_intc_handle_irq(struct pt_regs *regs);
>  extern void __iomem *omap4_get_l2cache_base(void);
>  #endif
>  
> +struct device_node;
> +#ifdef CONFIG_OF
> +int __init intc_of_init(struct device_node *node, struct device_node *parent);
> +#else
> +int __init intc_of_init(struct device_node *node, struct device_node *parent)
> +{
> +	return 0;
> +}
> +#endif
> +
>  #ifdef CONFIG_SMP
>  extern void __iomem *omap4_get_scu_base(void);
>  #else
> diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
> index 1fef061..e2d0f33 100644
> --- a/arch/arm/mach-omap2/irq.c
> +++ b/arch/arm/mach-omap2/irq.c
> @@ -11,12 +11,16 @@
>   * for more details.
>   */
>  #include <linux/kernel.h>
> +#include <linux/module.h>
>  #include <linux/init.h>
>  #include <linux/interrupt.h>
>  #include <linux/io.h>
>  #include <mach/hardware.h>
>  #include <asm/exception.h>
>  #include <asm/mach/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
>  
>  
>  /* selected INTC register offsets */
> @@ -57,6 +61,8 @@ static struct omap_irq_bank {
>  	},
>  };
>  
> +static struct irq_domain *domain;
> +
>  /* Structure to save interrupt controller context */
>  struct omap3_intc_regs {
>  	u32 sysconfig;
> @@ -147,17 +153,27 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
>  				IRQ_NOREQUEST | IRQ_NOPROBE, 0);
>  }
>  
> -static void __init omap_init_irq(u32 base, int nr_irqs)
> +static void __init omap_init_irq(u32 base, int nr_irqs,
> +				 struct device_node *node)
>  {
>  	void __iomem *omap_irq_base;
>  	unsigned long nr_of_irqs = 0;
>  	unsigned int nr_banks = 0;
> -	int i, j;
> +	int i, j, irq_base;
>  
>  	omap_irq_base = ioremap(base, SZ_4K);
>  	if (WARN_ON(!omap_irq_base))
>  		return;
>  
> +	irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
> +	if (irq_base < 0) {
> +		pr_warn("Couldn't allocate IRQ numbers\n");
> +		irq_base = 0;
> +	}
> +
> +	domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
> +				       &irq_domain_simple_ops, NULL);
> +
>  	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
>  		struct omap_irq_bank *bank = irq_banks + i;
>  
> @@ -166,36 +182,36 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
>  		/* Static mapping, never released */
>  		bank->base_reg = ioremap(base, SZ_4K);
>  		if (!bank->base_reg) {
> -			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
> +			pr_err("Could not ioremap irq bank%i\n", i);
>  			continue;
>  		}
>  
>  		omap_irq_bank_init_one(bank);
>  
>  		for (j = 0; j < bank->nr_irqs; j += 32)
> -			omap_alloc_gc(bank->base_reg + j, j, 32);
> +			omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
>  
>  		nr_of_irqs += bank->nr_irqs;
>  		nr_banks++;
>  	}
>  
> -	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
> -	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
> +	pr_info("Total of %ld interrupts on %d active controller%s\n",
> +		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
>  }
>  
>  void __init omap2_init_irq(void)
>  {
> -	omap_init_irq(OMAP24XX_IC_BASE, 96);
> +	omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
>  }
>  
>  void __init omap3_init_irq(void)
>  {
> -	omap_init_irq(OMAP34XX_IC_BASE, 96);
> +	omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
>  }
>  
>  void __init ti81xx_init_irq(void)
>  {
> -	omap_init_irq(OMAP34XX_IC_BASE, 128);
> +	omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
>  }
>  
>  static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
> @@ -225,8 +241,10 @@ out:
>  		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
>  		irqnr &= ACTIVEIRQ_MASK;
>  
> -		if (irqnr)
> +		if (irqnr) {
> +			irqnr = irq_find_mapping(domain, irqnr);
>  			handle_IRQ(irqnr, regs);
> +		}
>  	} while (irqnr);
>  }
>  
> @@ -236,6 +254,27 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
>  	omap_intc_handle_irq(base_addr, regs);
>  }
>  
> +int __init intc_of_init(struct device_node *node, struct device_node *parent)
> +{
> +	struct resource res;
> +	u32 nr_irqs = 96;
> +
> +	if (WARN_ON(!node))
> +		return -ENODEV;
> +
> +	if (of_address_to_resource(node, 0, &res)) {
> +		WARN(1, "unable to get intc registers\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
> +		pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
> +
> +	omap_init_irq(res.start, nr_irqs, of_node_get(node));
> +
> +	return 0;
> +}
> +
>  #ifdef CONFIG_ARCH_OMAP3
>  static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
>  

Re: [PATCH v3 2/4] ARM: OMAP2/3: intc: Add DT support for TI interrupt controller

[Grant Likely]

On Tue, Feb 14, 2012 at 06:56:10PM +0100, Benoit Cousson wrote:
> Add a function to initialize the OMAP2/3 interrupt controller (INTC)
> using a device tree node.
> 
> This version take advantage of the new irq_domain_add_legacy API.
> 
> Replace some printk() with the proper pr_ macro.
> 
> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Rob Herring <rob.herring@calxeda.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> ---
>  .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++
>  arch/arm/mach-omap2/common.h                       |   10 +++
>  arch/arm/mach-omap2/irq.c                          |   59 ++++++++++++++++---
>  3 files changed, 86 insertions(+), 10 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/omap/intc.txt b/Documentation/devicetree/bindings/arm/omap/intc.txt
> new file mode 100644
> index 0000000..f2583e6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/omap/intc.txt
> @@ -0,0 +1,27 @@
> +* OMAP Interrupt Controller
> +
> +OMAP2/3 are using a TI interrupt controller that can support several
> +configurable number of interrupts.
> +
> +Main node required properties:
> +
> +- compatible : should be:
> +	"ti,omap2-intc"
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> +  interrupt source. The type shall be a <u32> and the value shall be 1.
> +
> +  The cell contains the interrupt number in the range [0-128].
> +- ti,intc-size: Number of interrupts handled by the interrupt controller.
> +- reg: physical base address and size of the intc registers map.
> +
> +Example:
> +
> +	intc: interrupt-controller@1 {
> +		compatible = "ti,omap2-intc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		ti,intc-size = <96>;
> +		reg = <0x48200000 0x1000>;
> +	};
> +
> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
> index febffde..a87ce52 100644
> --- a/arch/arm/mach-omap2/common.h
> +++ b/arch/arm/mach-omap2/common.h
> @@ -174,6 +174,16 @@ void omap3_intc_handle_irq(struct pt_regs *regs);
>  extern void __iomem *omap4_get_l2cache_base(void);
>  #endif
>  
> +struct device_node;
> +#ifdef CONFIG_OF
> +int __init intc_of_init(struct device_node *node, struct device_node *parent);

This name is pretty generic for a global symbol.  How about omap2_intc_of_init?

Otherwise this series looks good.

Acked-by: Grant Likely <grant.likely@secretlab.ca>

This series need to be committed on top of the irqdomain tree.  I can either
pick it up myself (with Tony's ack) or I can stabilize the irqdomain/next tree
so that you can use it as a stable base to commit against (which I should
probably do anyway since there are others who will depend on it).

g.

Re: [PATCH v3 2/4] ARM: OMAP2/3: intc: Add DT support for TI interrupt controller

[Cousson, Benoit]

On 2/14/2012 8:48 PM, Rob Herring wrote:
> On 02/14/2012 11:56 AM, Benoit Cousson wrote:
>> Add a function to initialize the OMAP2/3 interrupt controller (INTC)
>> using a device tree node.
>>
>> This version take advantage of the new irq_domain_add_legacy API.
>>
>> Replace some printk() with the proper pr_ macro.
>>
>> Signed-off-by: Benoit Cousson<b-cousson@ti.com>
>> Cc: Tony Lindgren<tony@atomide.com>
>> Cc: Rob Herring<rob.herring@calxeda.com>
>> Cc: Grant Likely<grant.likely@secretlab.ca>
>
> Given that you plan to do gen irqchip:

Yes, I will. I even already have to patch, but I'm just trying to 
minimize the dependency since I'd like that to be merged for 3.4.
That series already missed 3.3.

> Acked-by: Rob Herring<rob.herring@calxeda.com>

Thanks,
Benoit

Re: [PATCH v3 2/4] ARM: OMAP2/3: intc: Add DT support for TI interrupt controller

[Cousson, Benoit]

On 2/14/2012 9:52 PM, Grant Likely wrote:
> On Tue, Feb 14, 2012 at 06:56:10PM +0100, Benoit Cousson wrote:
>> Add a function to initialize the OMAP2/3 interrupt controller (INTC)
>> using a device tree node.
>>
>> This version take advantage of the new irq_domain_add_legacy API.
>>
>> Replace some printk() with the proper pr_ macro.
>>
>> Signed-off-by: Benoit Cousson<b-cousson-l0cyMroinI0@public.gmane.org>
>> Cc: Tony Lindgren<tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
>> Cc: Rob Herring<rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
>> Cc: Grant Likely<grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>
>> ---
>>   .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++
>>   arch/arm/mach-omap2/common.h                       |   10 +++
>>   arch/arm/mach-omap2/irq.c                          |   59 ++++++++++++++++---
>>   3 files changed, 86 insertions(+), 10 deletions(-)
>>   create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/omap/intc.txt b/Documentation/devicetree/bindings/arm/omap/intc.txt
>> new file mode 100644
>> index 0000000..f2583e6
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/omap/intc.txt
>> @@ -0,0 +1,27 @@
>> +* OMAP Interrupt Controller
>> +
>> +OMAP2/3 are using a TI interrupt controller that can support several
>> +configurable number of interrupts.
>> +
>> +Main node required properties:
>> +
>> +- compatible : should be:
>> +	"ti,omap2-intc"
>> +- interrupt-controller : Identifies the node as an interrupt controller
>> +- #interrupt-cells : Specifies the number of cells needed to encode an
>> +  interrupt source. The type shall be a<u32>  and the value shall be 1.
>> +
>> +  The cell contains the interrupt number in the range [0-128].
>> +- ti,intc-size: Number of interrupts handled by the interrupt controller.
>> +- reg: physical base address and size of the intc registers map.
>> +
>> +Example:
>> +
>> +	intc: interrupt-controller@1 {
>> +		compatible = "ti,omap2-intc";
>> +		interrupt-controller;
>> +		#interrupt-cells =<1>;
>> +		ti,intc-size =<96>;
>> +		reg =<0x48200000 0x1000>;
>> +	};
>> +
>> diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
>> index febffde..a87ce52 100644
>> --- a/arch/arm/mach-omap2/common.h
>> +++ b/arch/arm/mach-omap2/common.h
>> @@ -174,6 +174,16 @@ void omap3_intc_handle_irq(struct pt_regs *regs);
>>   extern void __iomem *omap4_get_l2cache_base(void);
>>   #endif
>>
>> +struct device_node;
>> +#ifdef CONFIG_OF
>> +int __init intc_of_init(struct device_node *node, struct device_node *parent);
>
> This name is pretty generic for a global symbol.  How about omap2_intc_of_init?

That's a good point, I was trying mimic the gic name without thinking in 
my case it is not a generic IP :-(.

I'll rename that omap2_intc_of_init and update the branch for the pull 
request.

> Otherwise this series looks good.
>
> Acked-by: Grant Likely<grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>

> This series need to be committed on top of the irqdomain tree.  I can either
> pick it up myself (with Tony's ack) or I can stabilize the irqdomain/next tree
> so that you can use it as a stable base to commit against (which I should
> probably do anyway since there are others who will depend on it).

This series is the base for all the other OMAP DT series, so I'd rather 
keep it in Tony's tree that contains as well some OMAP fixes not yet in 
mainline.

I guess ideally the irqdomain/next should be stabilized and maybe pulled 
in arm-soc. I'm not sure how Arnd / Olof are handling this kind of 
dependency.

Thanks,
Benoit