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From: David Daney <david.s.daney-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: "linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org"
	<linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>,
	David Daney <david.daney-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>,
	"devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org"
	<devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org>,
	"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org"
	<ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>,
	Rob Herring <rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
Subject: Re: [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts.
Date: Sat, 03 Mar 2012 21:09:32 -0800	[thread overview]
Message-ID: <4F52F90C.5060306@gmail.com> (raw)
In-Reply-To: <4F527285.1020500-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

On 03/03/2012 11:35 AM, Rob Herring wrote:
> On 03/02/2012 01:29 PM, David Daney wrote:
>> On 03/02/2012 11:07 AM, Grant Likely wrote:
>>> +static void __init octeon_irq_set_ciu_mapping(unsigned int irq,
>>> +                          unsigned int line,
>>> +                          unsigned int bit,
>>> +                          struct irq_domain *domain,
>>>                               struct irq_chip *chip,
>>>                               irq_flow_handler_t handler)
>>>     {
>>> +    struct irq_data *irqd;
>>>         union octeon_ciu_chip_data cd;
>>>
>>>         irq_set_chip_and_handler(irq, chip, handler);
>>> -
>>>         cd.l = 0;
>>>         cd.s.line = line;
>>>         cd.s.bit = bit;
>>>
>>>         irq_set_chip_data(irq, cd.p);
>>>         octeon_irq_ciu_to_irq[line][bit] = irq;
>>> +
>>> +    irqd = irq_get_irq_data(irq);
>>> +    irqd->hwirq = line<<    6 | bit;
>>> +    irqd->domain = domain;
>>>>> I think the domain code will set these.
>>>> It is my understanding that the domain code only does this for:
>>>>
>>>> o irq_domain_add_legacy()
>>>>
>>>> o irq_create_direct_mapping()
>>>>
>>>> o irq_create_mapping()
>>>>
>>>> We use none of those.  So I do it here.
>>>>
>>>> If there is a better way, I am open to suggestions.
>>> irq_create_mapping is called by irq_create_of_mapping() which is
>>> in turn called by irq_of_parse_and-map().  irq_domain always
>>> manages the hwirq and domain values.  Driver code cannot manipulate
>>> them manually.
>>>
>> I really must be missing something.
>>
>> Given:
>>
>> 1) I must have a mapping between hwirq and irq that I control so that
>> non-OF code using the OCTEON_IRQ_* constants continues to work.
> Those defines are what you need to work to get rid of.

We are not starting from a blank slate here.  There is a lot of in-tree 
code using these symbols.  We cannot make them disappear with wishful 
thinking.

The first step is a switch to irq_domains using the existing mappings.

After we do that, I have patches to transition some drivers to use the 
OF mapping via irq_domains.  After those are merged, we can work toward 
getting rid of OCTEON_IRQ_*.  But I think it must be the last step in 
the process, not the first.
>
>> 2) irq_create_mapping() will allocate a random irq value if none is
>> already assigned to the hwirq.
>>
>> Therefore: To avoid having random irq values assigned, I must manually
>> assign them.
>>
> So you should be using legacy domain if you need to maintain fixed hwirq
> to linux irq numbers. "linear" is a bit confusing as it doesn't mean
> linear 1:1 irq number assignment, but linear search.

My reading of Grant's code in linux-next directly contradicts this 
statement.  There is no code in irqdomain.c, that I can see, that allows 
me to have an arbitrary mapping of irq <--> hwirq values.


>
> Ultimately, for DT boot you should use of_irq_init to scan the dts, and
> then create a linear domain for each interrupt controller node. You may
> need to decide on linear vs. legacy at runtime based on having a DT node
> pointer or not.

Perhaps, but we need to take the first step before gradually arriving at 
some Ultimate Solution.

We will also need to handle irq controllers with 2^20 sparsely populated 
hwirq values, so linear domains will probably be out of the question there.

David Daney

  parent reply	other threads:[~2012-03-04  5:09 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-01  0:56 [PATCH v6 0/5] MIPS: Octeon: Use Device Tree David Daney
2012-03-01  0:56 ` [PATCH v6 1/5] MIPS: Octeon: Add device tree source files David Daney
     [not found] ` <1330563422-14078-1-git-send-email-ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-03-01  0:56   ` [PATCH v6 2/5] MIPS: Don't define early_init_devtree() and device_tree_init() in prom.c for CPU_CAVIUM_OCTEON David Daney
2012-03-01  0:57 ` [PATCH v6 3/5] MIPS: Octeon: Add irq handlers for GPIO interrupts David Daney
2012-03-01  0:57 ` [PATCH v6 4/5] MIPS: Octeon: Setup irq_domains for interrupts David Daney
2012-03-02 14:22   ` Rob Herring
2012-03-02 18:03     ` David Daney
2012-03-02 19:07       ` Grant Likely
2012-03-02 19:29         ` David Daney
     [not found]           ` <4F511FB0.5070901-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
2012-03-03 19:35             ` Rob Herring
     [not found]               ` <4F527285.1020500-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-03-04  5:09                 ` David Daney [this message]
2012-03-09  5:57                   ` Grant Likely
2012-03-09 18:45                     ` David Daney
2012-03-09 21:07                       ` Rob Herring
2012-03-10  0:08                         ` David Daney
     [not found]                           ` <4F5A9B75.8090301-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2012-03-10 16:20                             ` Rob Herring
2012-03-03 19:38       ` Rob Herring
2012-03-04  5:41         ` David Daney
2012-03-02 19:02   ` Grant Likely
2012-03-01  0:57 ` [PATCH v6 5/5] MIPS: Octeon: Initialize and fixup device tree David Daney

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