From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver Date: Thu, 03 May 2012 11:59:33 -0600 Message-ID: <4FA2C785.2080703@wwwdotorg.org> References: <1336061147-10245-1-git-send-email-hdoyu@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1336061147-10245-1-git-send-email-hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Hiroshi DOYU Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Felipe Balbi , Arnd Bergmann , Colin Cross , Olof Johansson , Russell King , Grant Likely , Rob Herring , Greg Kroah-Hartman , Ohad Ben-Cohen , Linus Walleij , "John W. Linville" , MyungJoo Ham , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org List-Id: devicetree@vger.kernel.org On 05/03/2012 10:05 AM, Hiroshi DOYU wrote: > Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced > High-performance Bus (AHB) architecture. > > The AHB Arbiter controls AHB bus master arbitration. This effectively > forms a second level of arbitration for access to the memory > controller through the AHB Slave Memory device. The AHB pre-fetch > logic can be configured to enhance performance for devices doing > sequential access. Each AHB master is assigned to either the high or > low priority bin. Both Tegra20/30 have this AHB bus. > > Some of configuration param could be passed from DT too. This patch should add Documentation/devicetree/bindings/arm/tegra/tegra20-ahb.txt to describe the DT binding.