[PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Hiroshi DOYU]

Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
High-performance Bus (AHB) architecture.

The AHB Arbiter controls AHB bus master arbitration. This effectively
forms a second level of arbitration for access to the memory
controller through the AHB Slave Memory device. The AHB pre-fetch
logic can be configured to enhance performance for devices doing
sequential access. Each AHB master is assigned to either the high or
low priority bin. Both Tegra20/30 have this AHB bus.

Some of configuration param could be passed from DT too.

Signed-off-by: Hiroshi DOYU <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Felipe Balbi <balbi-l0cyMroinI0@public.gmane.org>
Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
 arch/arm/mach-tegra/Kconfig |    8 ++
 drivers/Makefile            |    2 +-
 drivers/amba/Makefile       |    4 +-
 drivers/amba/tegra-ahb.c    |  272 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 283 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 204d3d4..6a113a9 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -50,6 +50,14 @@ config TEGRA_PCI
 	depends on ARCH_TEGRA_2x_SOC
 	select PCI
 
+config TEGRA_AHB
+	bool "Enable AHB driver for NVIDIA Tegra SoCs"
+	default y
+	help
+	  Adds AHB configuration functionality for NVIDIA Tegra SoCs,
+	  which controls AHB bus master arbitration and some
+	  perfomance parameters(priority, prefech size).
+
 comment "Tegra board type"
 
 config MACH_HARMONY
diff --git a/drivers/Makefile b/drivers/Makefile
index 5870322..d97e2e2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_SFI)		+= sfi/
 # PnP must come after ACPI since it will eventually need to check if acpi
 # was used and do nothing if so
 obj-$(CONFIG_PNP)		+= pnp/
-obj-$(CONFIG_ARM_AMBA)		+= amba/
+obj-$(CONFIG_ARM)		+= amba/
 # Many drivers will want to use DMA so this has to be made available
 # really early.
 obj-$(CONFIG_DMA_ENGINE)	+= dma/
diff --git a/drivers/amba/Makefile b/drivers/amba/Makefile
index 40fe740..66e81c2 100644
--- a/drivers/amba/Makefile
+++ b/drivers/amba/Makefile
@@ -1,2 +1,2 @@
-obj-y		+= bus.o
-
+obj-$(CONFIG_ARM_AMBA)		+= bus.o
+obj-$(CONFIG_TEGRA_AHB)		+= tegra-ahb.o
diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c
new file mode 100644
index 0000000..03933f3
--- /dev/null
+++ b/drivers/amba/tegra-ahb.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2011 Google, Inc.
+ *
+ * Author:
+ *	Jay Cheng <jacheng-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+ *	James Wylder <james.wylder-3WKxDLwmzFNWk0Htik3J/w@public.gmane.org>
+ *	Benoit Goby <benoit-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
+ *	Colin Cross <ccross-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org>
+ *	Hiroshi DOYU <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define DRV_NAME "tegra-ahb"
+
+#define AHB_ARBITRATION_DISABLE		0x00
+#define AHB_ARBITRATION_PRIORITY_CTRL	0x04
+#define   AHB_PRIORITY_WEIGHT(x)	(((x) & 0x7) << 29)
+#define   PRIORITY_SELECT_USB BIT(6)
+#define   PRIORITY_SELECT_USB2 BIT(18)
+#define   PRIORITY_SELECT_USB3 BIT(17)
+
+#define AHB_GIZMO_AHB_MEM		0x0c
+#define   ENB_FAST_REARBITRATE BIT(2)
+#define   DONT_SPLIT_AHB_WR     BIT(7)
+
+#define AHB_GIZMO_APB_DMA		0x10
+#define AHB_GIZMO_IDE			0x18
+#define AHB_GIZMO_USB			0x1c
+#define AHB_GIZMO_AHB_XBAR_BRIDGE	0x20
+#define AHB_GIZMO_CPU_AHB_BRIDGE	0x24
+#define AHB_GIZMO_COP_AHB_BRIDGE	0x28
+#define AHB_GIZMO_XBAR_APB_CTLR		0x2c
+#define AHB_GIZMO_VCP_AHB_BRIDGE	0x30
+#define AHB_GIZMO_NAND			0x3c
+#define AHB_GIZMO_SDMMC4		0x44
+#define AHB_GIZMO_XIO			0x48
+#define AHB_GIZMO_BSEV			0x60
+#define AHB_GIZMO_BSEA			0x70
+#define AHB_GIZMO_NOR			0x74
+#define AHB_GIZMO_USB2			0x78
+#define AHB_GIZMO_USB3			0x7c
+#define   IMMEDIATE	BIT(18)
+
+#define AHB_GIZMO_SDMMC1		0x80
+#define AHB_GIZMO_SDMMC2		0x84
+#define AHB_GIZMO_SDMMC3		0x88
+#define AHB_MEM_PREFETCH_CFG_X		0xd8
+#define AHB_ARBITRATION_XBAR_CTRL	0xdc
+#define AHB_MEM_PREFETCH_CFG3		0xe0
+#define AHB_MEM_PREFETCH_CFG4		0xe4
+#define AHB_MEM_PREFETCH_CFG1		0xec
+#define AHB_MEM_PREFETCH_CFG2		0xf0
+#define   PREFETCH_ENB	BIT(31)
+#define   MST_ID(x)	(((x) & 0x1f) << 26)
+#define   AHBDMA_MST_ID	MST_ID(5)
+#define   USB_MST_ID	MST_ID(6)
+#define   USB2_MST_ID	MST_ID(18)
+#define   USB3_MST_ID	MST_ID(17)
+#define   ADDR_BNDRY(x)	(((x) & 0xf) << 21)
+#define   INACTIVITY_TIMEOUT(x)	(((x) & 0xffff) << 0)
+
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID	0xf8
+
+static u32 tegra_ahb_gizmo[] = {
+	AHB_ARBITRATION_DISABLE,
+	AHB_ARBITRATION_PRIORITY_CTRL,
+	AHB_GIZMO_AHB_MEM,
+	AHB_GIZMO_APB_DMA,
+	AHB_GIZMO_IDE,
+	AHB_GIZMO_USB,
+	AHB_GIZMO_AHB_XBAR_BRIDGE,
+	AHB_GIZMO_CPU_AHB_BRIDGE,
+	AHB_GIZMO_COP_AHB_BRIDGE,
+	AHB_GIZMO_XBAR_APB_CTLR,
+	AHB_GIZMO_VCP_AHB_BRIDGE,
+	AHB_GIZMO_NAND,
+	AHB_GIZMO_SDMMC4,
+	AHB_GIZMO_XIO,
+	AHB_GIZMO_BSEV,
+	AHB_GIZMO_BSEA,
+	AHB_GIZMO_NOR,
+	AHB_GIZMO_USB2,
+	AHB_GIZMO_USB3,
+	AHB_GIZMO_SDMMC1,
+	AHB_GIZMO_SDMMC2,
+	AHB_GIZMO_SDMMC3,
+	AHB_MEM_PREFETCH_CFG_X,
+	AHB_ARBITRATION_XBAR_CTRL,
+	AHB_MEM_PREFETCH_CFG3,
+	AHB_MEM_PREFETCH_CFG4,
+	AHB_MEM_PREFETCH_CFG1,
+	AHB_MEM_PREFETCH_CFG2,
+	AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
+};
+
+struct tegra_ahb {
+	void __iomem	*regs;
+	struct device	*dev;
+	u32		ctx[0];
+};
+
+static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
+{
+	return readl(ahb->regs + offset);
+}
+
+static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
+{
+	writel(value, ahb->regs + offset);
+}
+
+static int tegra_ahb_suspend(struct device *dev)
+{
+	int i;
+	struct tegra_ahb *ahb = dev_get_drvdata(dev);
+
+	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
+		ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
+	return 0;
+}
+
+static int tegra_ahb_resume(struct device *dev)
+{
+	int i;
+	struct tegra_ahb *ahb = dev_get_drvdata(dev);
+
+	for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
+		gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
+	return 0;
+}
+
+static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
+			    tegra_ahb_suspend,
+			    tegra_ahb_resume, NULL);
+
+static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
+{
+	u32 val;
+
+	val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
+	val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
+	gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
+
+	val = gizmo_readl(ahb, AHB_GIZMO_USB);
+	val |= IMMEDIATE;
+	gizmo_writel(ahb, val, AHB_GIZMO_USB);
+
+	val = gizmo_readl(ahb, AHB_GIZMO_USB2);
+	val |= IMMEDIATE;
+	gizmo_writel(ahb, val, AHB_GIZMO_USB2);
+
+	val = gizmo_readl(ahb, AHB_GIZMO_USB3);
+	val |= IMMEDIATE;
+	gizmo_writel(ahb, val, AHB_GIZMO_USB3);
+
+	val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
+	val |= PRIORITY_SELECT_USB |
+		PRIORITY_SELECT_USB2 |
+		PRIORITY_SELECT_USB3 |
+		AHB_PRIORITY_WEIGHT(7);
+	gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
+
+	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
+	val &= ~MST_ID(~0);
+	val |= PREFETCH_ENB |
+		AHBDMA_MST_ID |
+		ADDR_BNDRY(0xc) |
+		INACTIVITY_TIMEOUT(0x1000);
+	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
+
+	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
+	val &= ~MST_ID(~0);
+	val |= PREFETCH_ENB |
+		USB_MST_ID |
+		ADDR_BNDRY(0xc) |
+		INACTIVITY_TIMEOUT(0x1000);
+	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
+
+	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
+	val &= ~MST_ID(~0);
+	val |= PREFETCH_ENB |
+		USB3_MST_ID |
+		ADDR_BNDRY(0xc) |
+		INACTIVITY_TIMEOUT(0x1000);
+	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
+
+	val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
+	val &= ~MST_ID(~0);
+	val |= PREFETCH_ENB |
+		USB2_MST_ID |
+		ADDR_BNDRY(0xc) |
+		INACTIVITY_TIMEOUT(0x1000);
+	gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
+}
+
+static int __devinit tegra_ahb_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct tegra_ahb *ahb;
+	size_t bytes;
+
+	bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
+	ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
+	if (!ahb)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+	ahb->regs = devm_request_and_ioremap(&pdev->dev, res);
+	if (!ahb->regs)
+		return -EBUSY;
+
+	ahb->dev = &pdev->dev;
+	platform_set_drvdata(pdev, ahb);
+	tegra_ahb_gizmo_init(ahb);
+	return 0;
+}
+
+static int __devexit tegra_ahb_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static const struct of_device_id tegra_ahb_of_match[] __devinitconst = {
+	{ .compatible = "nvidia,tegra30-ahb", },
+	{ .compatible = "nvidia,tegra20-ahb", },
+	{},
+};
+
+static struct platform_driver tegra_ahb_driver = {
+	.probe = tegra_ahb_probe,
+	.remove = __devexit_p(tegra_ahb_remove),
+	.driver = {
+		.name = DRV_NAME,
+		.owner = THIS_MODULE,
+		.of_match_table = tegra_ahb_of_match,
+		.pm = &tegra_ahb_pm,
+	},
+};
+
+static int __init tegra_ahb_module_init(void)
+{
+	return platform_driver_register(&tegra_ahb_driver);
+}
+postcore_initcall(tegra_ahb_module_init);
+
+static void __exit tegra_ahb_module_exit(void)
+{
+	platform_driver_unregister(&tegra_ahb_driver);
+}
+module_exit(tegra_ahb_module_exit);
+
+MODULE_AUTHOR("Hiroshi DOYU <hdoyu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Tegra AHB driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRV_NAME);
-- 
1.7.5.4

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Stephen Warren]

On 05/03/2012 10:05 AM, Hiroshi DOYU wrote:
> Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
> High-performance Bus (AHB) architecture.
> 
> The AHB Arbiter controls AHB bus master arbitration. This effectively
> forms a second level of arbitration for access to the memory
> controller through the AHB Slave Memory device. The AHB pre-fetch
> logic can be configured to enhance performance for devices doing
> sequential access. Each AHB master is assigned to either the high or
> low priority bin. Both Tegra20/30 have this AHB bus.
> 
> Some of configuration param could be passed from DT too.

> diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c
> +static u32 tegra_ahb_gizmo[] = {

const?

> +static int __init tegra_ahb_module_init(void)
> +{
> +	return platform_driver_register(&tegra_ahb_driver);
> +}
> +postcore_initcall(tegra_ahb_module_init);

Can this be a module_init() instead of postcore_initcall()?

> +
> +static void __exit tegra_ahb_module_exit(void)
> +{
> +	platform_driver_unregister(&tegra_ahb_driver);
> +}
> +module_exit(tegra_ahb_module_exit);

If so, all of the previous two quoted chunks can be replaced with just:

module_platform_driver(tegra_ahb_module_init);

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Hiroshi Doyu]

From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Subject: Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver
Date: Thu, 3 May 2012 19:41:35 +0200
Message-ID: <4FA2C34F.5060406-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>

> On 05/03/2012 10:05 AM, Hiroshi DOYU wrote:
> > Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
> > High-performance Bus (AHB) architecture.
> > 
> > The AHB Arbiter controls AHB bus master arbitration. This effectively
> > forms a second level of arbitration for access to the memory
> > controller through the AHB Slave Memory device. The AHB pre-fetch
> > logic can be configured to enhance performance for devices doing
> > sequential access. Each AHB master is assigned to either the high or
> > low priority bin. Both Tegra20/30 have this AHB bus.
> > 
> > Some of configuration param could be passed from DT too.
> 
> > diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c
> > +static u32 tegra_ahb_gizmo[] = {
> 
> const?

Yes.

> > +static int __init tegra_ahb_module_init(void)
> > +{
> > +	return platform_driver_register(&tegra_ahb_driver);
> > +}
> > +postcore_initcall(tegra_ahb_module_init);
> 
> Can this be a module_init() instead of postcore_initcall()?

Since this driver configures prefetch size from AHB client devices,
it's better to make this driver available before other AHB client
drivers get ready. So "postcore_initcall()" seems to make sense if
there's no other better initcall.

> > +
> > +static void __exit tegra_ahb_module_exit(void)
> > +{
> > +	platform_driver_unregister(&tegra_ahb_driver);
> > +}
> > +module_exit(tegra_ahb_module_exit);
> 
> If so, all of the previous two quoted chunks can be replaced with just:
> 
> module_platform_driver(tegra_ahb_module_init);

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Stephen Warren]

On 05/04/2012 12:17 AM, Hiroshi Doyu wrote:
> Stephen Warren wrote at Thu, 3 May 2012 19:41:35 +0200:
>> On 05/03/2012 10:05 AM, Hiroshi DOYU wrote:
>>> Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
>>> High-performance Bus (AHB) architecture.
...
>>> +static int __init tegra_ahb_module_init(void)
>>> +{
>>> +	return platform_driver_register(&tegra_ahb_driver);
>>> +}
>>> +postcore_initcall(tegra_ahb_module_init);
>>
>> Can this be a module_init() instead of postcore_initcall()?
> 
> Since this driver configures prefetch size from AHB client devices,
> it's better to make this driver available before other AHB client
> drivers get ready. So "postcore_initcall()" seems to make sense if
> there's no other better initcall.

I believe this only affects when the driver is registered and has no
influence over when the device itself is probed.

When booting with board files rather than DT, it was possible to
register drivers and platform devices early using various initcalls to
control the order. However, with DT, I believe all the devices are
instantiated from DT at the same time (well, one by one in whatever
order as the DT is parsed), so the time when the driver is registered
isn't relevant.

So, if the other AHB devices really need this AHB driver to initialize
first, you'd better move all the AHB devices inside the AHB node in DT,
so that the AHB driver can influence when the children get probed.
Still, I'd suggest leaving that to a later patch, since everything
clearly works fine right now without this driver even existing.

>>> +
>>> +static void __exit tegra_ahb_module_exit(void)
>>> +{
>>> +	platform_driver_unregister(&tegra_ahb_driver);
>>> +}
>>> +module_exit(tegra_ahb_module_exit);
>>
>> If so, all of the previous two quoted chunks can be replaced with just:
>>
>> module_platform_driver(tegra_ahb_module_init);

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Hiroshi Doyu]

On Fri, 4 May 2012 18:48:56 +0200
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> wrote:

> On 05/04/2012 12:17 AM, Hiroshi Doyu wrote:
> > Stephen Warren wrote at Thu, 3 May 2012 19:41:35 +0200:
> >> On 05/03/2012 10:05 AM, Hiroshi DOYU wrote:
> >>> Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
> >>> High-performance Bus (AHB) architecture.
> ...
> >>> +static int __init tegra_ahb_module_init(void)
> >>> +{
> >>> +	return platform_driver_register(&tegra_ahb_driver);
> >>> +}
> >>> +postcore_initcall(tegra_ahb_module_init);
> >>
> >> Can this be a module_init() instead of postcore_initcall()?
> > 
> > Since this driver configures prefetch size from AHB client devices,
> > it's better to make this driver available before other AHB client
> > drivers get ready. So "postcore_initcall()" seems to make sense if
> > there's no other better initcall.
> 
> I believe this only affects when the driver is registered and has no
> influence over when the device itself is probed.
> 
> When booting with board files rather than DT, it was possible to
> register drivers and platform devices early using various initcalls to
> control the order. However, with DT, I believe all the devices are
> instantiated from DT at the same time (well, one by one in whatever
> order as the DT is parsed), so the time when the driver is registered
> isn't relevant.
> 
> So, if the other AHB devices really need this AHB driver to initialize
> first, you'd better move all the AHB devices inside the AHB node in DT,
> so that the AHB driver can influence when the children get probed.
> Still, I'd suggest leaving that to a later patch, since everything
> clearly works fine right now without this driver even existing.

Ok, I'll use module_platform_driver(tegra_ahb_driver). These order would be revisited.

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Stephen Warren]

On 05/03/2012 10:05 AM, Hiroshi DOYU wrote:
> Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
> High-performance Bus (AHB) architecture.
> 
> The AHB Arbiter controls AHB bus master arbitration. This effectively
> forms a second level of arbitration for access to the memory
> controller through the AHB Slave Memory device. The AHB pre-fetch
> logic can be configured to enhance performance for devices doing
> sequential access. Each AHB master is assigned to either the high or
> low priority bin. Both Tegra20/30 have this AHB bus.
> 
> Some of configuration param could be passed from DT too.

This patch should add
Documentation/devicetree/bindings/arm/tegra/tegra20-ahb.txt to describe
the DT binding.

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Hiroshi Doyu]

From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Subject: Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver
Date: Thu, 3 May 2012 19:59:33 +0200
Message-ID: <4FA2C785.2080703-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>

> On 05/03/2012 10:05 AM, Hiroshi DOYU wrote:
> > Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
> > High-performance Bus (AHB) architecture.
> > 
> > The AHB Arbiter controls AHB bus master arbitration. This effectively
> > forms a second level of arbitration for access to the memory
> > controller through the AHB Slave Memory device. The AHB pre-fetch
> > logic can be configured to enhance performance for devices doing
> > sequential access. Each AHB master is assigned to either the high or
> > low priority bin. Both Tegra20/30 have this AHB bus.
> > 
> > Some of configuration param could be passed from DT too.
> 
> This patch should add
> Documentation/devicetree/bindings/arm/tegra/tegra20-ahb.txt to describe
> the DT binding.

>From 'dts' POV, there's no difference between tegra20 and
tegra30. They just have a register range. Is
"../bindings/arm/tegra/tegra-ahb.txt" ok, instead of having both
tegra{20,30}-ahb.txt?

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Arnd Bergmann]

On Friday 04 May 2012, Hiroshi Doyu wrote:
> > This patch should add
> > Documentation/devicetree/bindings/arm/tegra/tegra20-ahb.txt to describe
> > the DT binding.
> 
> From 'dts' POV, there's no difference between tegra20 and
> tegra30. They just have a register range. Is
> "../bindings/arm/tegra/tegra-ahb.txt" ok, instead of having both
> tegra{20,30}-ahb.txt?

I think either one is ok. Just calling it tegra20-ahb.txt would be
fine too because tegra30 is compatible to that.

	Arnd

Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver

[Stephen Warren]

On 05/04/2012 12:40 AM, Hiroshi Doyu wrote:
> From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
> Subject: Re: [PATCHv3 1/4] ARM: tegra: Add Tegra AHB driver
> Date: Thu, 3 May 2012 19:59:33 +0200
> Message-ID: <4FA2C785.2080703-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
> 
>> On 05/03/2012 10:05 AM, Hiroshi DOYU wrote:
>>> Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced
>>> High-performance Bus (AHB) architecture.
>>>
>>> The AHB Arbiter controls AHB bus master arbitration. This effectively
>>> forms a second level of arbitration for access to the memory
>>> controller through the AHB Slave Memory device. The AHB pre-fetch
>>> logic can be configured to enhance performance for devices doing
>>> sequential access. Each AHB master is assigned to either the high or
>>> low priority bin. Both Tegra20/30 have this AHB bus.
>>>
>>> Some of configuration param could be passed from DT too.
>>
>> This patch should add
>> Documentation/devicetree/bindings/arm/tegra/tegra20-ahb.txt to describe
>> the DT binding.
> 
> From 'dts' POV, there's no difference between tegra20 and
> tegra30. They just have a register range. Is
> "../bindings/arm/tegra/tegra-ahb.txt" ok, instead of having both
> tegra{20,30}-ahb.txt?

Personally, I prefer to name files using the exact compatible value of
the first SoC version that introduced the HW. This allows e.g.
"tegra40-ahb.txt" to be introduced without making "tegra-ahb.txt" no
longer fully general.