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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Swapnil Jakhade <sjakhade@cadence.com>, <vkoul@kernel.org>,
	<robh+dt@kernel.org>, <p.zabel@pengutronix.de>,
	<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <a-govindraju@ti.com>
Subject: Re: [PATCH v3 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver
Date: Thu, 9 Dec 2021 13:25:29 +0530	[thread overview]
Message-ID: <4a9bdad2-9d5a-baf8-5a9c-aa0854505e5d@ti.com> (raw)
In-Reply-To: <20211022170236.18839-1-sjakhade@cadence.com>



On 22/10/21 10:32 pm, Swapnil Jakhade wrote:
> Cadence Sierra PHY is a multiprotocol PHY supporting different multilink
> PHY configurations. This patch series extends functionality of Sierra PHY
> driver by adding features like support for multilink multiprotocol
> configurations, derived reference clock etc.
> 
> The changes have been validated on TI J721E platform.
> 
> Version History:
> 
> v3:
>    - Rebased on latest PHY next
>    - Added Reviewed-by and Acked-by tags
> 
> v2:
>    - Added a new patch 3/15 to rename the SSC macros for dt-bindings
>      to use generic names. These macros are not yet used in any DTS file.
> 
> Swapnil Jakhade (15):
>   phy: cadence: Sierra: Use of_device_get_match_data() to get driver
>     data
>   phy: cadence: Sierra: Prepare driver to add support for multilink
>     configurations
>   dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic
>     names
>   dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
>   phy: cadence: Sierra: Add support to get SSC type from device tree
>   phy: cadence: Sierra: Rename some regmap variables to be in sync with
>     Sierra documentation
>   phy: cadence: Sierra: Add PHY PCS common register configurations
>   phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
>   phy: cadence: Sierra: Check PIPE mode PHY status to be ready for
>     operation
>   phy: cadence: Sierra: Update single link PCIe register configuration
>   phy: cadence: Sierra: Fix to get correct parent for mux clocks
>   phy: cadence: Sierra: Add support for PHY multilink configurations
>   phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
>   dt-bindings: phy: cadence-sierra: Add clock ID for derived reference
>     clock
>   phy: cadence: Sierra: Add support for derived reference clock output
> 
>  .../bindings/phy/phy-cadence-sierra.yaml      |    9 +
>  .../bindings/phy/phy-cadence-torrent.yaml     |    4 +-
>  drivers/phy/cadence/phy-cadence-sierra.c      | 1299 +++++++++++++++--
>  include/dt-bindings/phy/phy-cadence.h         |    9 +-
>  4 files changed, 1226 insertions(+), 95 deletions(-)


Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
> 

      parent reply	other threads:[~2021-12-09  7:55 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-22 17:02 [PATCH v3 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 01/15] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 02/15] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade
2021-11-23  4:33   ` Vinod Koul
2021-11-24  7:32     ` Swapnil Kashinath Jakhade
2021-10-22 17:02 ` [PATCH v3 03/15] dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 04/15] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 05/15] phy: cadence: Sierra: Add support to get SSC type from device tree Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 06/15] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 07/15] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 08/15] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 09/15] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 10/15] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 11/15] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 12/15] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade
2021-11-23  4:48   ` Vinod Koul
2021-11-24  7:33     ` Swapnil Kashinath Jakhade
2021-11-25  5:10       ` Vinod Koul
2021-12-02 14:12         ` Swapnil Kashinath Jakhade
2021-12-09  6:11           ` Milind Parab
2021-12-09 11:50             ` Vinod Koul
2021-12-09 11:53           ` Vinod Koul
2021-12-10  9:46             ` Swapnil Kashinath Jakhade
2021-12-14  9:22               ` Vinod Koul
2021-10-22 17:02 ` [PATCH v3 14/15] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock Swapnil Jakhade
2021-10-22 17:02 ` [PATCH v3 15/15] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade
2021-12-09  7:55 ` Kishon Vijay Abraham I [this message]

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