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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id z15-20020a05651c11cf00b00267db636cddsm3101755ljo.109.2022.09.08.06.56.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Sep 2022 06:56:26 -0700 (PDT) Message-ID: <4abfb333-fd68-d752-a140-d15828be2148@linaro.org> Date: Thu, 8 Sep 2022 15:56:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH 4/4] dt-bindings: memory: Add jedec,lpddrX-channel binding Content-Language: en-US To: Julius Werner Cc: Rob Herring , Dmitry Osipenko , Doug Anderson , Jian-Jia Su , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML References: <20220831013359.1807905-1-jwerner@chromium.org> <20220831013359.1807905-5-jwerner@chromium.org> <63c350a0-2393-208b-4fab-94db050407c2@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 01/09/2022 03:11, Julius Werner wrote: >>> +description: >>> + An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, >>> + CK, etc.) that connect one or more LPDDR chips to a host system. The main >>> + purpose of this node is to overall LPDDR topology of the system, including the >>> + amount of individual LPDDR chips and the ranks per chip. >> >> "channel" in this context confuses me a bit, because usually everyone is >> talking about DDR controller channels, not memory channels. I think this >> actually maps to a DDR controller channel? > > I'm not really sure what you mean by "memory channel" here (that would > be different from the DDR controller channel)? According to my > understanding there's only one kind of "channel" in the context of > main memory, that's the DDR controller channel (i.e. each separate > complete set of DDR pins coming out of the controller, as I tried to > explain in the description). > >>> + lpddr-channel1 { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + compatible = "jedec,lpddr4-channel"; >>> + io-width = <32>; >> >> I wonder now, how does it exactly work - channel is 32 bits, two ranks >> each with 32 bit IO bus. Your description said that: >> >> total_ram = (rank0 + rank1) * (channel_width / chip_width) >> so for this case: (4+2)*(32/32) = 6 Mbit >> >> If channel io-width = <64>, then memories are stacked in parallel and >> according to your description total RAM would be: (4+2)*(64/32) = 12 Mbit >> I wonder why stacking memories in parallel increases their size? > > Well, stacking in parallel just means you have more of them? In the > original example, you have a single LPDDR chip with two ranks, one > 4Gbit rank and one 2Gbit rank. That chip is directly hooked up to the > LPDDR controller and that's the only chip you have, so you have 4+2 = > 6Gbit total memory in the system. > > In your next example, the LPDDR controller has a 64 bit wide channel, > but you're still using that same 6Gbit LPDDR chip that only has 32 DQ > pins. The only way to fill out that 64 bit channel with this kind of > chip is to have two of them in parallel (one connected to DQ[0:31] and > one connected to DQ[32:63]). So we infer from the mismatch in io-width > that we have two chips. Each chip still has 6Gbit of memory, so the > total system would have 12Gbit. Two chips so more device nodes? Since there are no DTSes with it, please provide an additional example in the bindings. Best regards, Krzysztof