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([2401:4900:8f4d:6bb:6d92:919c:951b:7d96]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad7500e1d6sm111918585ad.58.2026.02.24.06.44.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Feb 2026 06:44:52 -0800 (PST) Message-ID: <4b16c937-6195-4307-88d2-874052203543@gmail.com> Date: Tue, 24 Feb 2026 20:14:45 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Alexandre Belloni , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20260217-arm-microchip-v1-0-ae5d907e10e3@gmail.com> <20260217-arm-microchip-v1-3-ae5d907e10e3@gmail.com> <20260217-surgical-gently-7f58e6fb5e5e@spud> Content-Language: en-US From: Akhila YS In-Reply-To: <20260217-surgical-gently-7f58e6fb5e5e@spud> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 17-02-2026 23:23, Conor Dooley wrote: > On Tue, Feb 17, 2026 at 05:24:21PM +0000, Akhila YS wrote: >> Convert Atmel Periodic interval timer of 64bit (PIT64b) binding to YAML >> format. >> Changes during conversion: >> - Add missing compatible "microchip,sama7g5-pit64b" along with a fallback >> compatible "microchip,sam9x60-pit64b". >> >> Signed-off-by: Akhila YS >> --- >> .../bindings/arm/microchip,sam9x60-pit64b.yaml | 71 ++++++++++++++++++++++ >> 1 file changed, 71 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml >> new file mode 100644 >> index 000000000000..6bf8e81d4c72 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml >> @@ -0,0 +1,71 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microchip PIT64B 64-bit Periodic Interval Timer >> + >> +maintainers: >> + - Nicolas Ferre >> + - Claudiu Beznea >> + >> +description: >> + The Microchip PIT64B is a 64-bit periodic interval timer used in >> + several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and >> + SAMA7D65 families. It provides extended timing range, flexible >> + clock selection and supports both periodic and one-shot interrupt >> + generation modes. >> + >> +properties: >> + compatible: >> + oneOf: >> + - const: microchip,sam9x60-pit64b >> + - items: >> + - const: microchip,sama7d65-pit64b >> + - const: microchip,sam9x60-pit64b >> + - items: >> + - const: microchip,sama7g5-pit64b >> + - const: microchip,sam9x60-pit64b >> + - items: >> + - const: microchip,sam9x7-pit64b >> + - const: microchip,sam9x60-pit64b > These three can be merged into one enum + const items list. Okay. > >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + clocks: >> + minItems: 1 >> + maxItems: 2 >> + >> + clock-names: >> + oneOf: >> + - const: pclk >> + - items: >> + - const: pclk >> + - const: gclk > This can be an items list with minItems: 1, but there should be some > conditional logic used to permit gclk only where it is valid. The text > binding removal is missing so I cannot say exactly what that logic > should be. Okay. > > pw-bot: changes-requested > > Cheers, > Conor. > >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + >> +unevaluatedProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + timer@f0028000 { >> + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; >> + reg = <0xf0028000 0x100>; >> + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; >> + clock-names = "pclk", "gclk"; >> + }; >> +... >> >> -- >> 2.43.0 >> -- Best Regards, Akhila.