From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90BB319992D; Tue, 15 Apr 2025 05:34:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744695270; cv=none; b=Kw1MDudVqGay3i6HdU0KXz+wvA6hTZO7aBYqdB57qylfa482ObB0kEzOMtFigO3oau4fWP6X2pTPOcEMfUgLQyid+g0+3MQ3fYuv4UNm0h3oO6NzunP6h155VyyIyO0kJLyahn5fggFL4koMBEu+jFA83U8k5+msp/gI6iAZ63g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744695270; c=relaxed/simple; bh=45o6nO1ZdabDZRp2mosO2ayRd8wFBJ7ZpP9Jr4qOmK0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=WahbjdBTo+9U936yautCBrFWV1RLinzbA7hZurPQnR5aKT2/d7panB3MgtwOyXpl135/syu50O9DI/t0rCrRHVPcSqO3ErBpcU36kjTseGK7GeZmL1aZvhWmbUmfYUM9dnz6z5QBZppOFPHAz8KqQCHLk8CNsjn7PFPux0Moxws= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KsdjjogM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KsdjjogM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 98203C4CEDD; Tue, 15 Apr 2025 05:34:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1744695270; bh=45o6nO1ZdabDZRp2mosO2ayRd8wFBJ7ZpP9Jr4qOmK0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KsdjjogMSU35get7rJpSvvMy+VkhJhyymfpDK8TmQz4J351HR9pBWxdxfB0c8SYRg yNKWwIwAqH96h642SSEh4QVPZ12p54L78O74Z+6CQGzWl7dRly9L/yyi9wWKUxReH/ 6d9uokbC/D95wk460z2A3wlNtGXvggrypCsyFqX2V8oqmeorWpx9rhnpdIPnXLAsG/ iIwtTv6+bmv1aDGpfcwoa/oWLmE7p28W5smy97fLA9lsbix6nzPSrgsJWt27YzUqSH H6H1IjW7zosBrHbNoG62r7+QaloK/AQQ2vpvYCi49nW1fv3zjeBLfKOco488CmD/q7 /jM6Hg676nIWg== Message-ID: <4b741da1-6540-4e5c-aa32-098420cab3c2@kernel.org> Date: Tue, 15 Apr 2025 07:34:22 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND PATCH v7 1/2] dt-bindings: PCI: xilinx-cpm: Add `cpm_crx` and `cpm5nc_fw_attr` properties To: "Musham, Sai Krishna" Cc: "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kw@linux.com" , "manivannan.sadhasivam@linaro.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "cassel@kernel.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Simek, Michal" , "Gogada, Bharat Kumar" , "Havalige, Thippeswamy" References: <20250414032304.862779-1-sai.krishna.musham@amd.com> <20250414032304.862779-2-sai.krishna.musham@amd.com> <20250414-naughty-simple-rattlesnake-bb75bb@shite> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 14/04/2025 14:23, Musham, Sai Krishna wrote: > [AMD Official Use Only - AMD Internal Distribution Only] > > Hi Krzysztof, > > Thanks for the review. > >> -----Original Message----- >> From: Krzysztof Kozlowski >> Sent: Monday, April 14, 2025 12:32 PM >> To: Musham, Sai Krishna >> Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; >> manivannan.sadhasivam@linaro.org; robh@kernel.org; krzk+dt@kernel.org; >> conor+dt@kernel.org; cassel@kernel.org; linux-pci@vger.kernel.org; >> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Simek, Michal >> ; Gogada, Bharat Kumar >> ; Havalige, Thippeswamy >> >> Subject: Re: [RESEND PATCH v7 1/2] dt-bindings: PCI: xilinx-cpm: Add `cpm_crx` >> and `cpm5nc_fw_attr` properties >> >> Caution: This message originated from an External Source. Use proper caution >> when opening attachments, clicking links, or responding. >> >> >> On Mon, Apr 14, 2025 at 08:53:03AM GMT, Sai Krishna Musham wrote: >>> Add the `cpm_crx` property to manage the PCIe IP reset, and >>> `cpm5nc_fw_attr` property to clear firewall after link reset, while >>> maintaining backward compatibility with existing device trees. >>> >>> Also, incorporate `reset-gpios` in example for GPIO-based handling of >>> the PCIe Root Port (RP) PERST# signal for enabling assert and deassert >>> control. >>> >>> The `reset-gpios` and `cpm_crx` properties must be provided for CPM, >>> CPM5 and CPM5_HOST1. For CPM5NC, all three properties - `reset-gpios`, >>> `cpm_crx` and `cpm5nc_fw_attr` must be explicitly defined to ensure >> >> This we see from the diff, but why they must be defined? >> >>> proper functionality. >> >> What functionality? >> > > For our controller, if cpm_crx is not provided lane errors will be observed. > Specifically for CPM5NC, if cpm5nc_fw_attr property is not provided, the firewall > is not cleared after reset and further PCIe transactions will not be allowed. > Therefore, these properties must be defined. This must be in the commit msg. > >>> >>> Include an example DTS node and complete the binding documentation for >>> CPM5NC. Also, fix the bridge register address size in the example for >>> CPM5. >>> >>> Signed-off-by: Sai Krishna Musham >>> --- >>> Changes for v7: >>> - Update CPM5NC device tree binding. >>> - Add CPM5NC device tree example node. >>> - Update commit message. >>> >>> Changes for v6: >>> - Resolve ABI break. >>> - Update commit message. >>> >> >> ... >> >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - xlnx,versal-cpm5nc-host >>> + then: >>> + properties: >>> + reg: >>> + items: >>> + - description: CPM system level control and status registers. >>> + - description: Configuration space region and bridge registers. >>> + - description: CPM clock and reset control registers. >>> + - description: CPM5NC Firewall attribute register. >>> + minItems: 2 >>> + reg-names: >>> + items: >>> + - const: cpm_slcr >>> + - const: cfg >>> + - const: cpm_crx >>> + - const: cpm5nc_fw_attr >>> + minItems: 2 >> >> Why interrupts are not required for this variant? Why isn't this an >> interrupt controller? >> > > MSI and MSI-X interrupts are handled via GIC, so msi-map property is > required for interrupt handling. > Legacy interrupt support is not available, and Error interrupt support will be > added in future, once it is added corresponding DT changes will be added. I don't think commit msg explained this. > Best regards, Krzysztof