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Subject: Re: [PATCH v2 2/2] clk: clk-conf: support assigned-clock-rates-u64
From: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
To: Luca Ceresoli <luca.ceresoli@bootlin.com>, Michael Turquette <mturquette@baylibre.com>, Peng Fan (OSS) <peng.fan@oss.nxp.com>, Rob Herring <robh@kernel.org>, Saravana Kannan <saravanak@google.com>
Date: Mon, 29 Jul 2024 17:22:59 -0700
User-Agent: alot/0.10

Quoting Peng Fan (OSS) (2024-07-28 19:30:53)
> diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
> index 058420562020..37b72600b296 100644
> --- a/drivers/clk/clk-conf.c
> +++ b/drivers/clk/clk-conf.c
> @@ -78,47 +78,89 @@ static int __set_clk_parents(struct device_node *node=
, bool clk_supplier)
[...]
> +static int __set_clk_rates(struct device_node *node, bool clk_supplier)
> +{
> +       int rc, index =3D 0;
> +       u64 rate;
> +       u32 rate_32;
> +       bool is_rate_32 =3D false;
> +
> +       if (!of_find_property(node, "assigned-clock-rates-u64", NULL))
> +               is_rate_32 =3D true;
> +
> +       if (is_rate_32) {
> +               of_property_for_each_u32(node, "assigned-clock-rates", ra=
te_32) {
> +                       if (rate_32) {
> +                               rc =3D __set_clk_rate(node, clk_supplier,=
 index, rate_32);
> +
> +                               if (rc =3D=3D 1 && !clk_supplier)
> +                                       return 0;
> +
> +                               if (rc < 0) {
> +                                       /* skip empty (null) phandles */
> +                                       if (rc =3D=3D -ENOENT)
> +                                               continue;
> +                                       else
> +                                               return rc;
> +                               }
>                         }
> +                       index++;
> +               }
> +       } else {
> +               of_property_for_each_u64(node, "assigned-clock-rates-u64"=
, rate) {
> +                       if (rate) {
> +                               rc =3D __set_clk_rate(node, clk_supplier,=
 index, rate);
> =20
> -                       rc =3D clk_set_rate(clk, rate);
> -                       if (rc < 0)
> -                               pr_err("clk: couldn't set %s clk rate to =
%u (%d), current rate: %lu\n",
> -                                      __clk_get_name(clk), rate, rc,
> -                                      clk_get_rate(clk));
> -                       clk_put(clk);
> +                               if (rc =3D=3D 1 && !clk_supplier)
> +                                       return 0;
> +
> +                               if (rc < 0) {
> +                                       /* skip empty (null) phandles */
> +                                       if (rc =3D=3D -ENOENT)
> +                                               continue;
> +                                       else
> +                                               return rc;
> +                               }
> +                       }
> +                       index++;

This patch is hard to read. I suspect that's because this code to skip
empty phandles is repeated. Can you expand
of_property_for_each_u{32,64}() and combine the loops? Doing that should
allow us to avoid repeating the same logic twice.