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[88.207.97.74]) by smtp.gmail.com with ESMTPSA id l9-20020a1709063d2900b0077086d2db8esm8789136ejf.140.2022.10.05.06.50.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Oct 2022 06:50:38 -0700 (PDT) Message-ID: <4bc9033c-624e-bafb-a6f7-3915a1b27664@gmail.com> Date: Wed, 5 Oct 2022 15:50:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.1 Subject: Re: [PATCH] dt-bindings: soc: qcom: qcom,spm: support regulator SAW2 devics Content-Language: en-US To: Dmitry Baryshkov , Krzysztof Kozlowski , Christian Marangi Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20220930231416.925132-1-dmitry.baryshkov@linaro.org> From: Robert Marko In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 02. 10. 2022. 14:20, Dmitry Baryshkov wrote: > On Sun, 2 Oct 2022 at 11:49, Krzysztof Kozlowski > wrote: >> On 01/10/2022 01:14, Dmitry Baryshkov wrote: >>> Merge qcom,saw2.txt bindings to existing qcom,spm.yaml. This fixes >>> compatibility of qcom,spm schema with regulator SAW2 devices. >>> >>> Signed-off-by: Dmitry Baryshkov >>> --- >>> .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ------------------- >>> .../bindings/soc/qcom/qcom,spm.yaml | 44 +++++++++----- >> You need to update reference in >> Documentation/devicetree/bindings/arm/cpus.yaml > ack > >>> 2 files changed, 30 insertions(+), 72 deletions(-) >>> delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt >>> >>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt >>> deleted file mode 100644 >>> index c0e3c3a42bea..000000000000 >>> --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt > [skipped] > >>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml >>> index f433e6e0a19f..8fe35fde70b8 100644 >>> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml >>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml >>> @@ -16,23 +16,33 @@ description: | >>> >>> properties: >>> compatible: >>> - items: >>> - - enum: >>> - - qcom,sdm660-gold-saw2-v4.1-l2 >>> - - qcom,sdm660-silver-saw2-v4.1-l2 >>> - - qcom,msm8998-gold-saw2-v4.1-l2 >>> - - qcom,msm8998-silver-saw2-v4.1-l2 >>> - - qcom,msm8909-saw2-v3.0-cpu >>> - - qcom,msm8916-saw2-v3.0-cpu >>> - - qcom,msm8226-saw2-v2.1-cpu >>> - - qcom,msm8974-saw2-v2.1-cpu >>> - - qcom,apq8084-saw2-v2.1-cpu >>> - - qcom,apq8064-saw2-v1.1-cpu >>> + oneOf: >>> - const: qcom,saw2 >> I understand old bindings had it, but I don't think we really want to >> support the generic compatible on its own. Even old bindings indicated >> that there are several differences between SAWs. >> >> Especially confusing is that once qcom,saw2 can be alone and in other >> cases must be preceded by specific compatible. IOW, you allow for >> apq8064 two cases: >> >> 1. qcom,apq8064-saw2-v1.1-cpu, qcom,saw2 >> 2. qcom,saw2 >> >> I think we should instead add everywhere specific compatibles. > I see your point. Yes, it's probably worth doing that. > > Robert, Christian, can you possibly check the version of the SAW2 used > on ipq4019 and ipq8064? It can be read from the SPM block at the > register offset 0xfd0. Hi, I completely missed this so far, sorry about that. I checked from U-boot on multiple SAW blocks on IPQ4019 and it looks to be v3.0: (IPQ40xx) # md.l 0xB0B9FD0 1 0b0b9fd0: 30000000    ...0 (IPQ40xx) # md.l 0xB089FD0 1 0b089fd0: 30000000    ...0 (IPQ40xx) # md.l 0xB099FD0 1 0b099fd0: 30000000    ...0 (IPQ40xx) # md.l 0xB0A9FD0 1 0b0a9fd0: 30000000    ...0 IPQ8064 is a bit weird, both SAW-s from DTS show all zeros: (IPQ) # md.l 0x2089FD0 1 02089fd0: 00000000    .... (IPQ) # md.l 0x2099FD0 1 02099fd0: 00000000    .... However some old datasheet says: 0x02011FD0 APCS_VERSION (IPQ) # md.l 0x02011FD0 1 02011fd0: 10010000    .... But It also says that minor and step are both bits 15:0 which makes no sense. Hope this helps, Robert > >>> + - items: >>> + - enum: >>> + - qcom,sdm660-gold-saw2-v4.1-l2 >>> + - qcom,sdm660-silver-saw2-v4.1-l2 >>> + - qcom,msm8998-gold-saw2-v4.1-l2 >>> + - qcom,msm8998-silver-saw2-v4.1-l2 >>> + - qcom,msm8909-saw2-v3.0-cpu >>> + - qcom,msm8916-saw2-v3.0-cpu >>> + - qcom,msm8226-saw2-v2.1-cpu >>> + - qcom,msm8974-saw2-v2.1-cpu >>> + - qcom,apq8084-saw2-v2.1-cpu >>> + - qcom,apq8064-saw2-v1.1-cpu >>> + - const: qcom,saw2 >>> >>> reg: >>> - description: Base address and size of the SPM register region >>> - maxItems: 1 >>> + description: Base address and size of the SPM register region. An optional >>> + second element specifies the base address and size of the alias register >>> + region. >>> + minItems: 1 >>> + maxItems: 2 >> And it seems second region is not present on some variants? > The second region is a bit of a puzzle for me as it doesn't seem to be > used at all. >