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Fri, 28 Mar 2025 08:48:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by HK2PEPF00006FAF.mail.protection.outlook.com (10.167.8.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.20 via Frontend Transport; Fri, 28 Mar 2025 08:48:28 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id B90254160CA0; Fri, 28 Mar 2025 16:48:27 +0800 (CST) Message-ID: <4bcc07b1-00ce-4ff9-bf23-e06b78950026@cixtech.com> Date: Fri, 28 Mar 2025 16:48:27 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations To: Krzysztof Kozlowski , Manikandan Karunakaran Pillai Cc: "bhelgaas@google.com" , "lpieralisi@kernel.org" , "kw@linux.com" , "manivannan.sadhasivam@linaro.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" References: <20250327111106.2947888-1-mpillai@cadence.com> <20250328-poised-dolphin-of-sympathy-e1d83e@krzk-bin> Content-Language: en-US From: Hans Zhang In-Reply-To: <20250328-poised-dolphin-of-sympathy-e1d83e@krzk-bin> Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2025 08:48:28.6637 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c4a9fe3-d727-402d-029c-08dd6dd54fb4 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: HK2PEPF00006FAF.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: JH0PR06MB6416 On 2025/3/28 16:22, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL > > On Thu, Mar 27, 2025 at 11:19:47AM +0000, Manikandan Karunakaran Pillai wrote: >> Document the compatible property for the newly added values for PCIe EP and >> RP configurations. Fix the compilation issues that came up for the existing >> Cadence bindings >> >> Signed-off-by: Manikandan K Pillai >> --- >> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 12 +- >> .../bindings/pci/cdns,cdns-pcie-host.yaml | 119 +++++++++++++++--- >> 2 files changed, 110 insertions(+), 21 deletions(-) > > One more thing: SoB mismatch. Maybe got corrupted by Microsoft (it is > known), so you really need to fix your mailing setup or use b4 relay. > Hi Krzysztof, I have obtained Manikandan's consent and we will collaborate to submit the series patch. Our Cixtech P1 (internal name sky1) is currently upstream. Because I need upstream Cadence root port driver, However, the Cadence common code of the current linux master does not support HPA[High Performance Architecture IP] is the second generation of cadence PCIe IP. Subsequently, I will send git send-email to pci mail list. Peter Chen patchs: https://patchwork.kernel.org/project/linux-arm-kernel/cover/20250324062420.360289-1-peter.chen@cixtech.com/ Best regards, Hans