Re: [PATCH 1/2] dt-bindings: iio: dac: add docs for ad8460

["Nuno Sá" <noname.nuno@gmail.com>]

On Sat, 2024-05-11 at 13:47 -0500, David Lechner wrote:
> On Sat, May 11, 2024 at 11:25 AM Jonathan Cameron <jic23@kernel.org> wrote:
> > 
> > On Fri, 10 May 2024 12:28:19 -0500
> > David Lechner <dlechner@baylibre.com> wrote:
> > 
> > > On Fri, May 10, 2024 at 1:42 AM Mariel Tinaco <Mariel.Tinaco@analog.com>
> > > wrote:
> > > > 
> > > > This adds the bindings documentation for the 14-bit
> > > > High Voltage, High Current, Waveform Generator
> > > > Digital-to-Analog converter.
> > > > 
> > > > Signed-off-by: Mariel Tinaco <Mariel.Tinaco@analog.com>
> > > > ---
> > > >  .../bindings/iio/dac/adi,ad8460.yaml          | 67 +++++++++++++++++++
> > > >  MAINTAINERS                                   |  7 ++
> > > >  2 files changed, 74 insertions(+)
> > > >  create mode 100644
> > > > Documentation/devicetree/bindings/iio/dac/adi,ad8460.yaml
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad8460.yaml
> > > > b/Documentation/devicetree/bindings/iio/dac/adi,ad8460.yaml
> > > > new file mode 100644
> > > > index 000000000..924f76209
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad8460.yaml
> > > > @@ -0,0 +1,67 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > > +# Copyright 2024 Analog Devices Inc.
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/iio/dac/adi,ad8460.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Analog Devices AD8460 DAC
> > > > +
> > > > +maintainers:
> > > > +  - Mariel Tinaco <mariel.tinaco@analog.com>
> > > > +
> > > > +description: |
> > > > +  Analog Devices AD8460 110 V High Voltage, 1 A High Current,
> > > > +  Arbitrary Waveform Generator with Integrated 14-Bit High Speed DAC
> > > > + 
> > > > https://www.analog.com/media/en/technical-documentation/data-sheets/ad8460.pdf
> > > > +
> > > > +properties:
> > > > +  compatible:
> > > > +    enum:
> > > > +      - adi,ad8460
> > > > +
> > > > +  reg:
> > > > +    maxItems: 1
> > > > +
> > > > +  spi-max-frequency:
> > > > +    maximum: 20000000
> > > > +
> > > > +  vref-supply:
> > > 
> > > It would be nice to make the property name match the pin name since
> > > there is more than one reference voltage input.
> > > 
> > > refio-1p2v-supply:
> > > 
> > > > +    description: Drive voltage in the range of 1.2V maximum to as low
> > > > as
> > > > +      low as 0.12V through the REF_IO pin to adjust full scale output
> > > > span
> > > 
> > > I don't seen anything in the datasheet named REF_IO. Is this a typo
> > > and it should be REFIO_1P2V?
> > > 
> > > > +
> > > > +  clocks:
> > > > +    description: The clock for the DAC. This is the sync clock
> > > > +
> > > > +  adi,rset-ohms:
> > > > +    description: Specify value of external resistor connected to FS_ADJ
> > > > pin
> > > > +      to establish internal HVDAC's reference current I_REF
> > > > +    minimum: 2000
> > > > +    maximum: 20000
> > > > +
> > > 
> > > I see lots more pins on the datasheet, many of which should be trivial
> > > to add bindings for (we prefer to have the bindings as complete as
> > > possible even if the driver doesn't implement everything). Potential
> > > candidates:
> > > 
> > > sdn-reset-gpios: (active high)
> > > reset-gpios: (active low)
> > > sdn-io-gpios: (active high)
> > > 
> > > hvcc-supply:
> > > hvee-supply:
> > > vcc-5v-supply:
> > > vref-5v-supply:
> > > dvdd-3p3v-supply:
> > > avdd-3p3v-supply:
> > > 
> > > It also looks like there is a parallel interface for data, so I would
> > > expect to see an io-backends property that links to the PHY used for
> > > handling that.
> > > 
> > Ultimately yes, but the parallel interface might require some decisions on
> > binding that are non obvious until it's actually implemented. So maybe
> > don't need that bit from the start.  The rest I agree should be here.
> > 
> > 
> 
> Since the driver patch uses a DMA channel that isn't documented here,
> I am assuming that the parallel interface is being used so we do need
> to consider it now. :-)

AFAIU, the way this is designed, the parallel interface is directly connected to
the DMA IP controller. So, at this point there's really no use for the DAC
backend. We may have different designs in the future but no use case for now.

- Nuno Sá