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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id m21-20020aa7c2d5000000b0042617ba6395sm1002195edp.31.2022.04.27.23.56.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Apr 2022 23:56:39 -0700 (PDT) Message-ID: <4d37f41c-4463-73e4-7271-8d191e9953af@linaro.org> Date: Thu, 28 Apr 2022 08:56:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 01/11] dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional Content-Language: en-US To: Andre Przywara , Rob Herring , Krzysztof Kozlowski Cc: Liviu Dudau , Robin Murphy , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Will Deacon , iommu@lists.linux-foundation.org References: <20220427112528.4097815-1-andre.przywara@arm.com> <20220427112528.4097815-2-andre.przywara@arm.com> From: Krzysztof Kozlowski In-Reply-To: <20220427112528.4097815-2-andre.przywara@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 27/04/2022 13:25, Andre Przywara wrote: > The Page Request Interface (PRI) is an optional PCIe feature. As such, a > SMMU would not need to handle it if the PCIe host bridge or the SMMU > itself do not implement it. Also an SMMU could be connected to a platform > device, without any PRI functionality whatsoever. > In all cases there would be no SMMU PRI queue interrupt to be wired up > to an interrupt controller. > > Relax the binding to allow specifying three interrupts, omitting the PRI > IRQ. At the moment, with the "eventq,gerror,priq,cmdq-sync" order, we > would need to sacrifice the command queue sync interrupt as well, which > might not be desired. > The Linux driver does not care about any order at all, just picks IRQs > based on their names, and treats all (wired) IRQs as optional. The last sentence is not a good explanation for the bindings. They are not about Linux and are used in other projects as well. > > Signed-off-by: Andre Przywara > --- > .../bindings/iommu/arm,smmu-v3.yaml | 21 ++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > index e87bfbcc69135..6b3111f1f06ce 100644 > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml > @@ -37,12 +37,23 @@ properties: > hardware supports just a single, combined interrupt line. > If provided, then the combined interrupt will be used in preference to > any others. > - - minItems: 2 > + - minItems: 1 > items: > - - const: eventq # Event Queue not empty > - - const: gerror # Global Error activated > - - const: priq # PRI Queue not empty > - - const: cmdq-sync # CMD_SYNC complete > + - enum: > + - eventq # Event Queue not empty > + - gerror # Global Error activated > + - cmdq-sync # CMD_SYNC complete > + - priq # PRI Queue not empty > + - enum: > + - gerror > + - cmdq-sync > + - priq > + - enum: > + - cmdq-sync > + - priq > + - enum: > + - cmdq-sync > + - priq The order should be strict, so if you want the first interrupt optional, then: oneOf: - items: ... 4 items list - items ... 3 items list Best regards, Krzysztof