Re: [PATCH 4/4] spi: dt-bindings: qcom,spi-qup: convert to dtschema

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 30/03/2022 13:42, Kuldeep Singh wrote:
> On Tue, Mar 29, 2022 at 01:29:02PM +0200, Krzysztof Kozlowski wrote:
>> Convert the Qualcomm Universal Peripheral (QUP) Serial Peripheral
>> Interface (SPI) bindings to DT Schema.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> ---
>>  .../devicetree/bindings/spi/qcom,spi-qup.txt  | 103 ------------------
>>  .../devicetree/bindings/spi/qcom,spi-qup.yaml |  82 ++++++++++++++
>>  2 files changed, 82 insertions(+), 103 deletions(-)
>>  delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
>>  create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
>> deleted file mode 100644
>> index 5c090771c016..000000000000
>> --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
>> +++ /dev/null
>> @@ -1,103 +0,0 @@
>> -Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
>> -
>> -The QUP core is an AHB slave that provides a common data path (an output FIFO
>> -and an input FIFO) for serial peripheral interface (SPI) mini-core.
>> -
>> -SPI in master mode supports up to 50MHz, up to four chip selects, programmable
>> -data path from 4 bits to 32 bits and numerous protocol variants.
>> -
>> -Required properties:
>> -- compatible:     Should contain:
>> -		  "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
>> -		  "qcom,spi-qup-v2.1.1" for 8974 and later
>> -		  "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
>> -
>> -- reg:            Should contain base register location and length
>> -- interrupts:     Interrupt number used by this controller
>> -
>> -- clocks:         Should contain the core clock and the AHB clock.
>> -- clock-names:    Should be "core" for the core clock and "iface" for the
>> -                  AHB clock.
>> -
>> -- #address-cells: Number of cells required to define a chip select
>> -                  address on the SPI bus. Should be set to 1.
>> -- #size-cells:    Should be zero.
>> -
>> -Optional properties:
>> -- spi-max-frequency: Specifies maximum SPI clock frequency,
>> -                     Units - Hz. Definition as per
>> -                     Documentation/devicetree/bindings/spi/spi-bus.txt
>> -- num-cs:	total number of chipselects
>> -- cs-gpios:	should specify GPIOs used for chipselects.
>> -		The gpios will be referred to as reg = <index> in the SPI child
>> -		nodes.  If unspecified, a single SPI device without a chip
>> -		select can be used.
>> -
>> -- dmas:         Two DMA channel specifiers following the convention outlined
>> -                in bindings/dma/dma.txt
>> -- dma-names:    Names for the dma channels, if present. There must be at
>> -                least one channel named "tx" for transmit and named "rx" for
>> -                receive.
>> -
>> -SPI slave nodes must be children of the SPI master node and can contain
>> -properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
>> -
>> -Example:
>> -
>> -	spi_8: spi@f9964000 { /* BLSP2 QUP2 */
>> -
>> -		compatible = "qcom,spi-qup-v2";
>> -		#address-cells = <1>;
>> -		#size-cells = <0>;
>> -		reg = <0xf9964000 0x1000>;
>> -		interrupts = <0 102 0>;
>> -		spi-max-frequency = <19200000>;
>> -
>> -		clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
>> -		clock-names = "core", "iface";
>> -
>> -		dmas = <&blsp1_bam 13>, <&blsp1_bam 12>;
>> -		dma-names = "rx", "tx";
>> -
>> -		pinctrl-names = "default";
>> -		pinctrl-0 = <&spi8_default>;
>> -
>> -		device@0 {
>> -			compatible = "arm,pl022-dummy";
>> -			#address-cells = <1>;
>> -			#size-cells = <1>;
>> -			reg = <0>; /* Chip select 0 */
>> -			spi-max-frequency = <19200000>;
>> -			spi-cpol;
>> -		};
>> -
>> -		device@1 {
>> -			compatible = "arm,pl022-dummy";
>> -			#address-cells = <1>;
>> -			#size-cells = <1>;
>> -			reg = <1>; /* Chip select 1 */
>> -			spi-max-frequency = <9600000>;
>> -			spi-cpha;
>> -		};
>> -
>> -		device@2 {
>> -			compatible = "arm,pl022-dummy";
>> -			#address-cells = <1>;
>> -			#size-cells = <1>;
>> -			reg = <2>; /* Chip select 2 */
>> -			spi-max-frequency = <19200000>;
>> -			spi-cpol;
>> -			spi-cpha;
>> -		};
>> -
>> -		device@3 {
>> -			compatible = "arm,pl022-dummy";
>> -			#address-cells = <1>;
>> -			#size-cells = <1>;
>> -			reg = <3>; /* Chip select 3 */
>> -			spi-max-frequency = <19200000>;
>> -			spi-cpol;
>> -			spi-cpha;
>> -			spi-cs-high;
>> -		};
>> -	};
>> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
>> new file mode 100644
>> index 000000000000..aa5756f7ba85
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
>> @@ -0,0 +1,82 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
>> +
>> +maintainers:
>> +  - Andy Gross <agross@kernel.org>
>> +  - Bjorn Andersson <bjorn.andersson@linaro.org>
>> +  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> +
>> +description:
>> +  The QUP core is an AHB slave that provides a common data path (an output FIFO
>> +  and an input FIFO) for serial peripheral interface (SPI) mini-core.
>> +
>> +  SPI in master mode supports up to 50MHz, up to four chip selects,
>> +  programmable data path from 4 bits to 32 bits and numerous protocol variants.
>> +
>> +allOf:
>> +  - $ref: /spi/spi-controller.yaml#
> 
> Same thing for reference here as we discussed on other thread.

Yes.

> 
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
>> +      - qcom,spi-qup-v2.1.1 # for 8974 and later
>> +      - qcom,spi-qup-v2.2.1 # for 8974 v2 and later
>> +
>> +  clocks:
>> +    maxItems: 2
>> +
>> +  clock-names:
>> +    items:
>> +      - const: core
>> +      - const: iface
>> +
>> +  dmas:
>> +    maxItems: 2
>> +
>> +  dma-names:
>> +    items:
>> +      - const: tx
>> +      - const: rx
> 
> Just wanted to confirm one thing, did you try with rx-tx?
> As once I noticed for some other spec, that warnings were reduced when
> order was reversed as most of the DTs follow rx-tx order.
> 
> We can keep order which disturb less DTs.

Yeah, I tried. The amount is more or less the same, so I went with tx-rx
as mentioned in original bindings.

> 
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - clock-names
>> +  - interrupts
>> +  - reg
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    spi@7575000 {
>> +        compatible = "qcom,spi-qup-v2.2.1";
>> +        reg = <0x07575000 0x600>;
>> +        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> +        clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
>> +                 <&gcc GCC_BLSP1_AHB_CLK>;
>> +        clock-names = "core",
>> +                      "iface";
> 
> clock-names can be written in one line.

I made it on purpose to align the format with clocks.

Best regards,
Krzysztof