[PATCH 0/3] Add UltraRISC DP1000 PLIC support

[PATCH 0/3] Add UltraRISC DP1000 PLIC support

[Lucas Zampieri]

This series adds support for the PLIC implementation in the UltraRISC
DP1000 SoC. The DP1000 PLIC claim register has a hardware bug where
reading it while multiple interrupts are pending can return the wrong
interrupt ID. The workaround temporarily disables all interrupts except
the first pending one before reading the claim register, then restores
the previous state. This is implemented as PLIC_QUIRK_CLAIM_REGISTER,
activated only for "ultrarisc,dp1000-plic" compatible strings.

Charles Mirabile (2):
  dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC
  irqchip/plic: add support for UltraRISC DP1000 PLIC

Lucas Zampieri (1):
  dt-bindings: vendor-prefixes: add UltraRISC

 .../devicetree/bindings/vendor-prefixes.yaml      |  2 +
 .../interrupt-controller/sifive,plic-1.0.0.yaml    |  2 +
 drivers/irqchip/irq-sifive-plic.c                  | 83 ++++++++++++++++++-
 3 files changed, 86 insertions(+), 1 deletion(-)

--
2.51.0

[PATCH 1/3] dt-bindings: vendor-prefixes: add UltraRISC

[Lucas Zampieri]

Add vendor prefix for UltraRISC Technology Co., Ltd.

Signed-off-by: Lucas Zampieri <lzampier@redhat.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 123456789abc..234567890def 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1642,6 +1642,8 @@ patternProperties:
     description: Universal Scientific Industrial Co., Ltd.
   "^usr,.*":
     description: U.S. Robotics Corporation
+  "^ultrarisc,.*":
+    description: UltraRISC Technology Co., Ltd.
   "^ultratronik,.*":
     description: Ultratronik GmbH
   "^utoo,.*":
--
2.51.0

[PATCH 2/3] dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC

[Lucas Zampieri]

From: Charles Mirabile <cmirabil@redhat.com>

Add a new compatible string for UltraRISC DP1000 PLIC.

Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 5b827bc24301..a419de50f5a8 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -74,6 +74,8 @@ properties:
               - sophgo,sg2044-plic
               - thead,th1520-plic
           - const: thead,c900-plic
+      - items:
+          - const: ultrarisc,dp1000-plic
       - items:
           - const: sifive,plic-1.0.0
           - const: riscv,plic0
--
2.51.0

[PATCH 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC

[Lucas Zampieri]

From: Charles Mirabile <cmirabil@redhat.com>

Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to
work around a known hardware bug with IRQ claiming.

When claiming an interrupt on the DP1000 PLIC all other interrupts must be
disabled before the claim register is accessed to prevent incorrect
handling of the interrupt.

When the PLIC_QUIRK_CLAIM_REGISTER is present, during plic_handle_irq
the enable state of all interrupts is saved and then all interrupts
except for the first pending one are disabled before reading the claim
register. The interrupts are then restored before further processing of
the claimed interrupt continues.

This modification matches "ultrarisc,dp1000-plic" and has no impact on
other platforms.

Co-developed-by: Zhang Xincheng <zhangxincheng@ultrarisc.com>
Signed-off-by: Zhang Xincheng <zhangxincheng@ultrarisc.com>
Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
---
 drivers/irqchip/irq-sifive-plic.c | 83 ++++++++++++++++++++++++++++++-
 1 file changed, 82 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 9c4af7d58846..a7b51a925e96 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -49,6 +49,8 @@
 #define CONTEXT_ENABLE_BASE		0x2000
 #define     CONTEXT_ENABLE_SIZE		0x80

+#define PENDING_BASE                    0x1000
+
 /*
  * Each hart context has a set of control registers associated with it.  Right
  * now there's only two: a source priority threshold over which the hart will
@@ -63,6 +65,7 @@
 #define	PLIC_ENABLE_THRESHOLD		0

 #define PLIC_QUIRK_EDGE_INTERRUPT	0
+#define PLIC_QUIRK_CLAIM_REGISTER	1

 struct plic_priv {
 	struct fwnode_handle *fwnode;
@@ -367,6 +370,82 @@ static const struct irq_domain_ops plic_irqdomain_ops = {
 	.free		= irq_domain_free_irqs_top,
 };

+static bool dp1000_isolate_pending_irq(int nr_irq_groups, u32 ie[],
+				       void __iomem *pending,
+				       void __iomem *enable)
+{
+	u32 pending_irqs = 0;
+	int i, j;
+
+	/* Look for first pending interrupt */
+	for (i = 0; i < nr_irq_groups; i++) {
+		pending_irqs = ie[i] & readl(pending + i * sizeof(u32));
+		if (pending_irqs)
+			break;
+	}
+
+	if (!pending_irqs)
+		return false;
+
+	/* Disable all interrupts but the first pending one */
+	for (j = 0; j < nr_irq_groups; j++) {
+		u32 new_mask = 0;
+
+		if (j == i)
+			/* Extract mask with lowest set bit */
+			new_mask = (pending_irqs & -pending_irqs);
+
+		writel(new_mask, enable + j * sizeof(u32));
+	}
+
+	return true;
+}
+
+static irq_hw_number_t dp1000_get_hwirq(struct plic_handler *handler,
+					void __iomem *claim)
+{
+	void __iomem *enable = handler->enable_base;
+	void __iomem *pending = handler->priv->regs + PENDING_BASE;
+	int nr_irqs = handler->priv->nr_irqs;
+	int nr_irq_groups = DIV_ROUND_UP(nr_irqs, 32);
+	int i;
+	u32 ie[32] = { 0 };
+	irq_hw_number_t hwirq = 0;
+
+	raw_spin_lock(&handler->enable_lock);
+
+	/* Save current interrupt enable state */
+	for (i = 0; i < nr_irq_groups; i++)
+		ie[i] = readl(enable + i * sizeof(u32));
+
+	if (!dp1000_isolate_pending_irq(nr_irq_groups, ie, pending, enable))
+		goto out;
+
+	hwirq = readl(claim);
+
+	/* Restore previous state */
+	for (i = 0; i < nr_irq_groups; i++)
+		writel(ie[i], enable + i * sizeof(u32));
+out:
+	raw_spin_unlock(&handler->enable_lock);
+	return hwirq;
+}
+
+static irq_hw_number_t plic_get_hwirq(struct plic_handler *handler,
+				      void __iomem *claim)
+{
+	/*
+	 * Due to a hardware bug in the implementation of the claim register
+	 * in the UltraRISC DP1000 platform, other interrupts must be disabled
+	 * before reading the claim register and restored afterwards.
+	 */
+
+	if (test_bit(PLIC_QUIRK_CLAIM_REGISTER, &handler->priv->plic_quirks))
+		return dp1000_get_hwirq(handler, claim);
+
+	return readl(claim);
+}
+
 /*
  * Handling an interrupt is a two-step process: first you claim the interrupt
  * by reading the claim register, then you complete the interrupt by writing
@@ -384,7 +463,7 @@ static void plic_handle_irq(struct irq_desc *desc)

 	chained_irq_enter(chip, desc);

-	while ((hwirq = readl(claim))) {
+	while ((hwirq = plic_get_hwirq(handler, claim))) {
 		int err = generic_handle_domain_irq(handler->priv->irqdomain,
 						    hwirq);
 		if (unlikely(err)) {
@@ -432,6 +511,8 @@ static const struct of_device_id plic_match[] = {
 	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
 	{ .compatible = "thead,c900-plic",
 	  .data = (const void *)BIT(PLIC_QUIRK_EDGE_INTERRUPT) },
+	{ .compatible = "ultrarisc,dp1000-plic",
+	  .data = (const void *)BIT(PLIC_QUIRK_CLAIM_REGISTER) },
 	{}
 };

--
2.51.0

Re: [PATCH 2/3] dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC

[Krzysztof Kozlowski]

On 09/10/2025 17:20, Lucas Zampieri wrote:
> From: Charles Mirabile <cmirabil@redhat.com>
> 
> Add a new compatible string for UltraRISC DP1000 PLIC.
> 
> Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
> ---
>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml        | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 5b827bc24301..a419de50f5a8 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -74,6 +74,8 @@ properties:
>                - sophgo,sg2044-plic
>                - thead,th1520-plic
>            - const: thead,c900-plic
> +      - items:


Missing SoC specific front compatible, me thinks.


Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC

[Krzysztof Kozlowski]

On 09/10/2025 17:29, Krzysztof Kozlowski wrote:
> On 09/10/2025 17:20, Lucas Zampieri wrote:
>> From: Charles Mirabile <cmirabil@redhat.com>
>>
>> Add a new compatible string for UltraRISC DP1000 PLIC.
>>
>> Signed-off-by: Charles Mirabile <cmirabil@redhat.com>


And incomplete SoB chain. See submitting patches and DCO.

Best regards,
Krzysztof

Re: [PATCH 2/3] dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC

[Lucas Zampieri]

On Thu, Oct 9, 2025 at 9:39 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 09/10/2025 17:20, Lucas Zampieri wrote:
> > From: Charles Mirabile <cmirabil@redhat.com>
> >
> > Add a new compatible string for UltraRISC DP1000 PLIC.
> >
> > Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
> > ---
> >  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml        | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index 5b827bc24301..a419de50f5a8 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -74,6 +74,8 @@ properties:
> >                - sophgo,sg2044-plic
> >                - thead,th1520-plic
> >            - const: thead,c900-plic
> > +      - items:
>
>
> Missing SoC specific front compatible, me thinks.

Right, if I'm understanding this correctly, I would need to add the
sifive,plic-1.0.0 fallback compatible to indicate register layout
compatibility. However, the DP1000 PLIC has a claim register hardware
bug that breaks interrupt handling without the driver quirk. Should we
still include the fallback even though the generic driver doesn't
work?

>
>
> Best regards,
> Krzysztof
>

Best,
Lucas Zampieri

Re: [PATCH 1/3] dt-bindings: vendor-prefixes: add UltraRISC

[Rob Herring (Arm)]

On Thu, 09 Oct 2025 09:20:11 +0100, Lucas Zampieri wrote:
> Add vendor prefix for UltraRISC Technology Co., Ltd.
> 
> Signed-off-by: Lucas Zampieri <lzampier@redhat.com>
> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 2/3] dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC

[Vivian Wang]

On 10/10/25 21:57, Lucas Zampieri wrote:
> On Thu, Oct 9, 2025 at 9:39 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>> On 09/10/2025 17:20, Lucas Zampieri wrote:
>>> From: Charles Mirabile <cmirabil@redhat.com>
>>>
>>> Add a new compatible string for UltraRISC DP1000 PLIC.
>>>
>>> Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
>>> ---
>>>  .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml        | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>>> index 5b827bc24301..a419de50f5a8 100644
>>> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>>> @@ -74,6 +74,8 @@ properties:
>>>                - sophgo,sg2044-plic
>>>                - thead,th1520-plic
>>>            - const: thead,c900-plic
>>> +      - items:
>>
>> Missing SoC specific front compatible, me thinks.
> Right, if I'm understanding this correctly, I would need to add the
> sifive,plic-1.0.0 fallback compatible to indicate register layout
> compatibility. However, the DP1000 PLIC has a claim register hardware
> bug that breaks interrupt handling without the driver quirk. Should we
> still include the fallback even though the generic driver doesn't
> work?

See what the thead,c900-plic thing is doing. The PLIC compatible should
be SoC-associated model, and then CPU-core-associated model.

(I guess *theoretically* the PLIC could be external to the CPU but it
doesn't really make sense to design a core this way.)

Supposedly [1] the cores are called UR-CP100, so it should be

    compatible = "ultrarisc,dp1000-plic", "ultrarisc,cp100-plic";

And the driver should match on ultrarisc,cp100-plic instead.

Vivian "dramforever" Wang

[1]: https://ultrarisc.github.io/ultrarisc-devblog/2025/06/18/dp1000-spec/