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([2a02:810d:15c0:828:62f5:eb43:f726:5fee]) by smtp.gmail.com with ESMTPSA id q17-20020a1709066ad100b0094f6f45b2c1sm4240673ejs.156.2023.04.19.00.48.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Apr 2023 00:48:35 -0700 (PDT) Message-ID: <4e6469e5-0f6c-4150-4709-7459597f06cc@linaro.org> Date: Wed, 19 Apr 2023 09:48:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [RFC PATCH 2/2] arm64: dts: add support for C3 based Amlogic AW409 Content-Language: en-US To: =Xianwei Zhao , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski References: <20230419073834.972273-1-xianwei.zhao@amlogic.com> <20230419073834.972273-3-xianwei.zhao@amlogic.com> From: Krzysztof Kozlowski In-Reply-To: <20230419073834.972273-3-xianwei.zhao@amlogic.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/04/2023 09:38, =Xianwei Zhao wrote: > From: Xianwei Zhao > > Amlogic C3 is an advanced edge AI processor designed for smart IP camera > applications. > > Add basic support for the C3 based Amlogic AW409 board, which describes > the following components: CPU, GIC, IRQ, Timer, UART. It's capable of > booting up into the serial console. > > Signed-off-by: Xianwei Zhao > --- > arch/arm64/boot/dts/amlogic/Makefile | 1 + > .../amlogic/amlogic-c3-c302x-aw409-256m.dts | 30 +++++++ > arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 87 +++++++++++++++++++ > 3 files changed, 118 insertions(+) > create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts > create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi > > diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile > index cd1c5b04890a..d2b5d0d750bc 100644 > --- a/arch/arm64/boot/dts/amlogic/Makefile > +++ b/arch/arm64/boot/dts/amlogic/Makefile > @@ -74,3 +74,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb > dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb > dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb > dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb > +dtb-$(CONFIG_ARCH_AMLIPC) += amlogic-c3-c302x-aw409-256m.dtb > diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts > new file mode 100644 > index 000000000000..38ca98a32181 > --- /dev/null > +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts > @@ -0,0 +1,30 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. > + */ > + > +/dts-v1/; > + > +#include "amlogic-c3.dtsi" > + > +/ { > + model = "Amlogic C302 aw409 Development Board"; > + compatible = "amlogic,aw409", "amlogic,c3"; Undocumented compatibles. Run checkpatch and fix all warnings. Anyway, I am not sure this warrants separate architecture. Isn't C3 standard Meson SoC? > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart_B; > + }; > + > + memory@0 { > + device_type = "memory"; > + reg = <0x0 0x0 0x0 0x10000000>; > + }; > + Drop stray blank lines. > +}; > + > +&uart_B { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi > new file mode 100644 > index 000000000000..c69072ac57f5 > --- /dev/null > +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi > @@ -0,0 +1,87 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > + > +/ { > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a35"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + Everywhere... > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "xtal"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + gic: interrupt-controller@fff01000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x0 0xfff01000 0 0x1000>, > + <0x0 0xfff02000 0 0x2000>, > + <0x0 0xfff04000 0 0x2000>, > + <0x0 0xfff06000 0 0x2000>; > + interrupts = ; > + }; > + > + apb4: apb4@fe000000 { Node names should be generic. https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "simple-bus"; > + reg = <0x0 0xfe000000 0x0 0x480000>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; > + > + uart_B: serial@7a000 { lowercase for labels > + compatible = "amlogic,meson-g12a-uart"; So this is just meson? Drop new ARCH, no need for it. Anyway, you need SoC specific compatible. Best regards, Krzysztof