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Subject: Re: [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186
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To:     Ashish Mhetre <amhetre@nvidia.com>,
        Dmitry Osipenko <digetx@gmail.com>,
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On 3/22/22 20:34, Ashish Mhetre wrote:
>>> +     switch (status & mc->soc->int_channel_mask) {
>>> +     case BIT(0):
>>> +             *mc_channel = 0;
>>> +             break;
>>> +
>>> +     case BIT(1):
>>> +             *mc_channel = 1;
>>> +             break;
>>> +
>>> +     case BIT(2):
>>> +             *mc_channel = 2;
>>> +             break;
>>> +
>>> +     case BIT(3):
>>> +             *mc_channel = 3;
>>> +             break;
>>> +
>>> +     case BIT(24):
>>> +             *mc_channel = MC_BROADCAST_CHANNEL;
>>> +             break;
>>> +
>>> +     default:
>>> +             pr_err("Unknown interrupt source\n");
>>
>> dev_err_ratelimited("unknown interrupt channel 0x%08x\n", status) and
>> should be moved to the common interrupt handler.
>>
> So return just error from default case and handle error in common
> interrupt handler with this print, right? I'll update this in next
> version.

Yes, just move out the common print.

Although, you could parameterize the shift per SoC and then have a
common helper that does "status >> intmask_chan_shift", couldn't you?