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([2a02:810d:15c0:828:7ee2:e73e:802e:45c1]) by smtp.gmail.com with ESMTPSA id mb3-20020a170906eb0300b008e772c97db6sm8603741ejb.128.2023.03.09.02.31.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Mar 2023 02:31:48 -0800 (PST) Message-ID: <4eab53fc-2d26-dc93-3ae6-c0b2546ad3e0@linaro.org> Date: Thu, 9 Mar 2023 11:31:46 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [RFC PATCH v2 7/7] arm64: dts: qcom: Add the Inline Crypto Engine nodes Content-Language: en-US To: Abel Vesa , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Adrian Hunter , "James E . J . Bottomley" , "Martin K . Petersen" Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org References: <20230308155838.1094920-1-abel.vesa@linaro.org> <20230308155838.1094920-8-abel.vesa@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20230308155838.1094920-8-abel.vesa@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08/03/2023 16:58, Abel Vesa wrote: > Drop all properties related to ICE from every UFS and SDCC node, > for all platforms, and add dedicated ICE nodes for each platform. > On most platforms, there is only one ICE instance, used by either > UFS or SDCC, but there are some platforms that have two separate > instances and, therefore, two separate nodes are added. > > Signed-off-by: Abel Vesa > --- > > Changes since v1: > * Made changes for all platforms that use ICE, as a single patch since > most changes look really similar. > > arch/arm64/boot/dts/qcom/sdm630.dtsi | 18 +++++++++----- > arch/arm64/boot/dts/qcom/sdm670.dtsi | 15 +++++++---- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 21 +++++++++------- > arch/arm64/boot/dts/qcom/sm6115.dtsi | 37 +++++++++++++++++----------- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++--------- > arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++------- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++------- > 7 files changed, 102 insertions(+), 63 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi > index 5827cda270a0..2aed49104d9d 100644 > --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi > +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi > @@ -1330,9 +1330,8 @@ opp-200000000 { > sdhc_1: mmc@c0c4000 { > compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; > reg = <0x0c0c4000 0x1000>, > - <0x0c0c5000 0x1000>, > - <0x0c0c8000 0x8000>; > - reg-names = "hc", "cqhci", "ice"; > + <0x0c0c5000 0x1000>; > + reg-names = "hc", "cqhci"; I believe this will break the ICE on these platforms without valid reason. The commit msg does not explain why you do it or why this is necessary. We already we received comment that we keep breaking Qualcomm platforms all the time and need to keep them in some shape. Also, patchset is non-applicable in current set (breaks users) and neither commit nor cover letter mentions it. Best regards, Krzysztof