[PATCH 00/16] arm64: qcom: add sm8550-aim300 board support

[PATCH 00/16] arm64: qcom: add sm8550-aim300 board support

[Tengfei Fan]

Add sm8550-aim300 board support, and enable serial, UFS, USB, PCIe,
audio, LEDs, PMIC Volume, Power buttons, sound card and bluetooth
functions support on this board.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---

Tengfei Fan (16):
  dt-bindings: arm: qcom: add SM8550 AIM300
  dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm8550-pdc
  arm64: dts: qcom: sm8550: update Soundwire node name
  arm64: dts: qcom: sm8550: remove address/size-cells from pwm
  arm64: dts: qcom: sm8550: remove address/size-cells from mdss_dsi1
  arm64: dts: qcom: sm8550-aim300: add SM8550 AIM300
  arm64: dts: qcom: sm8550-aim300: add PCIe0
  arm64: dts: qcom: sm8550-aim300: add WCD9385 audio-codec
  arm64: dts: qcom: sm8550-aim300: add flash LEDs
  arm64: dts: qcom: sm8550-aim300: add display and panel
  arm64: dts: qcom: sm8550-aim300: add notification RGB LED
  arm64: dts: qcom: sm8550-aim300: enable PMIC Volume and Power buttons
  arm64: dts: qcom: sm8550-aim300: add WSA8845 speakers
  arm64: dts: qcom: sm8550-aim300: add sound card
  arm64: dts: qcom: sm8550-aim300: add pmic glink port/endpoints
  arm64: dts: qcom: sm8550-aim300: add bluetooth support

 .../devicetree/bindings/arm/qcom.yaml         |   1 +
 .../interrupt-controller/qcom,pdc.yaml        |   1 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 arch/arm64/boot/dts/qcom/pm8550.dtsi          |   2 -
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts    | 995 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi          |  11 +-
 6 files changed, 1002 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8550-aim300.dts


base-commit: eff99d8edbed7918317331ebd1e365d8e955d65e
-- 
2.17.1

[PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Tengfei Fan]

Add board compatible for SM8550 AIM300.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 88b84035e7b1..26aee6058bfd 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -1040,6 +1040,7 @@ properties:
 
       - items:
           - enum:
+              - qcom,sm8550-aim300
               - qcom,sm8550-mtp
               - qcom,sm8550-qrd
           - const: qcom,sm8550
-- 
2.17.1

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Add board compatible for SM8550 AIM300.

Subject, commit msg and compatible tell basically the same... and none
of them tell me what is AIM300.



Best regards,
Krzysztof

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Krzysztof Kozlowski]

On 17/11/2023 11:22, Krzysztof Kozlowski wrote:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Add board compatible for SM8550 AIM300.
> 
> Subject, commit msg and compatible tell basically the same... and none
> of them tell me what is AIM300.

Due to lack of explanation it is difficult to judge what's this. However
based on pieces of information I got, it looks like it is not a board,
so it is not suitable to be DTS, but DTSI. You still need a board...

Best regards,
Krzysztof

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Tengfei Fan]

在 11/20/2023 4:53 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:22, Krzysztof Kozlowski wrote:
>> On 17/11/2023 11:18, Tengfei Fan wrote:
>>> Add board compatible for SM8550 AIM300.
>>
>> Subject, commit msg and compatible tell basically the same... and none
>> of them tell me what is AIM300.
> 
> Due to lack of explanation it is difficult to judge what's this. However
> based on pieces of information I got, it looks like it is not a board,
> so it is not suitable to be DTS, but DTSI. You still need a board...
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
AIM (Artificial Intelligence Module). This hardware platform can be used 
to develop AI related software based on Qualcomm chipset. I also will 
update this message to patch commit message.

I also will sync with internal team about if we should create DTSI file 
as your suggestion.

The email update was delayed because I asked for a day off yesterday.

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Krzysztof Kozlowski]

On 21/11/2023 01:30, Tengfei Fan wrote:
> 
> 
> 在 11/20/2023 4:53 PM, Krzysztof Kozlowski 写道:
>> On 17/11/2023 11:22, Krzysztof Kozlowski wrote:
>>> On 17/11/2023 11:18, Tengfei Fan wrote:
>>>> Add board compatible for SM8550 AIM300.
>>>
>>> Subject, commit msg and compatible tell basically the same... and none
>>> of them tell me what is AIM300.
>>
>> Due to lack of explanation it is difficult to judge what's this. However
>> based on pieces of information I got, it looks like it is not a board,
>> so it is not suitable to be DTS, but DTSI. You still need a board...
>>
>> Best regards,
>> Krzysztof
>>
> 
> Hi Krzysztof,
> AIM (Artificial Intelligence Module). This hardware platform can be used 
> to develop AI related software based on Qualcomm chipset. I also will 
> update this message to patch commit message.

Does "Module" means it is physical module?

> 
> I also will sync with internal team about if we should create DTSI file 
> as your suggestion.

Do they know how DTS should be organized upstream (not downstream)?

Best regards,
Krzysztof

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Konrad Dybcio]

On 11/21/23 08:18, Krzysztof Kozlowski wrote:
> On 21/11/2023 01:30, Tengfei Fan wrote:
>>
>>
>> 在 11/20/2023 4:53 PM, Krzysztof Kozlowski 写道:
>>> On 17/11/2023 11:22, Krzysztof Kozlowski wrote:
>>>> On 17/11/2023 11:18, Tengfei Fan wrote:
>>>>> Add board compatible for SM8550 AIM300.
>>>>
>>>> Subject, commit msg and compatible tell basically the same... and none
>>>> of them tell me what is AIM300.
>>>
>>> Due to lack of explanation it is difficult to judge what's this. However
>>> based on pieces of information I got, it looks like it is not a board,
>>> so it is not suitable to be DTS, but DTSI. You still need a board...
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> Hi Krzysztof,
>> AIM (Artificial Intelligence Module). This hardware platform can be used
>> to develop AI related software based on Qualcomm chipset. I also will
>> update this message to patch commit message.
> 
> Does "Module" means it is physical module?
Moreover, does it have anything specific that makes it different from
a MTP/QRD/regular 8550 SoM?
In general, you can develop AI software on any computer, there are no
runtime checks for "AI" presence in the naming ;)

Or is it perhaps like QRB5165N [1], a base soc with what seems to
be a fat AI accelerator connected to it?

Konrad

[1] https://www.thundercomm.com/product/qualcomm-robotics-rb6-development-kit/#specifications

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Tengfei Fan]

在 11/23/2023 3:35 AM, Konrad Dybcio 写道:
> 
> 
> On 11/21/23 08:18, Krzysztof Kozlowski wrote:
>> On 21/11/2023 01:30, Tengfei Fan wrote:
>>>
>>>
>>> 在 11/20/2023 4:53 PM, Krzysztof Kozlowski 写道:
>>>> On 17/11/2023 11:22, Krzysztof Kozlowski wrote:
>>>>> On 17/11/2023 11:18, Tengfei Fan wrote:
>>>>>> Add board compatible for SM8550 AIM300.
>>>>>
>>>>> Subject, commit msg and compatible tell basically the same... and none
>>>>> of them tell me what is AIM300.
>>>>
>>>> Due to lack of explanation it is difficult to judge what's this. 
>>>> However
>>>> based on pieces of information I got, it looks like it is not a board,
>>>> so it is not suitable to be DTS, but DTSI. You still need a board...
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>> Hi Krzysztof,
>>> AIM (Artificial Intelligence Module). This hardware platform can be used
>>> to develop AI related software based on Qualcomm chipset. I also will
>>> update this message to patch commit message.
>>
>> Does "Module" means it is physical module?
Yes, AIM300 is a physical module.

> Moreover, does it have anything specific that makes it different from
> a MTP/QRD/regular 8550 SoM?
> In general, you can develop AI software on any computer, there are no
> runtime checks for "AI" presence in the naming ;)
> 
> Or is it perhaps like QRB5165N [1], a base soc with what seems to
> be a fat AI accelerator connected to it?

AIM300 is something like C5165N SOM.
AIM300 Series is a highly optimized family of modules designed to 
support AIoT applications, intergrated with qualcomm qcs8550 SOC inside. 
The Module is mounted onto Qualcomm AIoT carrier board to support 
verification, evaluation and development.

In next patch series, AIM300 AIoT carrier board will be a DTS, AIM300 
will be a DTSI, qcs8550 will be a DTSI.


> 
> Konrad
> 
> [1] 
> https://www.thundercomm.com/product/qualcomm-robotics-rb6-development-kit/#specifications


-- 
Thx and BRs,
Tengfei Fan

[1]
https://www.thundercomm.com/product/c5165n-som/

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Krzysztof Kozlowski]

On 24/11/2023 03:31, Tengfei Fan wrote:

>>>> AIM (Artificial Intelligence Module). This hardware platform can be used
>>>> to develop AI related software based on Qualcomm chipset. I also will
>>>> update this message to patch commit message.
>>>
>>> Does "Module" means it is physical module?
> Yes, AIM300 is a physical module.
> 
>> Moreover, does it have anything specific that makes it different from
>> a MTP/QRD/regular 8550 SoM?
>> In general, you can develop AI software on any computer, there are no
>> runtime checks for "AI" presence in the naming ;)
>>
>> Or is it perhaps like QRB5165N [1], a base soc with what seems to
>> be a fat AI accelerator connected to it?
> 
> AIM300 is something like C5165N SOM.
> AIM300 Series is a highly optimized family of modules designed to 
> support AIoT applications, intergrated with qualcomm qcs8550 SOC inside. 
> The Module is mounted onto Qualcomm AIoT carrier board to support 
> verification, evaluation and development.

Then you send patches for wrong board. AIM is not a board.
> 
> In next patch series, AIM300 AIoT carrier board will be a DTS, AIM300 
> will be a DTSI, qcs8550 will be a DTSI.


Best regards,
Krzysztof

Re: [PATCH 01/16] dt-bindings: arm: qcom: add SM8550 AIM300

[Tengfei Fan]

在 11/24/2023 3:47 PM, Krzysztof Kozlowski 写道:
> On 24/11/2023 03:31, Tengfei Fan wrote:
> 
>>>>> AIM (Artificial Intelligence Module). This hardware platform can be used
>>>>> to develop AI related software based on Qualcomm chipset. I also will
>>>>> update this message to patch commit message.
>>>>
>>>> Does "Module" means it is physical module?
>> Yes, AIM300 is a physical module.
>>
>>> Moreover, does it have anything specific that makes it different from
>>> a MTP/QRD/regular 8550 SoM?
>>> In general, you can develop AI software on any computer, there are no
>>> runtime checks for "AI" presence in the naming ;)
>>>
>>> Or is it perhaps like QRB5165N [1], a base soc with what seems to
>>> be a fat AI accelerator connected to it?
>>
>> AIM300 is something like C5165N SOM.
>> AIM300 Series is a highly optimized family of modules designed to
>> support AIoT applications, intergrated with qualcomm qcs8550 SOC inside.
>> The Module is mounted onto Qualcomm AIoT carrier board to support
>> verification, evaluation and development.
> 
> Then you send patches for wrong board. AIM is not a board.
Yes, I used AIM as board by mistake, AIM300 AIOT is board.
>>
>> In next patch series, AIM300 AIoT carrier board will be a DTS, AIM300
>> will be a DTSI, qcs8550 will be a DTSI.
> 
> 
> Best regards,
> Krzysztof
> 

-- 
Thx and BRs,
Tengfei Fan

[PATCH 02/16] dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm8550-pdc

[Tengfei Fan]

Add SM8550 PDC, already used in upstreamed DTS.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index 86d61896f591..8473afffce63 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -41,6 +41,7 @@ properties:
           - qcom,sm8250-pdc
           - qcom,sm8350-pdc
           - qcom,sm8450-pdc
+          - qcom,sm8550-pdc
       - const: qcom,pdc
 
   reg:
-- 
2.17.1

Re: [PATCH 02/16] dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm8550-pdc

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Add SM8550 PDC, already used in upstreamed DTS.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>

Guys, stop sending the duplicates:

https://lore.kernel.org/lkml/20230127132558.1176730-1-abel.vesa@linaro.org/


Best regards,
Krzysztof

Re: [PATCH 02/16] dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm8550-pdc

[Tengfei Fan]

在 11/17/2023 6:23 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Add SM8550 PDC, already used in upstreamed DTS.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> 
> Guys, stop sending the duplicates:
> 
> https://lore.kernel.org/lkml/20230127132558.1176730-1-abel.vesa@linaro.org/
> 
> 
> Best regards,
> Krzysztof
> 

Thanks Krzysztof remind kindly, I will check all the patches which may 
contain duplicates.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 03/16] arm64: dts: qcom: sm8550: update Soundwire node name

[Tengfei Fan]

Update Soundwire node name from "soundwire-controller" to "soundwire"
for avoid dtbs check warning.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 7bafb3d88d69..52e8f4c52426 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2055,7 +2055,7 @@
 			#sound-dai-cells = <1>;
 		};
 
-		swr3: soundwire-controller@6ab0000 {
+		swr3: soundwire@6ab0000 {
 			compatible = "qcom,soundwire-v2.0.0";
 			reg = <0 0x06ab0000 0 0x10000>;
 			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
@@ -2101,7 +2101,7 @@
 			#sound-dai-cells = <1>;
 		};
 
-		swr1: soundwire-controller@6ad0000 {
+		swr1: soundwire@6ad0000 {
 			compatible = "qcom,soundwire-v2.0.0";
 			reg = <0 0x06ad0000 0 0x10000>;
 			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
@@ -2166,7 +2166,7 @@
 			#sound-dai-cells = <1>;
 		};
 
-		swr0: soundwire-controller@6b10000 {
+		swr0: soundwire@6b10000 {
 			compatible = "qcom,soundwire-v2.0.0";
 			reg = <0 0x06b10000 0 0x10000>;
 			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
@@ -2193,7 +2193,7 @@
 			status = "disabled";
 		};
 
-		swr2: soundwire-controller@6d30000 {
+		swr2: soundwire@6d30000 {
 			compatible = "qcom,soundwire-v2.0.0";
 			reg = <0 0x06d30000 0 0x10000>;
 			interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.17.1

Re: [PATCH 03/16] arm64: dts: qcom: sm8550: update Soundwire node name

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Update Soundwire node name from "soundwire-controller" to "soundwire"
> for avoid dtbs check warning.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

I see PDC duplicated, now I see this patch as well, so you just repeated
everything which we did already?

Best regards,
Krzysztof

Re: [PATCH 03/16] arm64: dts: qcom: sm8550: update Soundwire node name

[Tengfei Fan]

在 11/17/2023 6:24 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Update Soundwire node name from "soundwire-controller" to "soundwire"
>> for avoid dtbs check warning.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++----
>>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> I see PDC duplicated, now I see this patch as well, so you just repeated
> everything which we did already?
> 
> Best regards,
> Krzysztof
> 


Thanks Krzysztof remind kindly, I will check upstream patch for getting 
this patch and I will do "depend on" on my new patch series.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 04/16] arm64: dts: qcom: sm8550: remove address/size-cells from pwm

[Tengfei Fan]

Address/size-cells will cause dtbs check warning, because pwm node have
not ranges and child also have not reg, so remove address/size-cells.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/pm8550.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi
index db3d5c17a77d..273fa13b3a5c 100644
--- a/arch/arm64/boot/dts/qcom/pm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi
@@ -65,8 +65,6 @@
 		pm8550_pwm: pwm {
 			compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm";
 
-			#address-cells = <1>;
-			#size-cells = <0>;
 			#pwm-cells = <2>;
 
 			status = "disabled";
-- 
2.17.1

Re: [PATCH 04/16] arm64: dts: qcom: sm8550: remove address/size-cells from pwm

[Dmitry Baryshkov]

On 17/11/2023 12:18, Tengfei Fan wrote:
> Address/size-cells will cause dtbs check warning, because pwm node have
> not ranges and child also have not reg, so remove address/size-cells.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/pm8550.dtsi | 2 --
>   1 file changed, 2 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


-- 
With best wishes
Dmitry

[PATCH 05/16] arm64: dts: qcom: sm8550: remove address/size-cells from mdss_dsi1

[Tengfei Fan]

Address/size-cells will cause dtbs check warning, because mdss_dsi1 node
have not ranges and child also have not reg, so remove address/size-cells.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 52e8f4c52426..4d3650ad5d87 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2771,9 +2771,6 @@
 				phys = <&mdss_dsi1_phy>;
 				phy-names = "dsi";
 
-				#address-cells = <1>;
-				#size-cells = <0>;
-
 				status = "disabled";
 
 				ports {
-- 
2.17.1

Re: [PATCH 05/16] arm64: dts: qcom: sm8550: remove address/size-cells from mdss_dsi1

[Dmitry Baryshkov]

On 17/11/2023 12:18, Tengfei Fan wrote:
> Address/size-cells will cause dtbs check warning, because mdss_dsi1 node
> have not ranges and child also have not reg, so remove address/size-cells.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ---
>   1 file changed, 3 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH 05/16] arm64: dts: qcom: sm8550: remove address/size-cells from mdss_dsi1

[Dmitry Baryshkov]

On 17/11/2023 12:24, Dmitry Baryshkov wrote:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Address/size-cells will cause dtbs check warning, because mdss_dsi1 node
>> have not ranges and child also have not reg, so remove 
>> address/size-cells.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ---
>>   1 file changed, 3 deletions(-)
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 

On the other hand, probably no.

Panels beneath the DSI node will have single cell of address and 0 size 
cells. So these propeties are correct.

-- 
With best wishes
Dmitry

[PATCH 06/16] arm64: dts: qcom: sm8550-aim300: add SM8550 AIM300

[Tengfei Fan]

Add a minimal DTS for the new QRD8550 board, serial, UFS and USB should
be working.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile          |   1 +
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 490 +++++++++++++++++++++
 2 files changed, 491 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8550-aim300.dts

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index d6cb840b7050..ea5d4a07671a 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -229,5 +229,6 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-hdk.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-qrd.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-sony-xperia-nagara-pdx223.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-sony-xperia-nagara-pdx224.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm8550-aim300.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-mtp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-qrd.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
new file mode 100644
index 000000000000..202b979da8ca
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8550.dtsi"
+#include "pm8010.dtsi"
+#include "pm8550.dtsi"
+#include "pm8550b.dtsi"
+#include "pm8550ve.dtsi"
+#include "pm8550vs.dtsi"
+#include "pmk8550.dtsi"
+#include "pmr735d_a.dtsi"
+#include "pmr735d_b.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SM8550 AIM300";
+	compatible = "qcom,sm8550-aim300", "qcom,sm8550";
+
+	aliases {
+		serial0 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	pmic-glink {
+		compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
+
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_hs_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_ss>;
+					};
+				};
+			};
+		};
+	};
+
+	vph_pwr: vph-pwr-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s4g_1p25>;
+		vdd-l12-supply = <&vreg_s6g_1p86>;
+		vdd-l15-supply = <&vreg_s6g_1p86>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3296000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2720000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1b_1p8: ldo1 {
+			regulator-name = "vreg_l1b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3104000>;
+			regulator-max-microvolt = <3104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p2: ldo11 {
+			regulator-name = "vreg_l11b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s4g_1p25>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+
+		vreg_l3c_0p9: ldo3 {
+			regulator-name = "vreg_l3c_0p9";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+
+		vreg_l1d_0p88: ldo1 {
+			regulator-name = "vreg_l1d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		vreg_s4e_0p95: smps4 {
+			regulator-name = "vreg_s4e_0p95";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5e_1p08: smps5 {
+			regulator-name = "vreg_s5e_1p08";
+			regulator-min-microvolt = <1080000>;
+			regulator-max-microvolt = <1120000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1e_0p88: ldo1 {
+			regulator-name = "vreg_l1e_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2e_0p9: ldo2 {
+			regulator-name = "vreg_l2e_0p9";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <970000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s4f_0p5: smps4 {
+			regulator-name = "vreg_s4f_0p5";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_0p9: ldo1 {
+			regulator-name = "vreg_l1f_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_0p88: ldo2 {
+			regulator-name = "vreg_l2f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_0p88: ldo3 {
+			regulator-name = "vreg_l3f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "g";
+		vdd-l1-supply = <&vreg_s4g_1p25>;
+		vdd-l2-supply = <&vreg_s4g_1p25>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+
+		vreg_s1g_1p25: smps1 {
+			regulator-name = "vreg_s1g_1p25";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2g_0p85: smps2 {
+			regulator-name = "vreg_s2g_0p85";
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3g_0p8: smps3 {
+			regulator-name = "vreg_s3g_0p8";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <1004000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4g_1p25: smps4 {
+			regulator-name = "vreg_s4g_1p25";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1352000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5g_0p85: smps5 {
+			regulator-name = "vreg_s5g_0p85";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1004000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s6g_1p86: smps6 {
+			regulator-name = "vreg_s6g_1p86";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1g_1p2: ldo1 {
+			regulator-name = "vreg_l1g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+
+		vreg_l3g_1p2: ldo3 {
+			regulator-name = "vreg_l3g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&pm8550b_eusb2_repeater {
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sm8550/adsp.mbn",
+			"qcom/sm8550/adsp_dtb.mbn";
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/sm8550/cdsp.mbn",
+			"qcom/sm8550/cdsp_dtb.mbn";
+	status = "okay";
+};
+
+&remoteproc_mpss {
+	firmware-name = "qcom/sm8550/modem.mbn",
+			"qcom/sm8550/modem_dtb.mbn";
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&tlmm {
+	gpio-reserved-ranges = <32 8>;
+};
+
+&uart7 {
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l17b_2p5>;
+	vcc-max-microamp = <1300000>;
+	vccq-supply = <&vreg_l1g_1p2>;
+	vccq-max-microamp = <1200000>;
+	vdd-hba-supply = <&vreg_l3g_1p2>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l1d_0p88>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3 {
+	dr_mode = "otg";
+	usb-role-switch;
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_dwc3_ss {
+	remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
+};
+
+&usb_1_hsphy {
+	phys = <&pm8550b_eusb2_repeater>;
+
+	vdd-supply = <&vreg_l1e_0p88>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3f_0p88>;
+
+	orientation-switch;
+
+	status = "okay";
+};
+
+&xo_board {
+	clock-frequency = <76800000>;
+};
-- 
2.17.1

Re: [PATCH 06/16] arm64: dts: qcom: sm8550-aim300: add SM8550 AIM300

[Dmitry Baryshkov]

On 17/11/2023 12:18, Tengfei Fan wrote:
> Add a minimal DTS for the new QRD8550 board, serial, UFS and USB should
> be working.

An explanation of what is AIM300 would be welcomed.

> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/Makefile          |   1 +
>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 490 +++++++++++++++++++++
>   2 files changed, 491 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index d6cb840b7050..ea5d4a07671a 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -229,5 +229,6 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-hdk.dtb
>   dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-qrd.dtb
>   dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-sony-xperia-nagara-pdx223.dtb
>   dtb-$(CONFIG_ARCH_QCOM)	+= sm8450-sony-xperia-nagara-pdx224.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8550-aim300.dtb

My email client suggests that alignment is broken here.

>   dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-mtp.dtb
>   dtb-$(CONFIG_ARCH_QCOM)	+= sm8550-qrd.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> new file mode 100644
> index 000000000000..202b979da8ca
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> @@ -0,0 +1,490 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include "sm8550.dtsi"
> +#include "pm8010.dtsi"
> +#include "pm8550.dtsi"
> +#include "pm8550b.dtsi"
> +#include "pm8550ve.dtsi"
> +#include "pm8550vs.dtsi"
> +#include "pmk8550.dtsi"
> +#include "pmr735d_a.dtsi"
> +#include "pmr735d_b.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. SM8550 AIM300";
> +	compatible = "qcom,sm8550-aim300", "qcom,sm8550";
> +
> +	aliases {
> +		serial0 = &uart7;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	pmic-glink {
> +		compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
> +
> +		connector@0 {
> +			compatible = "usb-c-connector";
> +			reg = <0>;
> +			power-role = "dual";
> +			data-role = "dual";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +
> +					pmic_glink_hs_in: endpoint {
> +						remote-endpoint = <&usb_1_dwc3_hs>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					pmic_glink_ss_in: endpoint {
> +						remote-endpoint = <&usb_1_dwc3_ss>;
> +					};
> +				};
> +			};
> +		};
> +	};
> +
> +	vph_pwr: vph-pwr-regulator {

It's not demanded, I think, but I'd suggest 'regulator-vph-pwr' to allow 
all regulators to be grouped together.

> +		compatible = "regulator-fixed";
> +		regulator-name = "vph_pwr";
> +		regulator-min-microvolt = <3700000>;
> +		regulator-max-microvolt = <3700000>;
> +
> +		regulator-always-on;
> +		regulator-boot-on;
> +	};
> +};

Other than that looks good to me.

-- 
With best wishes
Dmitry

Re: [PATCH 06/16] arm64: dts: qcom: sm8550-aim300: add SM8550 AIM300

[Tengfei Fan]

在 11/17/2023 6:28 PM, Dmitry Baryshkov 写道:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Add a minimal DTS for the new QRD8550 board, serial, UFS and USB should
>> be working.
> 
> An explanation of what is AIM300 would be welcomed.
> 
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile          |   1 +
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 490 +++++++++++++++++++++
>>   2 files changed, 491 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile 
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index d6cb840b7050..ea5d4a07671a 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -229,5 +229,6 @@ dtb-$(CONFIG_ARCH_QCOM)    += sm8450-hdk.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8450-qrd.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8450-sony-xperia-nagara-pdx223.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8450-sony-xperia-nagara-pdx224.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sm8550-aim300.dtb
> 
> My email client suggests that alignment is broken here.
I checked the code after apply this patch, and find this code alignment 
have not issue, so I will check if have some format issue when I do this 
patch.
> 
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8550-mtp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8550-qrd.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts 
>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> new file mode 100644
>> index 000000000000..202b979da8ca
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -0,0 +1,490 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights 
>> reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> +#include "sm8550.dtsi"
>> +#include "pm8010.dtsi"
>> +#include "pm8550.dtsi"
>> +#include "pm8550b.dtsi"
>> +#include "pm8550ve.dtsi"
>> +#include "pm8550vs.dtsi"
>> +#include "pmk8550.dtsi"
>> +#include "pmr735d_a.dtsi"
>> +#include "pmr735d_b.dtsi"
>> +
>> +/ {
>> +    model = "Qualcomm Technologies, Inc. SM8550 AIM300";
>> +    compatible = "qcom,sm8550-aim300", "qcom,sm8550";
>> +
>> +    aliases {
>> +        serial0 = &uart7;
>> +    };
>> +
>> +    chosen {
>> +        stdout-path = "serial0:115200n8";
>> +    };
>> +
>> +    pmic-glink {
>> +        compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
>> +
>> +        connector@0 {
>> +            compatible = "usb-c-connector";
>> +            reg = <0>;
>> +            power-role = "dual";
>> +            data-role = "dual";
>> +
>> +            ports {
>> +                #address-cells = <1>;
>> +                #size-cells = <0>;
>> +
>> +                port@0 {
>> +                    reg = <0>;
>> +
>> +                    pmic_glink_hs_in: endpoint {
>> +                        remote-endpoint = <&usb_1_dwc3_hs>;
>> +                    };
>> +                };
>> +
>> +                port@1 {
>> +                    reg = <1>;
>> +
>> +                    pmic_glink_ss_in: endpoint {
>> +                        remote-endpoint = <&usb_1_dwc3_ss>;
>> +                    };
>> +                };
>> +            };
>> +        };
>> +    };
>> +
>> +    vph_pwr: vph-pwr-regulator {
> 
> It's not demanded, I think, but I'd suggest 'regulator-vph-pwr' to allow 
> all regulators to be grouped together.
Thanks this comments, I will sync your comments with internal team, then 
I will update sync result to you.
> 
>> +        compatible = "regulator-fixed";
>> +        regulator-name = "vph_pwr";
>> +        regulator-min-microvolt = <3700000>;
>> +        regulator-max-microvolt = <3700000>;
>> +
>> +        regulator-always-on;
>> +        regulator-boot-on;
>> +    };
>> +};
> 
> Other than that looks good to me.
> 

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH 06/16] arm64: dts: qcom: sm8550-aim300: add SM8550 AIM300

[Tengfei Fan]

在 11/17/2023 6:28 PM, Dmitry Baryshkov 写道:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Add a minimal DTS for the new QRD8550 board, serial, UFS and USB should
>> be working.
> 
> An explanation of what is AIM300 would be welcomed.
> 
Hi Dmitry,
AIM means Artificial Intelligence Module. This hardware platform can be 
used to develop AI related software based on Qualcomm chipset.
I will also update the explanation of AIM to the new patch series.

>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile          |   1 +
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 490 +++++++++++++++++++++
>>   2 files changed, 491 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile 
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index d6cb840b7050..ea5d4a07671a 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -229,5 +229,6 @@ dtb-$(CONFIG_ARCH_QCOM)    += sm8450-hdk.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8450-qrd.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8450-sony-xperia-nagara-pdx223.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8450-sony-xperia-nagara-pdx224.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += sm8550-aim300.dtb
> 
> My email client suggests that alignment is broken here.
> 
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8550-mtp.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)    += sm8550-qrd.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts 
>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> new file mode 100644
>> index 000000000000..202b979da8ca
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -0,0 +1,490 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights 
>> reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> +#include "sm8550.dtsi"
>> +#include "pm8010.dtsi"
>> +#include "pm8550.dtsi"
>> +#include "pm8550b.dtsi"
>> +#include "pm8550ve.dtsi"
>> +#include "pm8550vs.dtsi"
>> +#include "pmk8550.dtsi"
>> +#include "pmr735d_a.dtsi"
>> +#include "pmr735d_b.dtsi"
>> +
>> +/ {
>> +    model = "Qualcomm Technologies, Inc. SM8550 AIM300";
>> +    compatible = "qcom,sm8550-aim300", "qcom,sm8550";
>> +
>> +    aliases {
>> +        serial0 = &uart7;
>> +    };
>> +
>> +    chosen {
>> +        stdout-path = "serial0:115200n8";
>> +    };
>> +
>> +    pmic-glink {
>> +        compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
>> +
>> +        connector@0 {
>> +            compatible = "usb-c-connector";
>> +            reg = <0>;
>> +            power-role = "dual";
>> +            data-role = "dual";
>> +
>> +            ports {
>> +                #address-cells = <1>;
>> +                #size-cells = <0>;
>> +
>> +                port@0 {
>> +                    reg = <0>;
>> +
>> +                    pmic_glink_hs_in: endpoint {
>> +                        remote-endpoint = <&usb_1_dwc3_hs>;
>> +                    };
>> +                };
>> +
>> +                port@1 {
>> +                    reg = <1>;
>> +
>> +                    pmic_glink_ss_in: endpoint {
>> +                        remote-endpoint = <&usb_1_dwc3_ss>;
>> +                    };
>> +                };
>> +            };
>> +        };
>> +    };
>> +
>> +    vph_pwr: vph-pwr-regulator {
> 
> It's not demanded, I think, but I'd suggest 'regulator-vph-pwr' to allow 
> all regulators to be grouped together.
> 
>> +        compatible = "regulator-fixed";
>> +        regulator-name = "vph_pwr";
>> +        regulator-min-microvolt = <3700000>;
>> +        regulator-max-microvolt = <3700000>;
>> +
>> +        regulator-always-on;
>> +        regulator-boot-on;
>> +    };
>> +};
> 
> Other than that looks good to me.
> 

-- 
Thx and BRs,
Tengfei Fan

[PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Tengfei Fan]

Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
thus skip pcie_1_phy_aux_clk input clock to GCC.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index 202b979da8ca..3aca0a433a00 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -393,6 +393,38 @@
 	};
 };
 
+&gcc {
+	clocks = <&bi_tcxo_div2>, <&sleep_clk>,
+		 <&pcie0_phy>,
+		 <&pcie1_phy>,
+		 <0>,
+		 <&ufs_mem_phy 0>,
+		 <&ufs_mem_phy 1>,
+		 <&ufs_mem_phy 2>,
+		 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+};
+
+&pcie_1_phy_aux_clk {
+	status = "disabled";
+};
+
+&pcie0 {
+	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l1e_0p88>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
 &pm8550b_eusb2_repeater {
 	vdd18-supply = <&vreg_l15b_1p8>;
 	vdd3-supply = <&vreg_l5b_3p1>;
-- 
2.17.1

Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Dmitry Baryshkov]

On 17/11/2023 12:18, Tengfei Fan wrote:
> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
> thus skip pcie_1_phy_aux_clk input clock to GCC.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> index 202b979da8ca..3aca0a433a00 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> @@ -393,6 +393,38 @@
>   	};
>   };
>   
> +&gcc {
> +	clocks = <&bi_tcxo_div2>, <&sleep_clk>,
> +		 <&pcie0_phy>,
> +		 <&pcie1_phy>,
> +		 <0>,
> +		 <&ufs_mem_phy 0>,
> +		 <&ufs_mem_phy 1>,
> +		 <&ufs_mem_phy 2>,
> +		 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> +};

NAK, this should go to sm8550.dtsi unless there is a good reason.

> +
> +&pcie_1_phy_aux_clk {
> +	status = "disabled";
> +};
> +
> +&pcie0 {
> +	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
> +
> +	pinctrl-0 = <&pcie0_default_state>;
> +	pinctrl-names = "default";
> +
> +	status = "okay";
> +};
> +
> +&pcie0_phy {
> +	vdda-phy-supply = <&vreg_l1e_0p88>;
> +	vdda-pll-supply = <&vreg_l3e_1p2>;
> +
> +	status = "okay";
> +};
> +
>   &pm8550b_eusb2_repeater {
>   	vdd18-supply = <&vreg_l15b_1p8>;
>   	vdd3-supply = <&vreg_l5b_3p1>;

-- 
With best wishes
Dmitry

Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[neil.armstrong]

On 17/11/2023 11:29, Dmitry Baryshkov wrote:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
>> thus skip pcie_1_phy_aux_clk input clock to GCC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> index 202b979da8ca..3aca0a433a00 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -393,6 +393,38 @@
>>       };
>>   };
>> +&gcc {
>> +    clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>> +         <&pcie0_phy>,
>> +         <&pcie1_phy>,
>> +         <0>,
>> +         <&ufs_mem_phy 0>,
>> +         <&ufs_mem_phy 1>,
>> +         <&ufs_mem_phy 2>,
>> +         <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>> +};
> 
> NAK, this should go to sm8550.dtsi unless there is a good reason.

Actually this is how QRD8550 was designed, so it's fine to mimic.

Neil

> 
>> +
>> +&pcie_1_phy_aux_clk {
>> +    status = "disabled";
>> +};
>> +
>> +&pcie0 {
>> +    perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
>> +    wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
>> +
>> +    pinctrl-0 = <&pcie0_default_state>;
>> +    pinctrl-names = "default";
>> +
>> +    status = "okay";
>> +};
>> +
>> +&pcie0_phy {
>> +    vdda-phy-supply = <&vreg_l1e_0p88>;
>> +    vdda-pll-supply = <&vreg_l3e_1p2>;
>> +
>> +    status = "okay";
>> +};
>> +
>>   &pm8550b_eusb2_repeater {
>>       vdd18-supply = <&vreg_l15b_1p8>;
>>       vdd3-supply = <&vreg_l5b_3p1>;
> 

Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Konrad Dybcio]

On 17.11.2023 11:41, neil.armstrong@linaro.org wrote:
> On 17/11/2023 11:29, Dmitry Baryshkov wrote:
>> On 17/11/2023 12:18, Tengfei Fan wrote:
>>> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
>>> thus skip pcie_1_phy_aux_clk input clock to GCC.
>>>
>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++
>>>   1 file changed, 32 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>> index 202b979da8ca..3aca0a433a00 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>> @@ -393,6 +393,38 @@
>>>       };
>>>   };
>>> +&gcc {
>>> +    clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>>> +         <&pcie0_phy>,
>>> +         <&pcie1_phy>,
>>> +         <0>,
>>> +         <&ufs_mem_phy 0>,
>>> +         <&ufs_mem_phy 1>,
>>> +         <&ufs_mem_phy 2>,
>>> +         <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>>> +};
>>
>> NAK, this should go to sm8550.dtsi unless there is a good reason.
> 
> Actually this is how QRD8550 was designed, so it's fine to mimic.
Does CCF not handle this gracefully?

Konrad

Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Neil Armstrong]

Le 18/11/2023 à 01:08, Konrad Dybcio a écrit :
> On 17.11.2023 11:41, neil.armstrong@linaro.org wrote:
>> On 17/11/2023 11:29, Dmitry Baryshkov wrote:
>>> On 17/11/2023 12:18, Tengfei Fan wrote:
>>>> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
>>>> thus skip pcie_1_phy_aux_clk input clock to GCC.
>>>>
>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++
>>>>    1 file changed, 32 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>> index 202b979da8ca..3aca0a433a00 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>> @@ -393,6 +393,38 @@
>>>>        };
>>>>    };
>>>> +&gcc {
>>>> +    clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>>>> +         <&pcie0_phy>,
>>>> +         <&pcie1_phy>,
>>>> +         <0>,
>>>> +         <&ufs_mem_phy 0>,
>>>> +         <&ufs_mem_phy 1>,
>>>> +         <&ufs_mem_phy 2>,
>>>> +         <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>>>> +};
>>>
>>> NAK, this should go to sm8550.dtsi unless there is a good reason.
>>
>> Actually this is how QRD8550 was designed, so it's fine to mimic.
> Does CCF not handle this gracefully?

CCF handles this very gracefully and it's a perfectly valid DT in regard
to the bindings...

neil

> 
> Konrad

Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Tengfei Fan]

在 11/20/2023 1:59 AM, Neil Armstrong 写道:
> Le 18/11/2023 à 01:08, Konrad Dybcio a écrit :
>> On 17.11.2023 11:41, neil.armstrong@linaro.org wrote:
>>> On 17/11/2023 11:29, Dmitry Baryshkov wrote:
>>>> On 17/11/2023 12:18, Tengfei Fan wrote:
>>>>> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
>>>>> thus skip pcie_1_phy_aux_clk input clock to GCC.
>>>>>
>>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>>> ---
>>>>>    arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 
>>>>> ++++++++++++++++++++++
>>>>>    1 file changed, 32 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts 
>>>>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>>> index 202b979da8ca..3aca0a433a00 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>>> @@ -393,6 +393,38 @@
>>>>>        };
>>>>>    };
>>>>> +&gcc {
>>>>> +    clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>>>>> +         <&pcie0_phy>,
>>>>> +         <&pcie1_phy>,
>>>>> +         <0>,
>>>>> +         <&ufs_mem_phy 0>,
>>>>> +         <&ufs_mem_phy 1>,
>>>>> +         <&ufs_mem_phy 2>,
>>>>> +         <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>>>>> +};
>>>>
>>>> NAK, this should go to sm8550.dtsi unless there is a good reason.
>>>
>>> Actually this is how QRD8550 was designed, so it's fine to mimic.
>> Does CCF not handle this gracefully?
> 
> CCF handles this very gracefully and it's a perfectly valid DT in regard
> to the bindings...
> 
> neil
> 
>>
>> Konrad
> 
Thanks Konrad and Neil comments and disscusion this patch, I also will 
confirm this with internal team.

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
> thus skip pcie_1_phy_aux_clk input clock to GCC.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>

You just added this board. Does it mean you added incomplete and wrong DTSU?

Best regards,
Krzysztof

Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Tengfei Fan]

在 11/17/2023 6:30 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
>> thus skip pcie_1_phy_aux_clk input clock to GCC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> 
> You just added this board. Does it mean you added incomplete and wrong DTSU?
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
I will drop PCIe1 setting in dts file because of PCIe1 still have not 
enable in dts file.
Another I understand what your comments means is I should combine all 
the functions which should be implemented together and submit as a 
complete patch, right?
I will combine all the functions patch to a total patch when I do next 
version patch series, because there is another your comments also want 
to me do as so.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 08/16] arm64: dts: qcom: sm8550-aim300: add WCD9385 audio-codec

[Tengfei Fan]

Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX
and TX.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 57 ++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index 3aca0a433a00..6a9b384c4e08 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -24,6 +24,33 @@
 		serial0 = &uart7;
 	};
 
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9385-codec";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&wcd_default>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000
+							  500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 108 GPIO_ACTIVE_LOW>;
+
+		#sound-dai-cells = <1>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+	};
+
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
@@ -456,8 +483,38 @@
 	clock-frequency = <32000>;
 };
 
+&swr1 {
+	status = "okay";
+
+	/* WCD9385 RX */
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	/* WCD9385 TX */
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <1 1 2 3>;
+	};
+};
+
 &tlmm {
 	gpio-reserved-ranges = <32 8>;
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio108";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
 };
 
 &uart7 {
-- 
2.17.1

Re: [PATCH 08/16] arm64: dts: qcom: sm8550-aim300: add WCD9385 audio-codec

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX
> and TX.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>

You just added this board. Does it mean you added incomplete and wrong DTS?

Best regards,
Krzysztof

Re: [PATCH 08/16] arm64: dts: qcom: sm8550-aim300: add WCD9385 audio-codec

[Tengfei Fan]

在 11/17/2023 6:31 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Add Qualcomm Aqstic WCD9385 audio codec on two Soundwire interfaces: RX
>> and TX.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> 
> You just added this board. Does it mean you added incomplete and wrong DTS?
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I will do a board patch which contain all 
the functions which were splited in current patch series.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 09/16] arm64: dts: qcom: sm8550-aim300: add flash LEDs

[Tengfei Fan]

Enable PM8550 PMIC flash LED controller and add two flash LEDs using
four current outputs.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 25 ++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index 6a9b384c4e08..cafddc02aef0 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sm8550.dtsi"
 #include "pm8010.dtsi"
@@ -452,6 +453,30 @@
 	status = "okay";
 };
 
+&pm8550_flash {
+	status = "okay";
+
+	led-0 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_YELLOW>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <0>;
+		led-sources = <1>, <4>;
+		led-max-microamp = <500000>;
+	};
+
+	led-1 {
+		function = LED_FUNCTION_FLASH;
+		color = <LED_COLOR_ID_WHITE>;
+		flash-max-microamp = <2000000>;
+		flash-max-timeout-us = <1280000>;
+		function-enumerator = <1>;
+		led-sources = <2>, <3>;
+		led-max-microamp = <500000>;
+	};
+};
+
 &pm8550b_eusb2_repeater {
 	vdd18-supply = <&vreg_l15b_1p8>;
 	vdd3-supply = <&vreg_l5b_3p1>;
-- 
2.17.1

Re: [PATCH 09/16] arm64: dts: qcom: sm8550-aim300: add flash LEDs

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Enable PM8550 PMIC flash LED controller and add two flash LEDs using
> four current outputs.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---

NAK, it's initial submission.

Stop useless splitting of work which is done. You cannot have "release
late, release often". The rule is: "release early, release often".

Or you want to split DTS per each line?

Best regards,
Krzysztof

Re: [PATCH 09/16] arm64: dts: qcom: sm8550-aim300: add flash LEDs

[Tengfei Fan]

在 11/17/2023 6:34 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Enable PM8550 PMIC flash LED controller and add two flash LEDs using
>> four current outputs.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> 
> NAK, it's initial submission.
> 
> Stop useless splitting of work which is done. You cannot have "release
> late, release often". The rule is: "release early, release often".
> 
> Or you want to split DTS per each line?
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I will do a board patch which contain all 
the functions which were splited in current patch series.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 10/16] arm64: dts: qcom: sm8550-aim300: add display and panel

[Tengfei Fan]

Enable Display Subsystem with Visionox VTDR6130 Panel.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 68 ++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index cafddc02aef0..9b568ae9581e 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -432,6 +432,46 @@
 		 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&vreg_l3e_1p2>;
+	status = "okay";
+
+	panel@0 {
+		compatible = "visionox,vtdr6130";
+		reg = <0>;
+
+		pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
+		pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
+		pinctrl-names = "default", "sleep";
+
+		reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
+
+		vci-supply = <&vreg_l13b_3p0>;
+		vdd-supply = <&vreg_l11b_1p2>;
+		vddio-supply = <&vreg_l12b_1p8>;
+
+		port {
+			panel0_in: endpoint {
+				remote-endpoint = <&mdss_dsi0_out>;
+			};
+		};
+	};
+};
+
+&mdss_dsi0_out {
+	remote-endpoint = <&panel0_in>;
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+	vdds-supply = <&vreg_l1e_0p88>;
+	status = "okay";
+};
+
 &pcie_1_phy_aux_clk {
 	status = "disabled";
 };
@@ -533,6 +573,34 @@
 &tlmm {
 	gpio-reserved-ranges = <32 8>;
 
+	sde_dsi_active: sde-dsi-active-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	sde_dsi_suspend: sde-dsi-suspend-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_active: sde-te-active-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_suspend: sde-te-suspend-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
 	wcd_default: wcd-reset-n-active-state {
 		pins = "gpio108";
 		function = "gpio";
-- 
2.17.1

Re: [PATCH 10/16] arm64: dts: qcom: sm8550-aim300: add display and panel

[Dmitry Baryshkov]

On 17/11/2023 12:18, Tengfei Fan wrote:
> Enable Display Subsystem with Visionox VTDR6130 Panel.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 68 ++++++++++++++++++++++
>   1 file changed, 68 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> index cafddc02aef0..9b568ae9581e 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> @@ -432,6 +432,46 @@
>   		 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>   };
>   
> +&mdss {
> +	status = "okay";
> +};
> +
> +&mdss_dsi0 {
> +	vdda-supply = <&vreg_l3e_1p2>;
> +	status = "okay";
> +
> +	panel@0 {
> +		compatible = "visionox,vtdr6130";
> +		reg = <0>;
> +
> +		pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
> +		pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
> +		pinctrl-names = "default", "sleep";
> +
> +		reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
> +
> +		vci-supply = <&vreg_l13b_3p0>;
> +		vdd-supply = <&vreg_l11b_1p2>;
> +		vddio-supply = <&vreg_l12b_1p8>;
> +
> +		port {
> +			panel0_in: endpoint {
> +				remote-endpoint = <&mdss_dsi0_out>;
> +			};
> +		};
> +	};
> +};
> +
> +&mdss_dsi0_out {
> +	remote-endpoint = <&panel0_in>;
> +	data-lanes = <0 1 2 3>;
> +};
> +
> +&mdss_dsi0_phy {
> +	vdds-supply = <&vreg_l1e_0p88>;
> +	status = "okay";
> +};
> +
>   &pcie_1_phy_aux_clk {
>   	status = "disabled";
>   };
> @@ -533,6 +573,34 @@
>   &tlmm {
>   	gpio-reserved-ranges = <32 8>;
>   
> +	sde_dsi_active: sde-dsi-active-state {

sde is the name from the other kernel branch. Drop it please. Just 'dsi' 
is enough.

> +		pins = "gpio133";
> +		function = "gpio";
> +		drive-strength = <8>;
> +		bias-disable;
> +	};
> +
> +	sde_dsi_suspend: sde-dsi-suspend-state {
> +		pins = "gpio133";
> +		function = "gpio";
> +		drive-strength = <2>;
> +		bias-pull-down;
> +	};
> +
> +	sde_te_active: sde-te-active-state {
> +		pins = "gpio86";
> +		function = "mdp_vsync";
> +		drive-strength = <2>;
> +		bias-pull-down;
> +	};
> +
> +	sde_te_suspend: sde-te-suspend-state {
> +		pins = "gpio86";
> +		function = "mdp_vsync";
> +		drive-strength = <2>;
> +		bias-pull-down;
> +	};
> +
>   	wcd_default: wcd-reset-n-active-state {
>   		pins = "gpio108";
>   		function = "gpio";

-- 
With best wishes
Dmitry

Re: [PATCH 10/16] arm64: dts: qcom: sm8550-aim300: add display and panel

[Tengfei Fan]

在 11/17/2023 6:30 PM, Dmitry Baryshkov 写道:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Enable Display Subsystem with Visionox VTDR6130 Panel.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 68 ++++++++++++++++++++++
>>   1 file changed, 68 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts 
>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> index cafddc02aef0..9b568ae9581e 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -432,6 +432,46 @@
>>            <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>>   };
>> +&mdss {
>> +    status = "okay";
>> +};
>> +
>> +&mdss_dsi0 {
>> +    vdda-supply = <&vreg_l3e_1p2>;
>> +    status = "okay";
>> +
>> +    panel@0 {
>> +        compatible = "visionox,vtdr6130";
>> +        reg = <0>;
>> +
>> +        pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
>> +        pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
>> +        pinctrl-names = "default", "sleep";
>> +
>> +        reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
>> +
>> +        vci-supply = <&vreg_l13b_3p0>;
>> +        vdd-supply = <&vreg_l11b_1p2>;
>> +        vddio-supply = <&vreg_l12b_1p8>;
>> +
>> +        port {
>> +            panel0_in: endpoint {
>> +                remote-endpoint = <&mdss_dsi0_out>;
>> +            };
>> +        };
>> +    };
>> +};
>> +
>> +&mdss_dsi0_out {
>> +    remote-endpoint = <&panel0_in>;
>> +    data-lanes = <0 1 2 3>;
>> +};
>> +
>> +&mdss_dsi0_phy {
>> +    vdds-supply = <&vreg_l1e_0p88>;
>> +    status = "okay";
>> +};
>> +
>>   &pcie_1_phy_aux_clk {
>>       status = "disabled";
>>   };
>> @@ -533,6 +573,34 @@
>>   &tlmm {
>>       gpio-reserved-ranges = <32 8>;
>> +    sde_dsi_active: sde-dsi-active-state {
> 
> sde is the name from the other kernel branch. Drop it please. Just 'dsi' 
> is enough.
sure, I wil drop sde in next new version patch series.
> 
>> +        pins = "gpio133";
>> +        function = "gpio";
>> +        drive-strength = <8>;
>> +        bias-disable;
>> +    };
>> +
>> +    sde_dsi_suspend: sde-dsi-suspend-state {
>> +        pins = "gpio133";
>> +        function = "gpio";
>> +        drive-strength = <2>;
>> +        bias-pull-down;
>> +    };
>> +
>> +    sde_te_active: sde-te-active-state {
>> +        pins = "gpio86";
>> +        function = "mdp_vsync";
>> +        drive-strength = <2>;
>> +        bias-pull-down;
>> +    };
>> +
>> +    sde_te_suspend: sde-te-suspend-state {
>> +        pins = "gpio86";
>> +        function = "mdp_vsync";
>> +        drive-strength = <2>;
>> +        bias-pull-down;
>> +    };
>> +
>>       wcd_default: wcd-reset-n-active-state {
>>           pins = "gpio108";
>>           function = "gpio";
> 

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH 10/16] arm64: dts: qcom: sm8550-aim300: add display and panel

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Enable Display Subsystem with Visionox VTDR6130 Panel.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---

You just added this board. Does it mean you added incomplete and wrong DTS?

Best regards,
Krzysztof

Re: [PATCH 10/16] arm64: dts: qcom: sm8550-aim300: add display and panel

[Tengfei Fan]

在 11/17/2023 6:31 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Enable Display Subsystem with Visionox VTDR6130 Panel.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> 
> You just added this board. Does it mean you added incomplete and wrong DTS?
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I'm going to combine all the splited 
functions into one patch.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 11/16] arm64: dts: qcom: sm8550-aim300: add notification RGB LED

[Tengfei Fan]

The QRD features a notification LED connected to the pm8550.
Configure the RGB led controlled by the PMIC PWM controller.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 27 ++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index 9b568ae9581e..40132073038d 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -517,6 +517,33 @@
 	};
 };
 
+&pm8550_pwm {
+	status = "okay";
+
+	multi-led {
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_RED>;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_GREEN>;
+		};
+
+		led@3 {
+			reg = <3>;
+			color = <LED_COLOR_ID_BLUE>;
+		};
+	};
+};
+
 &pm8550b_eusb2_repeater {
 	vdd18-supply = <&vreg_l15b_1p8>;
 	vdd3-supply = <&vreg_l5b_3p1>;
-- 
2.17.1

Re: [PATCH 11/16] arm64: dts: qcom: sm8550-aim300: add notification RGB LED

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> The QRD features a notification LED connected to the pm8550.
> Configure the RGB led controlled by the PMIC PWM controller.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---

You just added this board. Does it mean you added incomplete and wrong DTS?

Best regards,
Krzysztof

Re: [PATCH 11/16] arm64: dts: qcom: sm8550-aim300: add notification RGB LED

[Tengfei Fan]

在 11/17/2023 6:31 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> The QRD features a notification LED connected to the pm8550.
>> Configure the RGB led controlled by the PMIC PWM controller.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> 
> You just added this board. Does it mean you added incomplete and wrong DTS?
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I'm going to combine all the splited 
functions into one patch.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 12/16] arm64: dts: qcom: sm8550-aim300: enable PMIC Volume and Power buttons

[Tengfei Fan]

The Volume Down & Power buttons are controlled by the PMIC via the PON
hardware, and the Volume Up is connected to a PMIC gpio.

Enable the necessary hardware and setup the GPIO state for the Volume Up
gpio key.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 37 ++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index 40132073038d..c3f49527b9ad 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -56,6 +56,22 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		pinctrl-0 = <&volume_up_n>;
+		pinctrl-names = "default";
+
+		key-volume-up {
+			label = "Volume Up";
+			debounce-interval = <15>;
+			gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
 	pmic-glink {
 		compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
 		#address-cells = <1>;
@@ -517,6 +533,16 @@
 	};
 };
 
+&pm8550_gpios {
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		bias-pull-up;
+		input-enable;
+	};
+};
+
 &pm8550_pwm {
 	status = "okay";
 
@@ -549,6 +575,17 @@
 	vdd3-supply = <&vreg_l5b_3p1>;
 };
 
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
-- 
2.17.1

Re: [PATCH 12/16] arm64: dts: qcom: sm8550-aim300: enable PMIC Volume and Power buttons

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> The Volume Down & Power buttons are controlled by the PMIC via the PON
> hardware, and the Volume Up is connected to a PMIC gpio.
> 
> Enable the necessary hardware and setup the GPIO state for the Volume Up
> gpio key.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---

No, really, necessary hardware? So why it is missing in the previous patch?

Stop useless splitting of work which is done. You cannot have "release
late, release often". The rule is: "release early, release often".

NAK.

Best regards,
Krzysztof

Re: [PATCH 12/16] arm64: dts: qcom: sm8550-aim300: enable PMIC Volume and Power buttons

[Tengfei Fan]

在 11/17/2023 6:32 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> The Volume Down & Power buttons are controlled by the PMIC via the PON
>> hardware, and the Volume Up is connected to a PMIC gpio.
>>
>> Enable the necessary hardware and setup the GPIO state for the Volume Up
>> gpio key.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> 
> No, really, necessary hardware? So why it is missing in the previous patch?
> 
> Stop useless splitting of work which is done. You cannot have "release
> late, release often". The rule is: "release early, release often".
> 
> NAK.
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I'm going to combine all the splited 
functions into one patch.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 13/16] arm64: dts: qcom: sm8550-aim300: add WSA8845 speakers

[Tengfei Fan]

Add Qualcomm WSA8845 Soundwire smart speaker amplifiers.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 48 ++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index c3f49527b9ad..e7035f57ce44 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -448,6 +448,24 @@
 		 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 };
 
+&lpass_tlmm {
+	spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+		pins = "gpio17";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+
+	spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
 &mdss {
 	status = "okay";
 };
@@ -612,6 +630,36 @@
 	clock-frequency = <32000>;
 };
 
+&swr0 {
+	status = "okay";
+
+	/* WSA8845, Speaker North */
+	north_spkr: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+		pinctrl-0 = <&spkr_1_sd_n_active>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l3g_1p2>;
+	};
+
+	/* WSA8845, Speaker South */
+	south_spkr: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+		pinctrl-0 = <&spkr_2_sd_n_active>;
+		pinctrl-names = "default";
+		powerdown-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>;
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		vdd-1p8-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l3g_1p2>;
+	};
+};
+
 &swr1 {
 	status = "okay";
 
-- 
2.17.1

Re: [PATCH 13/16] arm64: dts: qcom: sm8550-aim300: add WSA8845 speakers

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Add Qualcomm WSA8845 Soundwire smart speaker amplifiers.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>

NAK, it's initial submission.

Stop useless splitting of work which is done. You cannot have "release
late, release often". The rule is: "release early, release often".

Best regards,
Krzysztof

Re: [PATCH 13/16] arm64: dts: qcom: sm8550-aim300: add WSA8845 speakers

[Tengfei Fan]

在 11/17/2023 6:33 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Add Qualcomm WSA8845 Soundwire smart speaker amplifiers.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> 
> NAK, it's initial submission.
> 
> Stop useless splitting of work which is done. You cannot have "release
> late, release often". The rule is: "release early, release often".
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I'm going to combine all the splited 
functions into one patch.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 14/16] arm64: dts: qcom: sm8550-aim300: add sound card

[Tengfei Fan]

Add the sound card node with tested playback over WSA8845 speakers and
WCD9385 headset over USB Type-C.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 82 ++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index e7035f57ce44..6dc3040b9f76 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -107,6 +107,88 @@
 		};
 	};
 
+	sound {
+		compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+		model = "SM8550-AIM300";
+		audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA_SPK2 OUT",
+				"IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS1",
+				"VA DMIC1", "MIC BIAS1",
+				"VA DMIC2", "MIC BIAS3",
+				"TX DMIC0", "MIC BIAS1",
+				"TX DMIC1", "MIC BIAS2",
+				"TX DMIC2", "MIC BIAS3",
+				"TX SWR_ADC1", "ADC2_OUTPUT";
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-dai-link {
+			link-name = "WSA Playback";
+
+			cpu {
+				sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
+			};
+
+			codec {
+				sound-dai = <&north_spkr>, <&south_spkr>,
+					    <&swr0 0>, <&lpass_wsamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		va-dai-link {
+			link-name = "VA Capture";
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
 	vph_pwr: vph-pwr-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vph_pwr";
-- 
2.17.1

Re: [PATCH 14/16] arm64: dts: qcom: sm8550-aim300: add sound card

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Add the sound card node with tested playback over WSA8845 speakers and
> WCD9385 headset over USB Type-C.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 82 ++++++++++++++++++++++
>  1 file changed, 82 insertions(+)
> 

NAK, it's initial submission.

Stop useless splitting of work which is done. You cannot have "release
late, release often". The rule is: "release early, release often".

Best regards,
Krzysztof

Re: [PATCH 14/16] arm64: dts: qcom: sm8550-aim300: add sound card

[Tengfei Fan]

在 11/17/2023 6:33 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Add the sound card node with tested playback over WSA8845 speakers and
>> WCD9385 headset over USB Type-C.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 82 ++++++++++++++++++++++
>>   1 file changed, 82 insertions(+)
>>
> 
> NAK, it's initial submission.
> 
> Stop useless splitting of work which is done. You cannot have "release
> late, release often". The rule is: "release early, release often".
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I'm going to combine all the splited 
functions into one patch.

-- 
Thx and BRs,
Tengfei Fan

[PATCH 15/16] arm64: dts: qcom: sm8550-aim300: add pmic glink port/endpoints

[Tengfei Fan]

Add nodes to support Type-C USB/DP functionality.

On this platform, a Type-C redriver is added to the SuperSpeed graph.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 88 +++++++++++++++++++++-
 1 file changed, 87 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index 6dc3040b9f76..f3c558dd40f1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -100,7 +100,15 @@
 					reg = <1>;
 
 					pmic_glink_ss_in: endpoint {
-						remote-endpoint = <&usb_1_dwc3_ss>;
+						remote-endpoint = <&redriver_ss_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+
+					pmic_glink_sbu: endpoint {
+						remote-endpoint = <&fsa4480_sbu_mux>;
 					};
 				};
 			};
@@ -519,6 +527,62 @@
 	};
 };
 
+&i2c_master_hub_0 {
+	status = "okay";
+};
+
+&i2c_hub_2 {
+	status = "okay";
+
+	typec-mux@42 {
+		compatible = "fcs,fsa4480";
+		reg = <0x42>;
+
+		vcc-supply = <&vreg_bob1>;
+
+		mode-switch;
+		orientation-switch;
+
+		port {
+			fsa4480_sbu_mux: endpoint {
+				remote-endpoint = <&pmic_glink_sbu>;
+			};
+		};
+	};
+
+	typec-retimer@1c {
+		compatible = "onnn,nb7vpq904m";
+		reg = <0x1c>;
+
+		vcc-supply = <&vreg_l15b_1p8>;
+
+		orientation-switch;
+		retimer-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				redriver_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				redriver_ss_in: endpoint {
+					data-lanes = <3 2 1 0>;
+					remote-endpoint = <&usb_dp_qmpphy_out>;
+				};
+			};
+		};
+	};
+};
+
 &gcc {
 	clocks = <&bi_tcxo_div2>, <&sleep_clk>,
 		 <&pcie0_phy>,
@@ -552,6 +616,16 @@
 	status = "okay";
 };
 
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
+
 &mdss_dsi0 {
 	vdda-supply = <&vreg_l3e_1p2>;
 	status = "okay";
@@ -861,6 +935,18 @@
 	status = "okay";
 };
 
+&usb_dp_qmpphy_dp_in {
+	remote-endpoint = <&mdss_dp0_out>;
+};
+
+&usb_dp_qmpphy_out {
+	remote-endpoint = <&redriver_ss_in>;
+};
+
+&usb_dp_qmpphy_usb_ss_in {
+	remote-endpoint = <&usb_1_dwc3_ss>;
+};
+
 &xo_board {
 	clock-frequency = <76800000>;
 };
-- 
2.17.1

Re: [PATCH 15/16] arm64: dts: qcom: sm8550-aim300: add pmic glink port/endpoints

[Dmitry Baryshkov]

On 17/11/2023 12:18, Tengfei Fan wrote:
> Add nodes to support Type-C USB/DP functionality.
> 
> On this platform, a Type-C redriver is added to the SuperSpeed graph.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 88 +++++++++++++++++++++-
>   1 file changed, 87 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> index 6dc3040b9f76..f3c558dd40f1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> @@ -100,7 +100,15 @@
>   					reg = <1>;
>   
>   					pmic_glink_ss_in: endpoint {
> -						remote-endpoint = <&usb_1_dwc3_ss>;
> +						remote-endpoint = <&redriver_ss_out>;
> +					};
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +
> +					pmic_glink_sbu: endpoint {
> +						remote-endpoint = <&fsa4480_sbu_mux>;
>   					};
>   				};
>   			};
> @@ -519,6 +527,62 @@
>   	};
>   };
>   
> +&i2c_master_hub_0 {
> +	status = "okay";
> +};
> +
> +&i2c_hub_2 {
> +	status = "okay";
> +
> +	typec-mux@42 {
> +		compatible = "fcs,fsa4480";
> +		reg = <0x42>;
> +
> +		vcc-supply = <&vreg_bob1>;
> +
> +		mode-switch;
> +		orientation-switch;
> +
> +		port {
> +			fsa4480_sbu_mux: endpoint {
> +				remote-endpoint = <&pmic_glink_sbu>;
> +			};
> +		};
> +	};
> +
> +	typec-retimer@1c {
> +		compatible = "onnn,nb7vpq904m";
> +		reg = <0x1c>;
> +
> +		vcc-supply = <&vreg_l15b_1p8>;
> +
> +		orientation-switch;
> +		retimer-switch;
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0 {
> +				reg = <0>;
> +
> +				redriver_ss_out: endpoint {
> +					remote-endpoint = <&pmic_glink_ss_in>;
> +				};
> +			};
> +
> +			port@1 {
> +				reg = <1>;
> +
> +				redriver_ss_in: endpoint {
> +					data-lanes = <3 2 1 0>;
> +					remote-endpoint = <&usb_dp_qmpphy_out>;
> +				};
> +			};
> +		};
> +	};
> +};
> +
>   &gcc {
>   	clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>   		 <&pcie0_phy>,
> @@ -552,6 +616,16 @@
>   	status = "okay";
>   };
>   
> +&mdss_dp0 {
> +	status = "okay";
> +};
> +
> +&mdss_dp0_out {
> +	data-lanes = <0 1>;

Why? Are you really limited to two lanes for DP by the hardware?

> +	remote-endpoint = <&usb_dp_qmpphy_dp_in>;
> +};
> +
> +
>   &mdss_dsi0 {
>   	vdda-supply = <&vreg_l3e_1p2>;
>   	status = "okay";
> @@ -861,6 +935,18 @@
>   	status = "okay";
>   };
>   
> +&usb_dp_qmpphy_dp_in {
> +	remote-endpoint = <&mdss_dp0_out>;
> +};
> +
> +&usb_dp_qmpphy_out {
> +	remote-endpoint = <&redriver_ss_in>;
> +};
> +
> +&usb_dp_qmpphy_usb_ss_in {
> +	remote-endpoint = <&usb_1_dwc3_ss>;
> +};
> +
>   &xo_board {
>   	clock-frequency = <76800000>;
>   };

-- 
With best wishes
Dmitry

Re: [PATCH 15/16] arm64: dts: qcom: sm8550-aim300: add pmic glink port/endpoints

[Tengfei Fan]

在 11/17/2023 6:32 PM, Dmitry Baryshkov 写道:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Add nodes to support Type-C USB/DP functionality.
>>
>> On this platform, a Type-C redriver is added to the SuperSpeed graph.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 88 +++++++++++++++++++++-
>>   1 file changed, 87 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts 
>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> index 6dc3040b9f76..f3c558dd40f1 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -100,7 +100,15 @@
>>                       reg = <1>;
>>                       pmic_glink_ss_in: endpoint {
>> -                        remote-endpoint = <&usb_1_dwc3_ss>;
>> +                        remote-endpoint = <&redriver_ss_out>;
>> +                    };
>> +                };
>> +
>> +                port@2 {
>> +                    reg = <2>;
>> +
>> +                    pmic_glink_sbu: endpoint {
>> +                        remote-endpoint = <&fsa4480_sbu_mux>;
>>                       };
>>                   };
>>               };
>> @@ -519,6 +527,62 @@
>>       };
>>   };
>> +&i2c_master_hub_0 {
>> +    status = "okay";
>> +};
>> +
>> +&i2c_hub_2 {
>> +    status = "okay";
>> +
>> +    typec-mux@42 {
>> +        compatible = "fcs,fsa4480";
>> +        reg = <0x42>;
>> +
>> +        vcc-supply = <&vreg_bob1>;
>> +
>> +        mode-switch;
>> +        orientation-switch;
>> +
>> +        port {
>> +            fsa4480_sbu_mux: endpoint {
>> +                remote-endpoint = <&pmic_glink_sbu>;
>> +            };
>> +        };
>> +    };
>> +
>> +    typec-retimer@1c {
>> +        compatible = "onnn,nb7vpq904m";
>> +        reg = <0x1c>;
>> +
>> +        vcc-supply = <&vreg_l15b_1p8>;
>> +
>> +        orientation-switch;
>> +        retimer-switch;
>> +
>> +        ports {
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +
>> +            port@0 {
>> +                reg = <0>;
>> +
>> +                redriver_ss_out: endpoint {
>> +                    remote-endpoint = <&pmic_glink_ss_in>;
>> +                };
>> +            };
>> +
>> +            port@1 {
>> +                reg = <1>;
>> +
>> +                redriver_ss_in: endpoint {
>> +                    data-lanes = <3 2 1 0>;
>> +                    remote-endpoint = <&usb_dp_qmpphy_out>;
>> +                };
>> +            };
>> +        };
>> +    };
>> +};
>> +
>>   &gcc {
>>       clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>>            <&pcie0_phy>,
>> @@ -552,6 +616,16 @@
>>       status = "okay";
>>   };
>> +&mdss_dp0 {
>> +    status = "okay";
>> +};
>> +
>> +&mdss_dp0_out {
>> +    data-lanes = <0 1>;
> 
> Why? Are you really limited to two lanes for DP by the hardware?
I will ask my internal colleagues to comfirm this configuration, and the 
I will share the confimed result with you.
> 
>> +    remote-endpoint = <&usb_dp_qmpphy_dp_in>;
>> +};
>> +
>> +
>>   &mdss_dsi0 {
>>       vdda-supply = <&vreg_l3e_1p2>;
>>       status = "okay";
>> @@ -861,6 +935,18 @@
>>       status = "okay";
>>   };
>> +&usb_dp_qmpphy_dp_in {
>> +    remote-endpoint = <&mdss_dp0_out>;
>> +};
>> +
>> +&usb_dp_qmpphy_out {
>> +    remote-endpoint = <&redriver_ss_in>;
>> +};
>> +
>> +&usb_dp_qmpphy_usb_ss_in {
>> +    remote-endpoint = <&usb_1_dwc3_ss>;
>> +};
>> +
>>   &xo_board {
>>       clock-frequency = <76800000>;
>>   };
> 

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH 15/16] arm64: dts: qcom: sm8550-aim300: add pmic glink port/endpoints

[Tengfei Fan]

在 11/17/2023 6:32 PM, Dmitry Baryshkov 写道:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Add nodes to support Type-C USB/DP functionality.
>>
>> On this platform, a Type-C redriver is added to the SuperSpeed graph.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 88 +++++++++++++++++++++-
>>   1 file changed, 87 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts 
>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> index 6dc3040b9f76..f3c558dd40f1 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -100,7 +100,15 @@
>>                       reg = <1>;
>>                       pmic_glink_ss_in: endpoint {
>> -                        remote-endpoint = <&usb_1_dwc3_ss>;
>> +                        remote-endpoint = <&redriver_ss_out>;
>> +                    };
>> +                };
>> +
>> +                port@2 {
>> +                    reg = <2>;
>> +
>> +                    pmic_glink_sbu: endpoint {
>> +                        remote-endpoint = <&fsa4480_sbu_mux>;
>>                       };
>>                   };
>>               };
>> @@ -519,6 +527,62 @@
>>       };
>>   };
>> +&i2c_master_hub_0 {
>> +    status = "okay";
>> +};
>> +
>> +&i2c_hub_2 {
>> +    status = "okay";
>> +
>> +    typec-mux@42 {
>> +        compatible = "fcs,fsa4480";
>> +        reg = <0x42>;
>> +
>> +        vcc-supply = <&vreg_bob1>;
>> +
>> +        mode-switch;
>> +        orientation-switch;
>> +
>> +        port {
>> +            fsa4480_sbu_mux: endpoint {
>> +                remote-endpoint = <&pmic_glink_sbu>;
>> +            };
>> +        };
>> +    };
>> +
>> +    typec-retimer@1c {
>> +        compatible = "onnn,nb7vpq904m";
>> +        reg = <0x1c>;
>> +
>> +        vcc-supply = <&vreg_l15b_1p8>;
>> +
>> +        orientation-switch;
>> +        retimer-switch;
>> +
>> +        ports {
>> +            #address-cells = <1>;
>> +            #size-cells = <0>;
>> +
>> +            port@0 {
>> +                reg = <0>;
>> +
>> +                redriver_ss_out: endpoint {
>> +                    remote-endpoint = <&pmic_glink_ss_in>;
>> +                };
>> +            };
>> +
>> +            port@1 {
>> +                reg = <1>;
>> +
>> +                redriver_ss_in: endpoint {
>> +                    data-lanes = <3 2 1 0>;
>> +                    remote-endpoint = <&usb_dp_qmpphy_out>;
>> +                };
>> +            };
>> +        };
>> +    };
>> +};
>> +
>>   &gcc {
>>       clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>>            <&pcie0_phy>,
>> @@ -552,6 +616,16 @@
>>       status = "okay";
>>   };
>> +&mdss_dp0 {
>> +    status = "okay";
>> +};
>> +
>> +&mdss_dp0_out {
>> +    data-lanes = <0 1>;
> 
> Why? Are you really limited to two lanes for DP by the hardware?
I got confirmation from a colleague that it is right that limited to two 
lanes.
> 
>> +    remote-endpoint = <&usb_dp_qmpphy_dp_in>;
>> +};
>> +
>> +
>>   &mdss_dsi0 {
>>       vdda-supply = <&vreg_l3e_1p2>;
>>       status = "okay";
>> @@ -861,6 +935,18 @@
>>       status = "okay";
>>   };
>> +&usb_dp_qmpphy_dp_in {
>> +    remote-endpoint = <&mdss_dp0_out>;
>> +};
>> +
>> +&usb_dp_qmpphy_out {
>> +    remote-endpoint = <&redriver_ss_in>;
>> +};
>> +
>> +&usb_dp_qmpphy_usb_ss_in {
>> +    remote-endpoint = <&usb_1_dwc3_ss>;
>> +};
>> +
>>   &xo_board {
>>       clock-frequency = <76800000>;
>>   };
> 

-- 
Thx and BRs,
Tengfei Fan

Re: [PATCH 15/16] arm64: dts: qcom: sm8550-aim300: add pmic glink port/endpoints

[Dmitry Baryshkov]

On Tue, 28 Nov 2023 at 10:11, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>
>
>
> 在 11/17/2023 6:32 PM, Dmitry Baryshkov 写道:
> > On 17/11/2023 12:18, Tengfei Fan wrote:
> >> Add nodes to support Type-C USB/DP functionality.
> >>
> >> On this platform, a Type-C redriver is added to the SuperSpeed graph.
> >>
> >> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> >> ---
> >>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 88 +++++++++++++++++++++-
> >>   1 file changed, 87 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> >> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> >> index 6dc3040b9f76..f3c558dd40f1 100644
> >> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> >> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> >> @@ -100,7 +100,15 @@
> >>                       reg = <1>;
> >>                       pmic_glink_ss_in: endpoint {
> >> -                        remote-endpoint = <&usb_1_dwc3_ss>;
> >> +                        remote-endpoint = <&redriver_ss_out>;
> >> +                    };
> >> +                };
> >> +
> >> +                port@2 {
> >> +                    reg = <2>;
> >> +
> >> +                    pmic_glink_sbu: endpoint {
> >> +                        remote-endpoint = <&fsa4480_sbu_mux>;
> >>                       };
> >>                   };
> >>               };
> >> @@ -519,6 +527,62 @@
> >>       };
> >>   };
> >> +&i2c_master_hub_0 {
> >> +    status = "okay";
> >> +};
> >> +
> >> +&i2c_hub_2 {
> >> +    status = "okay";
> >> +
> >> +    typec-mux@42 {
> >> +        compatible = "fcs,fsa4480";
> >> +        reg = <0x42>;
> >> +
> >> +        vcc-supply = <&vreg_bob1>;
> >> +
> >> +        mode-switch;
> >> +        orientation-switch;
> >> +
> >> +        port {
> >> +            fsa4480_sbu_mux: endpoint {
> >> +                remote-endpoint = <&pmic_glink_sbu>;
> >> +            };
> >> +        };
> >> +    };
> >> +
> >> +    typec-retimer@1c {
> >> +        compatible = "onnn,nb7vpq904m";
> >> +        reg = <0x1c>;
> >> +
> >> +        vcc-supply = <&vreg_l15b_1p8>;
> >> +
> >> +        orientation-switch;
> >> +        retimer-switch;
> >> +
> >> +        ports {
> >> +            #address-cells = <1>;
> >> +            #size-cells = <0>;
> >> +
> >> +            port@0 {
> >> +                reg = <0>;
> >> +
> >> +                redriver_ss_out: endpoint {
> >> +                    remote-endpoint = <&pmic_glink_ss_in>;
> >> +                };
> >> +            };
> >> +
> >> +            port@1 {
> >> +                reg = <1>;
> >> +
> >> +                redriver_ss_in: endpoint {
> >> +                    data-lanes = <3 2 1 0>;
> >> +                    remote-endpoint = <&usb_dp_qmpphy_out>;
> >> +                };
> >> +            };
> >> +        };
> >> +    };
> >> +};
> >> +
> >>   &gcc {
> >>       clocks = <&bi_tcxo_div2>, <&sleep_clk>,
> >>            <&pcie0_phy>,
> >> @@ -552,6 +616,16 @@
> >>       status = "okay";
> >>   };
> >> +&mdss_dp0 {
> >> +    status = "okay";
> >> +};
> >> +
> >> +&mdss_dp0_out {
> >> +    data-lanes = <0 1>;
> >
> > Why? Are you really limited to two lanes for DP by the hardware?
> I got confirmation from a colleague that it is right that limited to two
> lanes.

Excuse me, I missed your reply earlier. Is it 2 DP lanes and 2 SS USB
lanes? Or are there just 2 lanes which are shared between DP and SS
USB?

> >
> >> +    remote-endpoint = <&usb_dp_qmpphy_dp_in>;
> >> +};
> >> +
> >> +
> >>   &mdss_dsi0 {
> >>       vdda-supply = <&vreg_l3e_1p2>;
> >>       status = "okay";
> >> @@ -861,6 +935,18 @@
> >>       status = "okay";
> >>   };
> >> +&usb_dp_qmpphy_dp_in {
> >> +    remote-endpoint = <&mdss_dp0_out>;
> >> +};
> >> +
> >> +&usb_dp_qmpphy_out {
> >> +    remote-endpoint = <&redriver_ss_in>;
> >> +};
> >> +
> >> +&usb_dp_qmpphy_usb_ss_in {
> >> +    remote-endpoint = <&usb_1_dwc3_ss>;
> >> +};
> >> +
> >>   &xo_board {
> >>       clock-frequency = <76800000>;
> >>   };
> >
>
> --
> Thx and BRs,
> Tengfei Fan



-- 
With best wishes
Dmitry

Re: [PATCH 15/16] arm64: dts: qcom: sm8550-aim300: add pmic glink port/endpoints

[Tengfei Fan]

On 12/13/2023 6:04 PM, Dmitry Baryshkov wrote:
> On Tue, 28 Nov 2023 at 10:11, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>>
>>
>>
>> 在 11/17/2023 6:32 PM, Dmitry Baryshkov 写道:
>>> On 17/11/2023 12:18, Tengfei Fan wrote:
>>>> Add nodes to support Type-C USB/DP functionality.
>>>>
>>>> On this platform, a Type-C redriver is added to the SuperSpeed graph.
>>>>
>>>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>>>> ---
>>>>    arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 88 +++++++++++++++++++++-
>>>>    1 file changed, 87 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>> index 6dc3040b9f76..f3c558dd40f1 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>>>> @@ -100,7 +100,15 @@
>>>>                        reg = <1>;
>>>>                        pmic_glink_ss_in: endpoint {
>>>> -                        remote-endpoint = <&usb_1_dwc3_ss>;
>>>> +                        remote-endpoint = <&redriver_ss_out>;
>>>> +                    };
>>>> +                };
>>>> +
>>>> +                port@2 {
>>>> +                    reg = <2>;
>>>> +
>>>> +                    pmic_glink_sbu: endpoint {
>>>> +                        remote-endpoint = <&fsa4480_sbu_mux>;
>>>>                        };
>>>>                    };
>>>>                };
>>>> @@ -519,6 +527,62 @@
>>>>        };
>>>>    };
>>>> +&i2c_master_hub_0 {
>>>> +    status = "okay";
>>>> +};
>>>> +
>>>> +&i2c_hub_2 {
>>>> +    status = "okay";
>>>> +
>>>> +    typec-mux@42 {
>>>> +        compatible = "fcs,fsa4480";
>>>> +        reg = <0x42>;
>>>> +
>>>> +        vcc-supply = <&vreg_bob1>;
>>>> +
>>>> +        mode-switch;
>>>> +        orientation-switch;
>>>> +
>>>> +        port {
>>>> +            fsa4480_sbu_mux: endpoint {
>>>> +                remote-endpoint = <&pmic_glink_sbu>;
>>>> +            };
>>>> +        };
>>>> +    };
>>>> +
>>>> +    typec-retimer@1c {
>>>> +        compatible = "onnn,nb7vpq904m";
>>>> +        reg = <0x1c>;
>>>> +
>>>> +        vcc-supply = <&vreg_l15b_1p8>;
>>>> +
>>>> +        orientation-switch;
>>>> +        retimer-switch;
>>>> +
>>>> +        ports {
>>>> +            #address-cells = <1>;
>>>> +            #size-cells = <0>;
>>>> +
>>>> +            port@0 {
>>>> +                reg = <0>;
>>>> +
>>>> +                redriver_ss_out: endpoint {
>>>> +                    remote-endpoint = <&pmic_glink_ss_in>;
>>>> +                };
>>>> +            };
>>>> +
>>>> +            port@1 {
>>>> +                reg = <1>;
>>>> +
>>>> +                redriver_ss_in: endpoint {
>>>> +                    data-lanes = <3 2 1 0>;
>>>> +                    remote-endpoint = <&usb_dp_qmpphy_out>;
>>>> +                };
>>>> +            };
>>>> +        };
>>>> +    };
>>>> +};
>>>> +
>>>>    &gcc {
>>>>        clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>>>>             <&pcie0_phy>,
>>>> @@ -552,6 +616,16 @@
>>>>        status = "okay";
>>>>    };
>>>> +&mdss_dp0 {
>>>> +    status = "okay";
>>>> +};
>>>> +
>>>> +&mdss_dp0_out {
>>>> +    data-lanes = <0 1>;
>>>
>>> Why? Are you really limited to two lanes for DP by the hardware?
>> I got confirmation from a colleague that it is right that limited to two
>> lanes.
> 
> Excuse me, I missed your reply earlier. Is it 2 DP lanes and 2 SS USB
> lanes? Or are there just 2 lanes which are shared between DP and SS
> USB?

Excuse me, because the patch series of V2 has been sent before you reply 
to this, so I missed your message in this patch series.

I confirmed with my colleagues, there are just 2 lanes which are shared 
between DP and SS USB.

> 
>>>
>>>> +    remote-endpoint = <&usb_dp_qmpphy_dp_in>;
>>>> +};
>>>> +
>>>> +
>>>>    &mdss_dsi0 {
>>>>        vdda-supply = <&vreg_l3e_1p2>;
>>>>        status = "okay";
>>>> @@ -861,6 +935,18 @@
>>>>        status = "okay";
>>>>    };
>>>> +&usb_dp_qmpphy_dp_in {
>>>> +    remote-endpoint = <&mdss_dp0_out>;
>>>> +};
>>>> +
>>>> +&usb_dp_qmpphy_out {
>>>> +    remote-endpoint = <&redriver_ss_in>;
>>>> +};
>>>> +
>>>> +&usb_dp_qmpphy_usb_ss_in {
>>>> +    remote-endpoint = <&usb_1_dwc3_ss>;
>>>> +};
>>>> +
>>>>    &xo_board {
>>>>        clock-frequency = <76800000>;
>>>>    };
>>>
>>
>> --
>> Thx and BRs,
>> Tengfei Fan
> 
> 
> 

-- 
Thx and BRs,
Tengfei Fan

[PATCH 16/16] arm64: dts: qcom: sm8550-aim300: add bluetooth support

[Tengfei Fan]

Enable the WCN7850 bluetooth over the UART14 link.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
index f3c558dd40f1..8129d57c4af1 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
@@ -23,6 +23,7 @@
 
 	aliases {
 		serial0 = &uart7;
+		serial1 = &uart14;
 	};
 
 	wcd938x: audio-codec {
@@ -764,6 +765,10 @@
 	status = "okay";
 };
 
+&qupv3_id_1 {
+	status = "okay";
+};
+
 &remoteproc_adsp {
 	firmware-name = "qcom/sm8550/adsp.mbn",
 			"qcom/sm8550/adsp_dtb.mbn";
@@ -841,6 +846,21 @@
 &tlmm {
 	gpio-reserved-ranges = <32 8>;
 
+	bt_default: bt-default-state {
+		bt-en-pins {
+			pins = "gpio81";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		sw-ctrl-pins {
+			pins = "gpio82";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+
 	sde_dsi_active: sde-dsi-active-state {
 		pins = "gpio133";
 		function = "gpio";
@@ -882,6 +902,29 @@
 	status = "okay";
 };
 
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+
+		enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+		swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>;
+
+		max-speed = <3200000>;
+
+		pinctrl-0 = <&bt_default>;
+		pinctrl-names = "default";
+
+		vddio-supply = <&vreg_l15b_1p8>;
+		vddaon-supply = <&vreg_s4e_0p95>;
+		vdddig-supply = <&vreg_s4e_0p95>;
+		vddrfa0p8-supply = <&vreg_s4e_0p95>;
+		vddrfa1p2-supply = <&vreg_s4g_1p25>;
+		vddrfa1p9-supply = <&vreg_s6g_1p86>;
+	};
+};
+
 &ufs_mem_hc {
 	reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
 	vcc-supply = <&vreg_l17b_2p5>;
-- 
2.17.1

Re: [PATCH 16/16] arm64: dts: qcom: sm8550-aim300: add bluetooth support

[Krzysztof Kozlowski]

On 17/11/2023 11:18, Tengfei Fan wrote:
> Enable the WCN7850 bluetooth over the UART14 link.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
NAK, it's initial submission.

Stop useless splitting of work which is done. You cannot have "release
late, release often". The rule is: "release early, release often".

Best regards,
Krzysztof

Re: [PATCH 16/16] arm64: dts: qcom: sm8550-aim300: add bluetooth support

[Tengfei Fan]

在 11/17/2023 6:33 PM, Krzysztof Kozlowski 写道:
> On 17/11/2023 11:18, Tengfei Fan wrote:
>> Enable the WCN7850 bluetooth over the UART14 link.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
> NAK, it's initial submission.
> 
> Stop useless splitting of work which is done. You cannot have "release
> late, release often". The rule is: "release early, release often".
> 
> Best regards,
> Krzysztof
> 

Hi Krzysztof,
In next version patch series, I'm going to combine all the splited 
functions into one patch.

-- 
Thx and BRs,
Tengfei Fan