Re: [PATCH RFC 1/2] arm64: dts: qcom: eliza: Add display (MDSS) with Display CC

[Krzysztof Kozlowski <krzk@kernel.org>]

On 02/04/2026 11:42, Konrad Dybcio wrote:
> On 3/31/26 4:02 PM, Krzysztof Kozlowski wrote:
>> Add device nodes for almost entire display: MDSS, DPU, DSI, DSI PHYs,
>> DisplayPort and Display Clock Controller.
>>
>> Missing pieces are HDMI PHY and HDMI controller.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>>
>> ---
> 
> [...]
> 
>> +			mdss_mdp: display-controller@ae01000 {
>> +				compatible = "qcom,eliza-dpu";
>> +				reg = <0x0 0x0ae01000 0x0 0x93000>,
>> +				      <0x0 0x0aeb0000 0x0 0x2008>;
> 
> sz=0x3000
> 
> [...]

Thanks, I will double check with spec.

> 
>> +			mdss_dsi0: dsi@ae94000 {
>> +				compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> 
> linebreak?
> 
>> +				reg = <0x0 0x0ae94000 0x0 0x400>;
>> +				reg-names = "dsi_ctrl";
>> +
>> +				interrupts-extended = <&mdss 4>;
>> +
>> +				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
>> +					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
>> +					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
>> +					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
>> +					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> +					 <&gcc GCC_DISP_HF_AXI_CLK>,
>> +					 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
>> +					 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
>> +					 <&dispcc DISP_CC_ESYNC0_CLK>,
>> +					 <&dispcc DISP_CC_OSC_CLK>,
>> +					 <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
>> +					 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
> 
> Why the source clocks?

Short answer: because SM8750 binding requires it and that's the
same/derivative as indicated by compatibles.

Typical mailing list answer when people do not have any arguments: But
Kaanapali has the same!

Long answer: because that's how we represent the parent clocks in ABI
for the kernel. IOW, assigned-clocks do not work :(.

Rationale is in the 34bdf809a567ccefa1984ccda010c4b5de6c68c8 commit.

> 
> [...]
> 
>> +			mdss_dsi0_phy: phy@ae95000 {
>> +				compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
>> +				reg = <0x0 0x0ae95000 0x0 0x200>,
>> +				      <0x0 0x0ae95200 0x0 0x280>,
> 
> sz=0x300
> 
> [...]
> 
>> +			mdss_dp0: displayport-controller@af54000 {
>> +				compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
>> +				reg = <0x0 0xaf54000 0x0 0x104>,
> 
> please pad the addr to 8 hex digits
> 
> sz=0x200
> 
>> +				      <0x0 0xaf54200 0x0 0xc0>,
> 
> sz=0x200
> 
>> +				      <0x0 0xaf55000 0x0 0x770>,
> 
> sz=0xc00
>> +				      <0x0 0xaf56000 0x0 0x9c>,
> 
> sz=0x400
>> +				      <0x0 0xaf57000 0x0 0x9c>;
> 
> sz=0x400
> 
> Also missing regs for quad-MST (Pixel2/3 @ 0x0af5_[89]000, each 0x400-long
> and MST2/3_link @ 0x0af5_[ab]000, 0x600-long). I don't know if the DPU can
> do quad-MST but there's registers..

OK, let me look at datasheet again.


Best regards,
Krzysztof