From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9087D3DEAEC; Thu, 2 Apr 2026 09:49:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775123389; cv=none; b=IUH3Lg2s2Bx4DLMforjDbE9axK2A//HtTf8N//Klq4mJHBKxgHfdL4hQMMNkCP8OqhG1m/N67hEIHPHkvn2vbtOqbApGDs2xUBiVdDSMK+p7JulmkezKvuR7FM2EECRCaVFl94XuUQIIpv+Iifj5DtwtAqwpituTn+UVtaXye0w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775123389; c=relaxed/simple; bh=Oj+5uBOFgp5Zzmr5HPFcAx2HeD+3q8NmM1W/70Z/BqE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=sO3JgSIKqh/DuVudt9anTo9dol65uS/jScB+VeNgwzDBwgLMSeuD2qymxR9P4BWAx1X2XhufbDg/scS4v5i+IbYOUXQCM2EApxPJt0zZpKTockLujgJVyAoklIsHInydZnM0HPnmoOnYtvPPKzMrVghwKFK+CgL0JJkfaL2QI3A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gWwxHjwE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gWwxHjwE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8B19C19423; Thu, 2 Apr 2026 09:49:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775123389; bh=Oj+5uBOFgp5Zzmr5HPFcAx2HeD+3q8NmM1W/70Z/BqE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=gWwxHjwEPBoxmXzZuynaETkXQUV9+daANbNJTNRxoC9ka4MetOO6Ui9KBI+0fi56K YahQuoyXlfmSXgMjOOO5fhKBfWvIjmpQyin/pvw613snEWoB1NLFHdOxrjEXIw0F8h aHIlltfdS5pj7kSs8Y+SBn+EAhFdp8NAF8+vVn+Px9/WforBtTH27w2t+ZKU+/4gB+ 3vRKpVPGzMFmRKfgC4vfjrDzuefZgcSK5BNrJdEp2b03hYd2juSn7d74FDcMYL3iRO 8Hc44vQPos63kwWV2jR/Ms7dCAgMkAe2en6mgPF2/XjscvPv4GEJ0p7EF/Rsf7tYlt 9GTLfwrvp/91Q== Message-ID: <4eb95523-c811-4702-b6e7-2e3f801dc754@kernel.org> Date: Thu, 2 Apr 2026 11:49:44 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/2] arm64: dts: qcom: eliza: Add display (MDSS) with Display CC To: Konrad Dybcio , Krzysztof Kozlowski , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa References: <20260331-dts-qcom-eliza-display-v1-0-856f0b66b282@oss.qualcomm.com> <20260331-dts-qcom-eliza-display-v1-1-856f0b66b282@oss.qualcomm.com> <6488e6e7-726c-4f0b-a6b0-2914b04e118a@oss.qualcomm.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 02/04/2026 11:42, Konrad Dybcio wrote: > On 3/31/26 4:02 PM, Krzysztof Kozlowski wrote: >> Add device nodes for almost entire display: MDSS, DPU, DSI, DSI PHYs, >> DisplayPort and Display Clock Controller. >> >> Missing pieces are HDMI PHY and HDMI controller. >> >> Signed-off-by: Krzysztof Kozlowski >> >> --- > > [...] > >> + mdss_mdp: display-controller@ae01000 { >> + compatible = "qcom,eliza-dpu"; >> + reg = <0x0 0x0ae01000 0x0 0x93000>, >> + <0x0 0x0aeb0000 0x0 0x2008>; > > sz=0x3000 > > [...] Thanks, I will double check with spec. > >> + mdss_dsi0: dsi@ae94000 { >> + compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > > linebreak? > >> + reg = <0x0 0x0ae94000 0x0 0x400>; >> + reg-names = "dsi_ctrl"; >> + >> + interrupts-extended = <&mdss 4>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, >> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, >> + <&dispcc DISP_CC_MDSS_ESC0_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, >> + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, >> + <&dispcc DISP_CC_ESYNC0_CLK>, >> + <&dispcc DISP_CC_OSC_CLK>, >> + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > > Why the source clocks? Short answer: because SM8750 binding requires it and that's the same/derivative as indicated by compatibles. Typical mailing list answer when people do not have any arguments: But Kaanapali has the same! Long answer: because that's how we represent the parent clocks in ABI for the kernel. IOW, assigned-clocks do not work :(. Rationale is in the 34bdf809a567ccefa1984ccda010c4b5de6c68c8 commit. > > [...] > >> + mdss_dsi0_phy: phy@ae95000 { >> + compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; >> + reg = <0x0 0x0ae95000 0x0 0x200>, >> + <0x0 0x0ae95200 0x0 0x280>, > > sz=0x300 > > [...] > >> + mdss_dp0: displayport-controller@af54000 { >> + compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; >> + reg = <0x0 0xaf54000 0x0 0x104>, > > please pad the addr to 8 hex digits > > sz=0x200 > >> + <0x0 0xaf54200 0x0 0xc0>, > > sz=0x200 > >> + <0x0 0xaf55000 0x0 0x770>, > > sz=0xc00 >> + <0x0 0xaf56000 0x0 0x9c>, > > sz=0x400 >> + <0x0 0xaf57000 0x0 0x9c>; > > sz=0x400 > > Also missing regs for quad-MST (Pixel2/3 @ 0x0af5_[89]000, each 0x400-long > and MST2/3_link @ 0x0af5_[ab]000, 0x600-long). I don't know if the DPU can > do quad-MST but there's registers.. OK, let me look at datasheet again. Best regards, Krzysztof