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([2001:818:ea8e:7f00:2575:914:eedd:620e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43f233c8224sm44508825e9.22.2025.04.10.02.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 02:40:14 -0700 (PDT) Message-ID: <4ef3b2464691d65a295d0f5669e27f8a5382ea06.camel@gmail.com> Subject: Re: [PATCH v1 4/7] iio: adc: ad4170: Add clock provider support From: Nuno =?ISO-8859-1?Q?S=E1?= To: Marcelo Schmitt , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: jic23@kernel.org, lars@metafoo.de, Michael.Hennerich@analog.com, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, marcelo.schmitt1@gmail.com Date: Thu, 10 Apr 2025 10:40:16 +0100 In-Reply-To: <65b71e307d37b8e3e26937a1e67398b2af0af399.1744200264.git.marcelo.schmitt@analog.com> References: <65b71e307d37b8e3e26937a1e67398b2af0af399.1744200264.git.marcelo.schmitt@analog.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2025-04-09 at 09:25 -0300, Marcelo Schmitt wrote: > The AD4170 chip can use an externally supplied clock at the XTAL2 pin, or > an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively, > the AD4170 can provide it's 16 MHz internal clock at the XTAL2 pin. Exten= d > the AD4170 driver so it effectively uses the provided external clock, if > any, or supplies it's own clock as a clock provider. >=20 > Signed-off-by: Marcelo Schmitt > --- Just one minor note, with it: Reviewed-by: Nuno S=C3=A1 > =C2=A0drivers/iio/adc/ad4170.c | 135 ++++++++++++++++++++++++++++++++++++= ++- > =C2=A01 file changed, 134 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/iio/adc/ad4170.c b/drivers/iio/adc/ad4170.c > index 5ffcdedf3e7f..97cf4465038f 100644 > --- a/drivers/iio/adc/ad4170.c > +++ b/drivers/iio/adc/ad4170.c > @@ -7,6 +7,8 @@ > =C2=A0 > =C2=A0#include > =C2=A0#include > +#include > +#include > =C2=A0#include > =C2=A0#include > =C2=A0#include > @@ -62,6 +64,7 @@ > =C2=A0#define AD4170_DATA_16B_STATUS_REG 0x1A > =C2=A0#define AD4170_DATA_24B_REG 0x1E > =C2=A0#define AD4170_PIN_MUXING_REG 0x69 > +#define AD4170_CLOCK_CTRL_REG 0x6B > =C2=A0#define AD4170_ADC_CTRL_REG 0x71 > =C2=A0#define AD4170_CHAN_EN_REG 0x79 > =C2=A0#define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x)) > @@ -89,6 +92,9 @@ > =C2=A0#define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4) > =C2=A0#define AD4170_PIN_MUXING_SYNC_CTRL_MSK GENMASK(3, 2) > =C2=A0 > +/* AD4170_CLOCK_CTRL_REG */ > +#define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0) > + > =C2=A0/* AD4170_ADC_CTRL_REG */ > =C2=A0#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7) > =C2=A0#define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4) > @@ -121,6 +127,12 @@ > =C2=A0 > =C2=A0/* AD4170 register constants */ > =C2=A0 > +/* AD4170_CLOCK_CTRL_REG constants */ > +#define AD4170_CLOCK_CTRL_CLOCKSEL_INT 0x0 > +#define AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT 0x1 > +#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT 0x2 > +#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT_XTAL 0x3 > + > =C2=A0/* AD4170_CHAN_MAP_REG constants */ > =C2=A0#define AD4170_CHAN_MAP_AIN0 0 > =C2=A0#define AD4170_CHAN_MAP_AIN1 1 > @@ -238,6 +250,10 @@ enum ad4170_regulator { > =C2=A0 AD4170_MAX_SUP > =C2=A0}; > =C2=A0 > +static const char *const ad4170_clk_sel[] =3D { > + "ext-clk", "xtal" > +}; > + > =C2=A0enum ad4170_int_pin_sel { > =C2=A0 AD4170_INT_PIN_SDO, > =C2=A0 AD4170_INT_PIN_DIG_AUX1, > @@ -320,6 +336,9 @@ struct ad4170_state { > =C2=A0 struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS]; > =C2=A0 struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS]; > =C2=A0 u32 mclk_hz; > + unsigned int clock_ctrl; > + struct clk *ext_clk; > + struct clk_hw int_clk_hw; > =C2=A0 int pins_fn[AD4170_NUM_ANALOG_PINS]; > =C2=A0 u32 int_pin_sel; > =C2=A0 int > sps_tbl[ARRAY_SIZE(ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE][2]; > @@ -1693,13 +1712,127 @@ static int ad4170_parse_channels(struct iio_dev > *indio_dev) > =C2=A0 return 0; > =C2=A0} > =C2=A0 > +static struct ad4170_state *clk_hw_to_ad4170(struct clk_hw *hw) > +{ > + return container_of(hw, struct ad4170_state, int_clk_hw); > +} > + > +static unsigned long ad4170_sel_clk(struct ad4170_state *st, > + =C2=A0=C2=A0=C2=A0 unsigned int clk_sel) > +{ > + st->clock_ctrl &=3D ~AD4170_CLOCK_CTRL_CLOCKSEL_MSK; > + st->clock_ctrl |=3D FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, > clk_sel); > + return regmap_write(st->regmap16, AD4170_CLOCK_CTRL_REG, st- > >clock_ctrl); > +} > + > +static unsigned long ad4170_clk_recalc_rate(struct clk_hw *hw, > + =C2=A0=C2=A0=C2=A0 unsigned long parent_rate) > +{ > + return AD4170_INT_CLOCK_16MHZ; > +} > + > +static int ad4170_clk_output_is_enabled(struct clk_hw *hw) > +{ > + struct ad4170_state *st =3D clk_hw_to_ad4170(hw); > + u32 clk_sel; > + > + clk_sel =3D FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl); > + return clk_sel =3D=3D AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT; > +} > + > +static int ad4170_clk_output_prepare(struct clk_hw *hw) > +{ > + struct ad4170_state *st =3D clk_hw_to_ad4170(hw); > + > + return ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT); > +} > + > +static void ad4170_clk_output_unprepare(struct clk_hw *hw) > +{ > + struct ad4170_state *st =3D clk_hw_to_ad4170(hw); > + > + ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT); > +} > + > +static const struct clk_ops ad4170_int_clk_ops =3D { > + .recalc_rate =3D ad4170_clk_recalc_rate, > + .is_enabled =3D ad4170_clk_output_is_enabled, > + .prepare =3D ad4170_clk_output_prepare, > + .unprepare =3D ad4170_clk_output_unprepare, > +}; > + > +static int ad4170_register_clk_provider(struct iio_dev *indio_dev) > +{ > + struct ad4170_state *st =3D iio_priv(indio_dev); > + struct device *dev =3D indio_dev->dev.parent; > + struct fwnode_handle *fwnode =3D dev_fwnode(dev); > + struct clk_init_data init =3D {}; > + int ret; > + > + if (!IS_ENABLED(CONFIG_COMMON_CLK)) > + return 0; > + > + init.name =3D fwnode_get_name(fwnode); Maybe allow for clock-output-names? See: https://elixir.bootlin.com/linux/v6.13.7/source/drivers/iio/frequency/adf43= 50.c#L467 - Nuno S=C3=A1