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Thu, 25 Jun 2026 01:47:10 -0700 (PDT) X-Received: by 2002:a05:622a:1451:b0:517:6d82:9d7b with SMTP id d75a77b69052e-51a7279ef50mr12133051cf.4.1782377230257; Thu, 25 Jun 2026 01:47:10 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c11fbe05f9csm132345966b.31.2026.06.25.01.47.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jun 2026 01:47:09 -0700 (PDT) Message-ID: <4f0878a0-2ab1-490d-b251-c6d68c4ee241@oss.qualcomm.com> Date: Thu, 25 Jun 2026 10:47:07 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/6] iommu/arm-smmu: Add interconnect bandwidth voting support To: Bibek Kumar Patro , Dmitry Baryshkov Cc: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20260526-smmu_interconnect_addition-v2-0-2a6d8ca30d63@oss.qualcomm.com> <20260526-smmu_interconnect_addition-v2-2-2a6d8ca30d63@oss.qualcomm.com> <7xfxlxfqjcqdzl6gckaoyy2ioefglc7bgi66yv5khrbl6fi2zc@ivtiukdaj4jv> <299d54c5-fb93-47ee-9495-fbf48a3204fd@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA3NCBTYWx0ZWRfX/QLgynoGf9C5 6nAlJuuM42lsijkjYPtmLEJKD4vDP6v6hJoUZQM5UnMRi/JQ0qmXkcX0j1lfO5sHkLs4ZLJny20 p8xIX2IB2r3/SC1t+JsH1i7aBtcEhps= X-Proofpoint-ORIG-GUID: bQRlw9LEFCRphEcB7H13hL-vmIfFbGdO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA3NCBTYWx0ZWRfX5xH0WTihp1Lp HiAXXrP2AjnOH3UPX/k14+T8m6spgOgO0kjbBKXnrFunsGsgamSBbxpfhs4nr+pMylSPpA3TSvo 5Cg525+9WOo2S6p20hyGDJPQ02FlCW4rrCZBgHfwr2ywyHRQssJ0aMm1VBukltFWNkh7vQHMWgU RgjIIrOjehSCfS8J63bk3A2SJ6ljUpCNlJuNGoTJgepwHngDtFr1Rw/VODyKQ77Z0Xq8YvjWTgG hi60PBADSnykMuwhw2QMDJxc/u5oGEH+K+9naiyBUatspXIhx/1jIrzpabfJuPR/KXuFNv7bKrU hhqi1HXhdYaLI7p1Y6eEnzcrTC+s/c+3gRaIiKcMQED90Poro+J31kM7cDWoHXgE3/UZIrhhXSm yG6cagkk9LqFLjvgAmSdksGcR8oobKlnaVh6toPl1v8DVXbTKLV8Dp011p06VdFP1fUpOO5TdYZ Bir+KQbvP7LPvj7C4+A== X-Proofpoint-GUID: bQRlw9LEFCRphEcB7H13hL-vmIfFbGdO X-Authority-Analysis: v=2.4 cv=TcSmcxQh c=1 sm=1 tr=0 ts=6a3ceb10 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=TtB6gFZ535HFW_zVIisA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250074 On 6/19/26 12:54 PM, Bibek Kumar Patro wrote: > > > On 6/18/2026 2:58 PM, Konrad Dybcio wrote: >> On 6/17/26 4:26 PM, Bibek Kumar Patro wrote: >>> >>> >>> On 6/16/2026 5:51 AM, Dmitry Baryshkov wrote: >>>> On Mon, Jun 15, 2026 at 06:36:51PM +0530, Bibek Kumar Patro wrote: >>>>> >>>>> >>>>> On 6/8/2026 7:25 PM, Dmitry Baryshkov wrote: >>>>>> On Tue, May 26, 2026 at 08:12:03PM +0530, Bibek Kumar Patro wrote: >>>>>>> On some SoCs the SMMU registers require an active interconnect >>>>>>> bandwidth vote to be accessible. While other clients typically >>>>>>> satisfy this requirement implicitly, certain corner cases (e.g. >>>>>>> during sleep/wakeup transitions) can leave the SMMU without a >>>>>>> vote, causing intermittent register access failures. >>>>>>> >>>>>>> Add support for an optional interconnect path to the arm-smmu >>>>>>> driver and vote for bandwidth while the SMMU is active. The path >>>>>>> is acquired from DT if present and ignored otherwise. >>>>>>> >>>>>>> The bandwidth vote is enabled before accessing SMMU registers >>>>>>> during probe and runtime resume, and released during runtime >>>>>>> suspend and on error paths. >>>>>>> >>>>>>> Generally, from an architectural perspective, GEM_NOC and DDR are >>>>>>> expected to have an active vote whenever the adreno_smmu block is >>>>>>> powered on. In most common use cases, this requirement is implicitly >>>>>>> satisfied because other GPU-related clients (for example, the GMU >>>>>>> device) already hold a GEM_NOC vote when adreno_smmu is enabled. >>>>>>> >>>>>>> However, there are certain corner cases, such as during sleep/wakeup >>>>>>> transitions, where the GEM_NOC vote can be removed before adreno_smmu >>>>>>> is powered down. If adreno_smmu is then accessed while the interconnect >>>>>>> vote is missing, it can lead to the observed failures. Because of the >>>>>>> precise ordering involved, this scenario is difficult to reproduce >>>>>>> consistently. >>>>>>> (also GDSC is involved in adreno usecases can have an independent vote) >>>>>>> >>>>>>> Signed-off-by: Bibek Kumar Patro >>>>>>> --- >>>>>>>     drivers/iommu/arm/arm-smmu/arm-smmu.c | 57 +++++++++++++++++++++++++++++++++-- >>>>>>>     drivers/iommu/arm/arm-smmu/arm-smmu.h |  2 ++ >>>>>>>     2 files changed, 57 insertions(+), 2 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>>>> index 0bd21d206eb3e75c3b9fb1364cdc92e82c5aa499..07c7e44ec6a5bd1488f00f87d859a20495e46601 100644 >>>>>>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>>>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c >>>>>>> @@ -53,6 +53,11 @@ >>>>>>>     #define MSI_IOVA_BASE            0x8000000 >>>>>>>     #define MSI_IOVA_LENGTH            0x100000 >>>>>>> +/* Interconnect bandwidth vote values for the SMMU register access path */ >>>>>>> +#define ARM_SMMU_ICC_AVG_BW        0 >>>>>>> +#define ARM_SMMU_ICC_PEAK_BW_HIGH    1000 >>>>>> >>>>>> totally random numbers, which might be different for non-Qualcomm platform. >>>>>> >>>>> >>>>> Ideally, any non-zero value would be enough to keep the path active. >>>> >>>> This is true for Qualcomm devices. However, you are adding this to a >>>> generic code. >>>> >>>>> Here 1 Would be enough to keep the path active, but might be too small to >>>>> reliably keep the bus active. >>>>> Other is UINT_MAX, which will reliably keep the bus active but might cause a >>>>> power penalty. >>>>> >>>>> #define ARM_SMMU_ICC_PEAK_BW_HIGH    UINT_MAX >>>>> >>>>> seems to be suitable here to reliably keep the bus active by BCM >>>>> for both Qualcomm and non-Qualcomm platforms (with some power penalty). >>>>> >>>>> LMK, if you feel otherwise. >>>> >>>> Shift it to the qcom instance or provide platform-specific values? (My >>>> preference would be towards the first solution). >>>> >>> >>> >>> To support platform-specific values, we may need to introduce a LUT-based approach in the driver. (Bandwidth voting values cannot be placed in device-tree property IIRC ?) >>> >>> Currently, all Qualcomm platforms use 0x1000 for SMMU ICC voting. I >> >> (you used decimal 1000) >> > > It's my bad, i meant 1000 only > (I'll check on the icc_bw calculation to get clarity on the values) > >>> can evaluate if this could be moved to a Qualcomm-specific >>> implementation. >> >> Add a vendor hook to arm_smmu_runtime_suspend/resume and handle it within >> the QC driver >> > > Just curious, wouldn't this apply for all the arm-smmu users in addition to Qualcomm devices as i mentioned here [1]. > Vendor hook would make it Qualcomm specific. You're proposing to use a Qualcomm-specific bandwidth value so that fits Konrad > > [1]: https://lore.kernel.org/all/984ff9c7-3eef-463c-a330-bf7acd063667@oss.qualcomm.com/ > > Thanks & regards, > Bibek > >> Konrad >