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Mon, 23 Jan 2023 03:03:17 -0800 (PST) Received: from [192.168.1.109] ([178.197.216.144]) by smtp.gmail.com with ESMTPSA id bg24-20020a05600c3c9800b003d9ed40a512sm14284884wmb.45.2023.01.23.03.03.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jan 2023 03:03:16 -0800 (PST) Message-ID: <4f0f8477-2a06-0e95-be32-0ec0f337a7fe@linaro.org> Date: Mon, 23 Jan 2023 12:03:14 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v4 09/12] dt-bindings: PCI: qcom: Add SM8550 compatible Content-Language: en-US To: Abel Vesa Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List References: <20230119140453.3942340-1-abel.vesa@linaro.org> <20230119140453.3942340-10-abel.vesa@linaro.org> <7af21247-a44e-cb46-7461-204fa6b4fcab@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 23/01/2023 11:44, Abel Vesa wrote: > On 23-01-22 15:10:59, Krzysztof Kozlowski wrote: >> On 19/01/2023 15:04, Abel Vesa wrote: >>> Add the SM8550 platform to the binding. >>> >>> Signed-off-by: Abel Vesa >>> --- >>> >>> The v3 of this patchset is: >>> https://lore.kernel.org/all/20230119112453.3393911-1-abel.vesa@linaro.org/ >>> >>> Changes since v3: >>> * renamed noc_aggr to noc_aggr_4, as found in the driver >>> >>> Changes since v2: >>> * dropped the pipe from clock-names >>> * removed the pcie instance number from aggre clock-names comment >>> * renamed aggre clock-names to noc_aggr >>> * dropped the _pcie infix from cnoc_pcie_sf_axi >>> * renamed pcie_1_link_down_reset to simply link_down >>> * added enable-gpios back, since pcie1 node will use it >>> >>> Changes since v1: >>> * Switched to single compatible for both PCIes (qcom,pcie-sm8550) >>> * dropped enable-gpios property >>> * dropped interconnects related properties, the power-domains >>> * properties >>> and resets related properties the sm8550 specific allOf:if:then >>> * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific >>> allOf:if:then clock-names array and decreased the minItems and >>> maxItems for clocks property accordingly >>> * added "minItems: 1" to interconnects, since sm8550 pcie uses just >>> * one, >>> same for interconnect-names >>> >>> >>> .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++++++++++++++++++ >>> 1 file changed, 44 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> index a5859bb3dc28..58f926666332 100644 >>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>> @@ -34,6 +34,7 @@ properties: >>> - qcom,pcie-sm8250 >>> - qcom,pcie-sm8450-pcie0 >>> - qcom,pcie-sm8450-pcie1 >>> + - qcom,pcie-sm8550 >>> - qcom,pcie-ipq6018 >>> >>> reg: >>> @@ -65,9 +66,11 @@ properties: >>> dma-coherent: true >>> >>> interconnects: >>> + minItems: 1 >>> maxItems: 2 >>> >> >> I don't see my concerns from v3 answered. > > Check the dates for v4 and your reply to v3. > > v4 was sent a day before you sent your v3 comments. :) > >> >> This is a friendly reminder during the review process. >> >> It seems my previous comments were not fully addressed. Maybe my >> feedback got lost between the quotes, maybe you just forgot to apply it. >> Please go back to the previous discussion and either implement all >> requested changes or keep discussing them. > > Will address your comments in next version. Ah, then ok :) Best regards, Krzysztof