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Tue, 20 Oct 2026 00:59:31 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c408e32897fsm456214766b.2.2026.10.20.00.59.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Oct 2026 00:59:30 -0700 (PDT) Message-ID: <4f586fa8-e7c1-42fd-b853-a2093e8a243b@oss.qualcomm.com> Date: Tue, 20 Oct 2026 09:59:27 +0200 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 00/13] Enable USB3 for Qualcomm IPQ5018 To: george.moussalem@outlook.com, Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Varadarajan Narayanan , Nitheesh Sekar , Wesley Cheng , Manivannan Sadhasivam , Varadarajan Narayanan Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Stanislaw Pal , Manivannan Sadhasivam , Krzysztof Kozlowski , Dmitry Baryshkov References: <20260908-ipq5018-usb3-v4-0-b789702f0695@outlook.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260908-ipq5018-usb3-v4-0-b789702f0695@outlook.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=DrrDa2/+ c=1 sm=1 tr=0 ts=6ad71f65 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=UqCG9HQmAAAA:8 a=C43bMXcMikSIT81_BHoA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDAzMSBTYWx0ZWRfX9MLJ/yvVa8jG pZaqAmchddwWk9ixfiO4rTApa+q2Yl4yo8rafYphceaPajjjsCNyATaUC1w5S30+qYkmWOtkyzr alnNBhGLJOA3dGpLhO+YC1RVhd6TKiywTxXCA5Ks7d787f0LMnJKlrB/I1IBk8ikWMho7vDTuSY WHbtLX759YkjDIkmUTJQ0dmtT1MmsPsaTnkUsOYkvjVCEti3XH1RTuyKPL5gP9nPM4fS7I83IKt XcHuzRlQaEcc4hElFL1fqnwHDP/ekyjOHxmS6qKFnfCeS36gqeXZp6DIIcZxF+ZLvU1ofd7OmGo T7GzPYhJXMZghULr2gYShoqCojO/Rz5VzBkhJTpVMij9var5YKahR5fEO6wBFRC1wwYASUqdBee X/b/8yvWbGGJGaXryLBQ2cTAs3DtD49fK8PRzNmAJDbKMSNu4NfdA8koUIzgOH7wN8i4UtDvn4K XFPYSAGfr7yk3414oLA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDAzMSBTYWx0ZWRfX5Nbcs5++c8L3 Q0WUmZXZeS6TAa3s9dK9lSDcjVICvJ3eURP6rrBBBWXQscc++6bN3zLWssZ8KW1wMCW6/NYW1xE 4WHslDZ9aP5L3tQbM+Z3JDmtzop83hY= X-Proofpoint-GUID: 4kRNM34DLo6Oq3YGOJsLGgv6o5UppTz8 X-Proofpoint-ORIG-GUID: 4kRNM34DLo6Oq3YGOJsLGgv6o5UppTz8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 suspectscore=0 bulkscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200031 On 9/8/26 11:40 AM, George Moussalem via B4 Relay wrote: > Patch series adds Qualcomm 22ull Super-Speed USB UNIPHY driver support > present in Qualcomm IPQ5018 and IPQ5332 SoC which is required to enable > USB3. This PHY is interfaced with SNPS DWC3 USB and SNPS DWC PCIe. > Either one of the interface can use it via the mux selection present in > the TCSR register. Current patch series adds the support for UNIPHY with > DWC3 USB. > > The series is now split into 3 parts: > 1. Flatten USB Controller Nodes on IPQ SoCs > link: https://lore.kernel.org/r/20260906-ipq-flatten-usb-v3-0-13e4e0f63123@outlook.com > 2. Enable USB3 for Qualcomm IPQ5018 (this patch series) > 3. Enable USB3 for Qualcomm IPQ5332 (to be submitted) > > --- > Changes in v4: [...] > - It's worth noting that I left the logic to register 1 phy in this > patch unchanged despite Konard's suggestion to register both > (PCIe and USB3) to avoid changing the existing binding for the > existing PCIe phy instances in ipq5018/ipq5332. Although the silicon > is capable of supporting both PCIe and USB3, the instances in scope > are wired for single mode only. The next patch set will register both > PCIe and USB3 PHYs for the combo PHY instance in IPQ5332 and use > #phy-cells to select the right PHY in the respective PCIe and USB3 > controller nodes. We need a bindings change either way, so might as well do it "right"! Konrad