Re: [PATCH 2/4] clk: qcom: rpmh: Add RPMH clocks support for SM4450

[neil.armstrong@linaro.org]

On 29/08/2023 07:51, Ajit Pandey wrote:
> 
> 
> On 8/25/2023 7:31 PM, Neil Armstrong wrote:
>> Hi,
>>
>> On 24/08/2023 19:34, Ajit Pandey wrote:
>>> Add support for RPMH clocks for SM4450 platform.
>>>
>>> Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
>>> ---
>>>   drivers/clk/qcom/clk-rpmh.c | 21 +++++++++++++++++++++
>>>   1 file changed, 21 insertions(+)
>>>
>>> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
>>> index 4c5b552b47b6..5d853fd43294 100644
>>> --- a/drivers/clk/qcom/clk-rpmh.c
>>> +++ b/drivers/clk/qcom/clk-rpmh.c
>>> @@ -350,6 +350,7 @@ DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a2, "lnbclka3", 2);
>>>   DEFINE_CLK_RPMH_VRM(ln_bb_clk1, _a4, "lnbclka1", 4);
>>>   DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _a4, "lnbclka2", 4);
>>> +DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _a4, "lnbclka3", 4);
>>>   DEFINE_CLK_RPMH_VRM(ln_bb_clk2, _g4, "lnbclkg2", 4);
>>>   DEFINE_CLK_RPMH_VRM(ln_bb_clk3, _g4, "lnbclkg3", 4);
>>> @@ -717,6 +718,25 @@ static const struct clk_rpmh_desc clk_rpmh_sdx75 = {
>>>       .num_clks = ARRAY_SIZE(sdx75_rpmh_clocks),
>>>   };
>>> +static struct clk_hw *sm4450_rpmh_clocks[] = {
>>> +    [RPMH_CXO_CLK]        = &clk_rpmh_bi_tcxo_div4.hw,
>>> +    [RPMH_CXO_CLK_A]    = &clk_rpmh_bi_tcxo_div4_ao.hw,
>>
>> Are you sure about div4 here ?
>>
>> Kailua uses div2 because the CXO input gets used divided by 2
>> by PHYs and divided by 4 for GCC/DISPCC/...
>>
>> This is why we introduced a div2 clock in DT used to feed GCC/DISPCC/...
>>
>> Neil
> 
> Yes div4 is the correct divider only for sm4450 as CXO input get directly divided by 4 only. This is someting similiar to sm8450 and there is no in between div2 divider like Kailua.

Ack, thx for checking !

Neil

> 
>>
>>> +    [RPMH_LN_BB_CLK2]    = &clk_rpmh_ln_bb_clk2_a4.hw,
>>> +    [RPMH_LN_BB_CLK2_A]    = &clk_rpmh_ln_bb_clk2_a4_ao.hw,
>>> +    [RPMH_LN_BB_CLK3]       = &clk_rpmh_ln_bb_clk3_a4.hw,
>>> +    [RPMH_LN_BB_CLK3_A]     = &clk_rpmh_ln_bb_clk3_a4_ao.hw,
>>> +    [RPMH_RF_CLK1]        = &clk_rpmh_rf_clk1_a.hw,
>>> +    [RPMH_RF_CLK1_A]    = &clk_rpmh_rf_clk1_a_ao.hw,
>>> +    [RPMH_RF_CLK5]        = &clk_rpmh_rf_clk5_a.hw,
>>> +    [RPMH_RF_CLK5_A]    = &clk_rpmh_rf_clk5_a_ao.hw,
>>> +    [RPMH_IPA_CLK]        = &clk_rpmh_ipa.hw,
>>> +};
>>> +
>>> +static const struct clk_rpmh_desc clk_rpmh_sm4450 = {
>>> +    .clks = sm4450_rpmh_clocks,
>>> +    .num_clks = ARRAY_SIZE(sm4450_rpmh_clocks),
>>> +};
>>> +
>>>   static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
>>>                        void *data)
>>>   {
>>> @@ -810,6 +830,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
>>>       { .compatible = "qcom,sdx55-rpmh-clk",  .data = &clk_rpmh_sdx55},
>>>       { .compatible = "qcom,sdx65-rpmh-clk",  .data = &clk_rpmh_sdx65},
>>>       { .compatible = "qcom,sdx75-rpmh-clk",  .data = &clk_rpmh_sdx75},
>>> +    { .compatible = "qcom,sm4450-rpmh-clk", .data = &clk_rpmh_sm4450},
>>>       { .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
>>>       { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
>>>       { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
>>