Re: [PATCH v5 13/16] can: grcan: Add CANFD TX support alongside legacy CAN

[Vincent Mailhol <mailhol@kernel.org>]

On 16/02/2026 at 14:53, Arun Muthusamy wrote:
> Include CANFD TX support with the legacy CAN support, enabling
> support for extended data payloads to provide higher bit rates.
> 
> Signed-off-by: Arun Muthusamy <arun.muthusamy@gaisler.com>
> ---
>  drivers/net/can/grcan.c | 111 ++++++++++++++++++++++++++++++----------
>  1 file changed, 85 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/net/can/grcan.c b/drivers/net/can/grcan.c
> index 28fa219e1c3b..ae9f6fd4c8bf 100644
> --- a/drivers/net/can/grcan.c
> +++ b/drivers/net/can/grcan.c
> @@ -196,6 +196,10 @@ struct grcan_registers {
>  #define GRCAN_MSG_OFF		0x00000002
>  #define GRCAN_MSG_PASS		0x00000001
>  
> +#define GRCAN_MSG_EID_MASK      GENMASK(28, 0)
> +#define GRCAN_MSG_BID_MASK      GENMASK(28, 18)
> +#define GRCAN_MSG_DLC_MASK      GENMASK(31, 28)
> +
>  #define GRCAN_BUFFER_ALIGNMENT		1024
>  #define GRCAN_DEFAULT_BUFFER_SIZE	1024
>  #define GRCAN_VALID_TR_SIZE_MASK	0x001fffc0
> @@ -228,6 +232,9 @@ struct grcan_registers {
>  #define GRCANFD_FDBTR_PS2_BIT 5
>  #define GRCANFD_FDBTR_SJW_BIT 0
>  
> +#define GRCAN_TX_BRS  BIT(25)
> +#define GRCAN_TX_FDF  BIT(26)
> +
>  /* Hardware capabilities */
>  struct grcan_hwcap {
>  	/* CAN-FD capable, indicates GRCANFD IP.
> @@ -1222,6 +1229,19 @@ static void grcan_transmit_catch_up(struct net_device *dev)
>  	spin_unlock_irqrestore(&priv->lock, flags);
>  }
>  
> +static int grcan_numbds(int len)
> +{
> +	if (len <= GRCAN_CLASSIC_DATA_SIZE)
> +		return 1;
> +
> +	return 1 + DIV_ROUND_UP(len - GRCAN_CLASSIC_DATA_SIZE, GRCAN_MSG_SIZE);
> +}
> +
> +static inline union grcan_msg_slot *grcan_tx_msg_slot(struct grcan_dma *dma, u32 off)
> +{
> +	return (union grcan_msg_slot *)((u8 *)dma->tx.msg_slot + off);
> +}
> +
>  static int grcan_receive(struct net_device *dev, int budget)
>  {
>  	struct grcan_priv *priv = netdev_priv(dev);
> @@ -1404,15 +1424,23 @@ static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
>  				    struct net_device *dev)
>  {
>  	struct grcan_priv *priv = netdev_priv(dev);
> -	struct grcan_registers __iomem *regs = priv->regs;
> +	struct grcan_registers __iomem *regs;
> +	u32 eff, rtr, dlc, tmp, err, can_id;
>  	struct grcan_dma *dma = &priv->dma;
> -	struct can_frame *cf = (struct can_frame *)skb->data;
> +	u32 bds, copy_len, payload_offset;
>  	u32 id, txwr, txrd, space, txctrl;
> -	int slotindex;
> -	u32 *slot;

All the slot refactor is not part of adding CANFD support. It should
be squashed in previous patch:

  can: grcan: Refactor GRCAN DMA buffer to use structured memory layout

As a result, it is hard to understand which part of this patch is
related to struct grcan_dma_buffer refactor and which part is the
introduction of the new CAN FD feature.

> -	u32 rtr, eff, dlc, tmp, err;
> +	union grcan_msg_slot *msg;
> +	struct canfd_frame *cfd;
> +	struct can_frame *cf;
>  	unsigned long flags;
> -	u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
> +	u32 oneshotmode;
> +	int slotindex;
> +	u8 *payload;
> +	u8 len;
> +	int i;
> +
> +	regs = priv->regs;
> +	oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
>  
>  	if (can_dev_dropped_skb(dev, skb))
>  		return NETDEV_TX_OK;
> @@ -1423,6 +1451,18 @@ static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
>  	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
>  		return NETDEV_TX_BUSY;
>  
> +	cfd = (struct canfd_frame *)skb->data;
> +	len = cfd->len;
> +	can_id  = cfd->can_id;
> +	payload = cfd->data;
> +
> +	if (can_is_canfd_skb(skb)) {
> +		dlc = can_fd_len2dlc(len);
> +	} else {
> +		cf = (struct can_frame *)skb->data;
> +		dlc = can_get_cc_dlc(cf, priv->can.ctrlmode);
> +	}
> +
>  	/* Reads of priv->eskbp and shut-downs of the queue needs to
>  	 * be atomic towards the updates to priv->eskbp and wake-ups
>  	 * of the queue in the interrupt handler.
> @@ -1433,7 +1473,7 @@ static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
>  	space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
>  
>  	slotindex = txwr / GRCAN_MSG_SIZE;
> -	slot = (u32 *)((u8 *)dma->tx.msg_slot + txwr);
> +	bds = grcan_numbds(len);
>  
>  	if (unlikely(space == 1))
>  		netif_stop_queue(dev);
> @@ -1449,24 +1489,44 @@ static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
>  		return NETDEV_TX_BUSY;
>  	}
>  
> -	/* Convert and write CAN message to DMA buffer */
> -	eff = cf->can_id & CAN_EFF_FLAG;
> -	rtr = cf->can_id & CAN_RTR_FLAG;
> -	id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
> -	dlc = cf->len;
> -	if (eff)
> -		tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
> -	else
> -		tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
> -	slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
> +	msg = grcan_tx_msg_slot(dma, txwr);
> +	memset(msg, 0, sizeof(*msg));
> +
> +	eff = can_id & CAN_EFF_FLAG;
> +	rtr = can_id & CAN_RTR_FLAG;
> +	id  = can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
> +
> +	tmp = eff ? FIELD_PREP(GRCAN_MSG_EID_MASK, id)
> +		  : FIELD_PREP(GRCAN_MSG_BID_MASK, id);
> +
> +	msg->header.id = (eff ? GRCAN_MSG_IDE : 0) |
> +		      (rtr ? GRCAN_MSG_RTR : 0) |
> +		      tmp;
>  
> -	slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
> -	slot[2] = 0;
> -	slot[3] = 0;
> -	if (dlc > 0)
> -		memcpy(&slot[2], cf->data, sizeof(u32));
> -	if (dlc > 4)
> -		memcpy(&slot[3], cf->data + 4, sizeof(u32));

You introduced this in patch #5:

  can: grcan: optimize DMA by 32-bit accesses

to just remove it here. Please rework your series. You shouldn't undo
what you previously introduced. If patch #8 becomes unneeded, just drop
it.

> +	msg->header.ctrl = FIELD_PREP(GRCAN_MSG_DLC_MASK, dlc);
> +
> +	if (can_is_canfd_skb(skb)) {
> +		msg->header.ctrl |= GRCAN_TX_FDF;
> +		if (cfd->flags & CANFD_BRS)
> +			msg->header.ctrl |= GRCAN_TX_BRS;
> +	}
> +
> +	copy_len = min_t(u32, len, GRCAN_CLASSIC_DATA_SIZE);
> +	memcpy(msg->header.data, payload, copy_len);
> +	payload_offset = copy_len;
> +
> +	txwr = grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size);
> +
> +	for (i = 1; i < bds; i++) {
> +		msg = grcan_tx_msg_slot(dma, txwr);
> +
> +		memset(msg, 0, sizeof(*msg));
> +		copy_len = min_t(u32, (u32)len - payload_offset, (u32)GRCAN_MSG_SIZE);
> +		memcpy(msg->frags.data, payload + payload_offset, copy_len);
> +		payload_offset += copy_len;
> +
> +		txwr = grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size);
> +	}
>  
>  	/* Checking that channel has not been disabled. These cases
>  	 * should never happen
> @@ -1508,8 +1568,7 @@ static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
>  	wmb();
>  
>  	/* Update write pointer to start transmission */
> -	grcan_write_reg(&regs->txwr,
> -			grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
> +	grcan_write_reg(&regs->txwr, txwr);
>  
>  	return NETDEV_TX_OK;
>  }


Yours sincerely,
Vincent Mailhol