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([fe80::2c4e:e92a:4fa:a456]) by IA1PR11MB7198.namprd11.prod.outlook.com ([fe80::2c4e:e92a:4fa:a456%3]) with mapi id 15.20.9870.023; Tue, 5 May 2026 09:51:54 +0000 Message-ID: <5002f40e-9b8e-4454-81c8-986dbb0768b6@intel.com> Date: Tue, 5 May 2026 12:51:49 +0300 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] mmc: cqe: Add CQE support for cadence mmc driver To: , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Masahiro Yamada CC: , , , Milind Parab , "Swapnil Jakhade" , Manikandan Pillai References: <20260407-cdns_sdhci_cqe-support-v1-0-13efc0810631@cadence.com> <20260407-cdns_sdhci_cqe-support-v1-2-13efc0810631@cadence.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20260407-cdns_sdhci_cqe-support-v1-2-13efc0810631@cadence.com> Content-Type: text/plain; charset="UTF-8" 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=?utf-8?B?bUZ1UHFBQVJwV3pla3FVWHhNMEVVWFdPSkJMN3pHaythTzlvV0hCWW0xNGd3?= =?utf-8?Q?OCdKSYjDLz/9HZQo=3D?= X-Exchange-RoutingPolicyChecked: V4hHeqC8FFDMWVq+uR6jdYjUJbsQXFPBJsgffqoOFsxVRibqoSbnjnPTpRfaxTs0RNEJwI6yQpJKi7i0Mqlr3yW10gmcZoAmlhL8yBmyp3AA3MjzobeAWKNTwe5LxTXcm9FBT9fmmqLrQLrkw1GFesXcHAhDl+zG6ntwm4NNraPQmwJXVjgMvm4+iuxjwVmUkDRTmWrtcJW1xiGdKaB60aGy5e4P4Nik1QF+YTrzIsR3ixRVjvlR85uiTJ6bPVrrG1Hz4zXHsfTwCiaRVqAqOUxeGEFP9GYmbUH0uXU6EqxfDQjPbg/dhJgWSiNsdEN/NQYuHPlguy8hWLXP0oy9Xw== X-MS-Exchange-CrossTenant-Network-Message-Id: 2ab3e5f9-0988-41d4-6654-08deaa8bf091 X-MS-Exchange-CrossTenant-AuthSource: IA1PR11MB7198.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2026 09:51:54.8786 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FTchYZiJ5qIG4aORKDlia//yEwOwXcUJZY5Ylr2KjwoYw4u5XF3U3nGQywM+Q8iSvPGm7XK9+qcjiM5xPOa4HQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4559 X-OriginatorOrg: intel.com On 07/04/2026 14:18, rohan1sj via B4 Relay wrote: > From: rohan1sj > > Add Command Queuing Engine (CQE) support for cadence driver > > Signed-off-by: rohan1sj > --- > drivers/mmc/host/sdhci-cadence.c | 118 ++++++++++++++++++++++++++++++++++++++- > 1 file changed, 115 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c > index 435603c8c00b..14b12272dae9 100644 > --- a/drivers/mmc/host/sdhci-cadence.c > +++ b/drivers/mmc/host/sdhci-cadence.c > @@ -15,6 +15,8 @@ > #include > > #include "sdhci-pltfm.h" > +#include "sdhci-cqhci.h" > +#include "cqhci.h" Also need to select MMC_CQHCI in Kconfig for MMC_SDHCI_CADENCE > > /* HRS - Host Register Set (specific to Cadence) */ > #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ > @@ -36,6 +38,10 @@ > #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5 > #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6 > > +/* Host capabilities not covered by the standard capability registers (SRS16-SRS18) */ > +#define SDHCI_CDNS_HRS30 0x78 /* Host capabilities */ > +#define SDHCI_CDNS_HRS30_CQE_SUPPORTED BIT(0) > + > /* Read block gap */ > #define SDHCI_CDNS_HRS37 0x94 /* interface mode select */ > #define SDHCI_CDNS_HRS37_MODE_DS 0x0 > @@ -88,6 +94,7 @@ struct sdhci_cdns_priv { > void __iomem *ctl_addr; /* write control */ > spinlock_t wrlock; /* write lock */ > bool enhanced_strobe; > + bool cqe_support; /* Command Queuing Engine support */ > void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); > struct reset_control *rst_hw; > unsigned int nr_phy_params; > @@ -385,6 +392,73 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, > sdhci_set_uhs_signaling(host, timing); > } > > +static u32 sdhci_cdns_cqhci_irq(struct sdhci_host *host, u32 intmask) > +{ > + int cmd_err = 0; > + int data_err = 0; > + > + /* return original intmask to be handled by other handlers if it's not a CQE interrupt */ > + if (!sdhci_cqe_irq(host, intmask, &cmd_err, &data_err)) > + return intmask; > + > + cqhci_irq(host->mmc, intmask, cmd_err, data_err); > + > + return 0; > +} > + > +static const struct cqhci_host_ops sdhci_cdns_cqhci_ops = { > + .enable = sdhci_cqe_enable, > + .disable = sdhci_cqe_disable, > +}; > + > +static int sdhci_cdns_cqe_add_host(struct sdhci_host *host, struct platform_device *pdev) > +{ > + struct cqhci_host *cq_host; > + bool dma64; > + int ret; > + > + /* setup SDHCI host first */ > + ret = sdhci_setup_host(host); > + Unnecessary blank line > + if (ret) > + return ret; > + > + /* Init CQE */ > + cq_host = cqhci_pltfm_init(pdev); > + if (IS_ERR(cq_host)) { > + ret = PTR_ERR(cq_host); > + goto cleanup; > + } > + > + dma64 = host->flags & SDHCI_USE_64_BIT_DMA; > + if (dma64) > + cq_host->caps |= CQHCI_TASK_DESC_SZ_128; > + > + cq_host->ops = &sdhci_cdns_cqhci_ops; > + > + host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; > + > + /* Finally initialize CQHCI */ > + ret = cqhci_init(cq_host, host->mmc, dma64); > + if (ret) { > + dev_err(mmc_dev(host->mmc), "Failed to initialize CQHCI: %d\n", ret); > + goto cleanup; > + } > + > + /* add host to MMC subsystem */ > + ret = __sdhci_add_host(host); > + if (ret) > + goto cleanup; > + > + dev_info(mmc_dev(host->mmc), "CQE init: success\n"); > + return 0; > + > +cleanup: > + dev_err(mmc_dev(host->mmc), "CQE init: failed for %s\n", mmc_hostname(host->mmc)); > + sdhci_cleanup_host(host); > + return ret; > +} > + > /* Elba control register bits [6:3] are byte-lane enables */ > #define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) > > @@ -474,9 +548,10 @@ static const struct sdhci_ops sdhci_cdns_ops = { > .set_clock = sdhci_set_clock, > .get_timeout_clock = sdhci_cdns_get_timeout_clock, > .set_bus_width = sdhci_set_bus_width, > - .reset = sdhci_reset, > + .reset = sdhci_and_cqhci_reset, > .platform_execute_tuning = sdhci_cdns_execute_tuning, > .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, > + .irq = sdhci_cdns_cqhci_irq, > }; sdhci_elba_ops is unchanged, so presumably doesn't support CQE. However, the commit message should say something about that so that it is clear that it is deliberate. > > static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { > @@ -553,6 +628,8 @@ static int sdhci_cdns_probe(struct platform_device *pdev) > int ret; > struct device *dev = &pdev->dev; > static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT; > + bool cqe_enabled; > + u32 host_caps; > > clk = devm_clk_get_enabled(dev, NULL); > if (IS_ERR(clk)) > @@ -608,7 +685,35 @@ static int sdhci_cdns_probe(struct platform_device *pdev) > host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset; > } > > - return sdhci_add_host(host); > + host_caps = readl(priv->hrs_addr + SDHCI_CDNS_HRS30); > + cqe_enabled = host_caps & SDHCI_CDNS_HRS30_CQE_SUPPORTED; > + > + if (cqe_enabled) { > + priv->cqe_support = true; > + ret = sdhci_cdns_cqe_add_host(host, pdev); > + } else { > + ret = sdhci_add_host(host); > + } > + > + return ret; > +} > + > +static int sdhci_cdns_suspend(struct device *dev) > +{ > + struct sdhci_host *host = dev_get_drvdata(dev); > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host); > + int ret; > + > + if (priv->cqe_support) { > + ret = cqhci_suspend(host->mmc); > + if (ret) > + return ret; > + } > + > + ret = sdhci_pltfm_suspend(dev); > + > + return ret; > } > > static int sdhci_cdns_resume(struct device *dev) > @@ -630,6 +735,13 @@ static int sdhci_cdns_resume(struct device *dev) > if (ret) > goto disable_clk; > > + /* Resume CQE if enabled */ > + if (priv->cqe_support) { > + ret = cqhci_resume(host->mmc); > + if (ret) > + goto disable_clk; > + } > + > return 0; > > disable_clk: > @@ -638,7 +750,7 @@ static int sdhci_cdns_resume(struct device *dev) > return ret; > } > > -static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_pltfm_suspend, sdhci_cdns_resume); > +static DEFINE_SIMPLE_DEV_PM_OPS(sdhci_cdns_pm_ops, sdhci_cdns_suspend, sdhci_cdns_resume); > > static const struct of_device_id sdhci_cdns_match[] = { > { >