[PATCH v4 3/6] tegra: fdt: Add NAND controller binding and definitions

[PATCH v4 3/6] tegra: fdt: Add NAND controller binding and definitions

[Simon Glass]

Add a NAND controller along with a bindings file for review.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Update NAND binding to add "nvidia," prefix

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Change note in fdt binding about the need for a hardware-specific binding
- Fix up typos in fdt binding, and rename the file
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Remove fdt bindings related to page structure

 arch/arm/dts/tegra20.dtsi                          |    7 +++
 .../nand/nvidia,tegra20-nand.txt                   |   53 ++++++++++++++++++++
 2 files changed, 60 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index f95be58..d936b1e 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -204,4 +204,11 @@
 		compatible = "nvidia,tegra20-kbc";
 		reg = <0x7000e200 0x0078>;
 	};
+
+	nand: nand-controller@70008000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nvidia,tegra20-nand";
+		reg = <0x70008000 0x100>;
+	};
 };
diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
new file mode 100644
index 0000000..86ae408
--- /dev/null
+++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
@@ -0,0 +1,53 @@
+NAND Flash
+----------
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot. There should not be Linux-specific or U-Boot specific binding, just
+a binding that describes this hardware. But agreeing a binding in Linux in
+the absence of a driver may be beyond my powers.)
+
+The device node for a NAND flash device is as follows:
+
+Required properties :
+ - compatible : Should be "manufacturer,device", "nand-flash"
+
+This node should sit inside its controller.
+
+
+Nvidia NAND Controller
+----------------------
+
+The device node for a NAND flash controller is as follows:
+
+Optional properties:
+
+nvidia,wp-gpios : GPIO of write-protect line, three cells in the format:
+		phandle, parameter, flags
+nvidia,nand-width : bus width of the NAND device in bits
+
+ - nvidia,nand-timing : Timing parameters for the NAND. Each is in ns.
+	Order is: MAX_TRP_TREA, TWB, Max(tCS, tCH, tALS, tALH),
+	TWHR, Max(tCS, tCH, tALS, tALH), TWH, TWP, TRH, TADL
+
+	MAX_TRP_TREA is:
+		non-EDO mode: Max(tRP, tREA) + 6ns
+		EDO mode: tRP timing
+
+The 'reg' property should provide the chip select used by the flash chip.
+
+
+Example
+-------
+
+nand-controller@0x70008000 {
+	compatible = "nvidia,tegra20-nand";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+	nvidia,nand-width = <8>;
+	nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+	nand@0 {
+		reg = <0>;
+		compatible = "hynix,hy27uf4g2b", "nand-flash";
+	};
+};
-- 
1.7.7.3

[PATCH v4 4/6] tegra: fdt: Add NAND definitions to fdt

[Simon Glass]

Add a flash node to handle the NAND, including memory timings and
page / block size information.

Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v2:
- Update NAND binding to add "nvidia," prefix

Changes in v3:
- Add reg property for unit address (should be used for chip select)
- Update fdt binding to make everything Nvidia-specific

Changes in v4:
- Remove fdt bindings related to page structure

 board/nvidia/dts/tegra20-seaboard.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index 3352539..25a63a0 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -153,4 +153,14 @@
 			0x1f04008a>;
 		linux,fn-keymap = <0x05040002>;
 	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };
-- 
1.7.7.3

Re: [PATCH v4 4/6] tegra: fdt: Add NAND definitions to fdt

[Scott Wood]

On 07/30/2012 01:53 AM, Simon Glass wrote:
> Add a flash node to handle the NAND, including memory timings and
> page / block size information.
> 
> Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> Changes in v2:
> - Update NAND binding to add "nvidia," prefix
> 
> Changes in v3:
> - Add reg property for unit address (should be used for chip select)
> - Update fdt binding to make everything Nvidia-specific
> 
> Changes in v4:
> - Remove fdt bindings related to page structure
> 
>  board/nvidia/dts/tegra20-seaboard.dts |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
> index 3352539..25a63a0 100644
> --- a/board/nvidia/dts/tegra20-seaboard.dts
> +++ b/board/nvidia/dts/tegra20-seaboard.dts
> @@ -153,4 +153,14 @@
>  			0x1f04008a>;
>  		linux,fn-keymap = <0x05040002>;
>  	};
> +
> +	nand-controller@70008000 {
> +		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
> +		nvidia,width = <8>;
> +		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
> +		nand@0 {
> +			reg = <0>;
> +			compatible = "hynix,hy27uf4g2b", "nand-flash";
> +		};
> +	};

Are #address-cells, #size-cells, and reg on the controller node provided
by an /include/?

-Scott

Re: [PATCH v4 3/6] tegra: fdt: Add NAND controller binding and definitions

[Scott Wood]

On 07/30/2012 01:53 AM, Simon Glass wrote:
> diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
> index f95be58..d936b1e 100644
> --- a/arch/arm/dts/tegra20.dtsi
> +++ b/arch/arm/dts/tegra20.dtsi
> @@ -204,4 +204,11 @@
>  		compatible = "nvidia,tegra20-kbc";
>  		reg = <0x7000e200 0x0078>;
>  	};
> +
> +	nand: nand-controller@70008000 {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "nvidia,tegra20-nand";
> +		reg = <0x70008000 0x100>;
> +	};
>  };
> diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
> new file mode 100644
> index 0000000..86ae408
> --- /dev/null
> +++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
> @@ -0,0 +1,53 @@
> +NAND Flash
> +----------
> +
> +(there isn't yet a generic binding in Linux, so this describes what is in
> +U-Boot. There should not be Linux-specific or U-Boot specific binding, just
> +a binding that describes this hardware. But agreeing a binding in Linux in
> +the absence of a driver may be beyond my powers.)

Please at least attempt to get a binding accepted in Linux, or perhaps
in a neutral repository such as devicetree.org (but point out on
devicetree-discuss that you've posted it there).  The device tree is
supposed to describe the hardware, not what Linux currently uses.

> +Example
> +-------
> +
> +nand-controller@0x70008000 {
> +	compatible = "nvidia,tegra20-nand";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
> +	nvidia,nand-width = <8>;
> +	nvidia,timing = <26 100 20 80 20 10 12 10 70>;
> +	nand@0 {
> +		reg = <0>;
> +		compatible = "hynix,hy27uf4g2b", "nand-flash";
> +	};
> +};

Where is "reg" in the parent node?  You're not supposed to have a unit
address without reg.   Also, most bus bindings don't put 0x in the unit
address).

I see that it's OK in the actual .dtsi -- it's just the example that
needs fixing.

-Scott

Re: [PATCH v4 4/6] tegra: fdt: Add NAND definitions to fdt

[Simon Glass]

Hi Scott,

On Mon, Jul 30, 2012 at 11:49 PM, Scott Wood <scottwood-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:
> On 07/30/2012 01:53 AM, Simon Glass wrote:
>> Add a flash node to handle the NAND, including memory timings and
>> page / block size information.
>>
>> Signed-off-by: Simon Glass <sjg-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>> ---
>> Changes in v2:
>> - Update NAND binding to add "nvidia," prefix
>>
>> Changes in v3:
>> - Add reg property for unit address (should be used for chip select)
>> - Update fdt binding to make everything Nvidia-specific
>>
>> Changes in v4:
>> - Remove fdt bindings related to page structure
>>
>>  board/nvidia/dts/tegra20-seaboard.dts |   10 ++++++++++
>>  1 files changed, 10 insertions(+), 0 deletions(-)
>>
>> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
>> index 3352539..25a63a0 100644
>> --- a/board/nvidia/dts/tegra20-seaboard.dts
>> +++ b/board/nvidia/dts/tegra20-seaboard.dts
>> @@ -153,4 +153,14 @@
>>                       0x1f04008a>;
>>               linux,fn-keymap = <0x05040002>;
>>       };
>> +
>> +     nand-controller@70008000 {
>> +             nvidia,wp-gpios = <&gpio 59 0>;         /* PH3 */
>> +             nvidia,width = <8>;
>> +             nvidia,timing = <26 100 20 80 20 10 12 10 70>;
>> +             nand@0 {
>> +                     reg = <0>;
>> +                     compatible = "hynix,hy27uf4g2b", "nand-flash";
>> +             };
>> +     };
>
> Are #address-cells, #size-cells, and reg on the controller node provided
> by an /include/?

Yes that's right, in the previous patch:

	nand: nand-controller@70008000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "nvidia,tegra20-nand";
		reg = <0x70008000 0x100>;
	};

Regards,
Simon

>
> -Scott
>
>

Re: [PATCH v4 3/6] tegra: fdt: Add NAND controller binding and definitions

[Simon Glass]

Hi Scott,

On Tue, Jul 31, 2012 at 12:05 AM, Scott Wood <scottwood-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:
> On 07/30/2012 01:53 AM, Simon Glass wrote:
>> diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
>> index f95be58..d936b1e 100644
>> --- a/arch/arm/dts/tegra20.dtsi
>> +++ b/arch/arm/dts/tegra20.dtsi
>> @@ -204,4 +204,11 @@
>>               compatible = "nvidia,tegra20-kbc";
>>               reg = <0x7000e200 0x0078>;
>>       };
>> +
>> +     nand: nand-controller@70008000 {
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +             compatible = "nvidia,tegra20-nand";
>> +             reg = <0x70008000 0x100>;
>> +     };
>>  };
>> diff --git a/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
>> new file mode 100644
>> index 0000000..86ae408
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt
>> @@ -0,0 +1,53 @@
>> +NAND Flash
>> +----------
>> +
>> +(there isn't yet a generic binding in Linux, so this describes what is in
>> +U-Boot. There should not be Linux-specific or U-Boot specific binding, just
>> +a binding that describes this hardware. But agreeing a binding in Linux in
>> +the absence of a driver may be beyond my powers.)
>
> Please at least attempt to get a binding accepted in Linux, or perhaps
> in a neutral repository such as devicetree.org (but point out on
> devicetree-discuss that you've posted it there).  The device tree is
> supposed to describe the hardware, not what Linux currently uses.
>
>> +Example
>> +-------
>> +
>> +nand-controller@0x70008000 {
>> +     compatible = "nvidia,tegra20-nand";
>> +     #address-cells = <1>;
>> +     #size-cells = <0>;
>> +     nvidia,wp-gpios = <&gpio 59 0>;         /* PH3 */
>> +     nvidia,nand-width = <8>;
>> +     nvidia,timing = <26 100 20 80 20 10 12 10 70>;
>> +     nand@0 {
>> +             reg = <0>;
>> +             compatible = "hynix,hy27uf4g2b", "nand-flash";
>> +     };
>> +};
>
> Where is "reg" in the parent node?  You're not supposed to have a unit
> address without reg.   Also, most bus bindings don't put 0x in the unit
> address).
>
> I see that it's OK in the actual .dtsi -- it's just the example that
> needs fixing.

OK I will fix these and send a new patch.

Regards,
Simon

>
> -Scott
>
>