* [PATCH 00/14] Support more devices on rockchip rv1108
@ 2017-07-31 10:04 Andy Yan
2017-07-31 10:08 ` [PATCH 02/14] clk: rockchip: support more clks for rv1108 Andy Yan
` (4 more replies)
0 siblings, 5 replies; 26+ messages in thread
From: Andy Yan @ 2017-07-31 10:04 UTC (permalink / raw)
To: heiko
Cc: devicetree, linus.walleij, mturquette, linux-gpio, sboyd, broonie,
linux-clk, linux-kernel, wsa, linux-rockchip, robh+dt, linux-i2c,
shawn.lin, linux-spi, zhangqing, linux-arm-kernel, Andy Yan
This series try to support i2c/spi/pwm/saradc/pmic/watchdog and
the full clk tree on rockchip rv1108 soc.
Andy Yan (12):
pinctrl: rockchip: add input schmitt support for rv1108
dt-bindings: i2c: rk3x: add support for rv1108
i2c: rk3x: add support for rv1108
ARM: dts: rockchip: add i2c dt node for rv1108
spi: rockchip: add compatible string for rv1108 spi
ARM: dts: rockchip: add spi dt node for rv1108
ARM: dts: rockchip: add pwm dt node for rv1108
ARM: dts: rockchip: add watchdog dt node for rv1108
ARM: dts: rockchip: add saradc support for rv1108
ARM: dts: rockchip: add pwm backlight for rv1108 evb
ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
Elaine Zhang (2):
clk: rockchip: add more clk ids for rv1108
clk: rockchip: support more clks for rv1108
Documentation/devicetree/bindings/i2c/i2c-rk3x.txt | 1 +
.../devicetree/bindings/spi/spi-rockchip.txt | 1 +
arch/arm/boot/dts/rv1108-evb.dts | 158 +++++++
arch/arm/boot/dts/rv1108.dtsi | 249 ++++++++++
drivers/clk/rockchip/clk-rv1108.c | 513 ++++++++++++++++-----
drivers/i2c/busses/i2c-rk3x.c | 9 +
drivers/pinctrl/pinctrl-rockchip.c | 31 ++
drivers/spi/spi-rockchip.c | 1 +
include/dt-bindings/clock/rv1108-cru.h | 128 ++++-
9 files changed, 964 insertions(+), 127 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH 02/14] clk: rockchip: support more clks for rv1108 2017-07-31 10:04 [PATCH 00/14] Support more devices on rockchip rv1108 Andy Yan @ 2017-07-31 10:08 ` Andy Yan 2017-07-31 23:31 ` Heiko Stuebner 2017-07-31 10:10 ` [PATCH 03/14] pinctrl: rockchip: add input schmitt support " Andy Yan ` (3 subsequent siblings) 4 siblings, 1 reply; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:08 UTC (permalink / raw) To: heiko Cc: devicetree, linux-clk, linux-kernel, linux-rockchip, robh+dt, shawn.lin, zhangqing, mturquette, sboyd, linux-arm-kernel, Andy Yan From: Elaine Zhang <zhangqing@rock-chips.com> 1. Added the description of the missing clock, make the clock more complete. 2. fix up some clk descriptions error. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Andy Yan <andy.yan@rock-chips.com> --- drivers/clk/rockchip/clk-rv1108.c | 513 ++++++++++++++++++++++++++++++-------- 1 file changed, 405 insertions(+), 108 deletions(-) diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c index 7c05ab3..8d9cb2f 100644 --- a/drivers/clk/rockchip/clk-rv1108.c +++ b/drivers/clk/rockchip/clk-rv1108.c @@ -93,9 +93,24 @@ static struct rockchip_pll_rate_table rv1108_pll_rates[] = { } static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = { - RV1108_CPUCLK_RATE(816000000, 4), - RV1108_CPUCLK_RATE(600000000, 4), - RV1108_CPUCLK_RATE(312000000, 4), + RV1108_CPUCLK_RATE(1608000000, 7), + RV1108_CPUCLK_RATE(1512000000, 7), + RV1108_CPUCLK_RATE(1488000000, 5), + RV1108_CPUCLK_RATE(1416000000, 5), + RV1108_CPUCLK_RATE(1392000000, 5), + RV1108_CPUCLK_RATE(1296000000, 5), + RV1108_CPUCLK_RATE(1200000000, 5), + RV1108_CPUCLK_RATE(1104000000, 5), + RV1108_CPUCLK_RATE(1008000000, 5), + RV1108_CPUCLK_RATE(912000000, 5), + RV1108_CPUCLK_RATE(816000000, 3), + RV1108_CPUCLK_RATE(696000000, 3), + RV1108_CPUCLK_RATE(600000000, 3), + RV1108_CPUCLK_RATE(500000000, 3), + RV1108_CPUCLK_RATE(408000000, 1), + RV1108_CPUCLK_RATE(312000000, 1), + RV1108_CPUCLK_RATE(216000000, 1), + RV1108_CPUCLK_RATE(96000000, 1), }; static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { @@ -105,7 +120,7 @@ static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { .mux_core_alt = 1, .mux_core_main = 0, .mux_core_shift = 8, - .mux_core_mask = 0x1, + .mux_core_mask = 0x3, }; PNAME(mux_pll_p) = { "xin24m", "xin24m"}; @@ -114,30 +129,42 @@ PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" }; PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; -PNAME(mux_pll_src_4plls_p) = { "dpll", "hdmiphy", "gpll", "usb480m" }; +PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" }; PNAME(mux_pll_src_3plls_p) = { "apll", "gpll", "dpll" }; PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" }; PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" }; -PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_dpll", "aclk_peri_src_gpll" }; +PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" }; PNAME(mux_aclk_bus_src_p) = { "aclk_bus_src_gpll", "aclk_bus_src_apll", "aclk_bus_src_dpll" }; PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" }; PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" }; PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; -PNAME(mux_sclk_macphy_p) = { "sclk_macphy_pre", "ext_gmac" }; +PNAME(mux_sclk_macphy_p) = { "ext_gmac", "sclk_macphy_pre" }; PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; -PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" }; -PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; +PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" }; +PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "dummy", "xin12m" }; +PNAME(mux_wifi_src_p) = { "gpll", "xin24m" }; +PNAME(mux_cifout_src_p) = { "hdmiphy", "gpll" }; +PNAME(mux_cifout_p) = { "sclk_cifout_src", "xin24m" }; +PNAME(mux_sclk_cif0_src_p) = { "pclk_vip", "clk_cif0_chn_out", "pclkin_cvbs2cif" }; +PNAME(mux_sclk_cif1_src_p) = { "pclk_vip", "clk_cif1_chn_out", "pclkin_cvbs2cif" }; +PNAME(mux_sclk_cif2_src_p) = { "pclk_vip", "clk_cif2_chn_out", "pclkin_cvbs2cif" }; +PNAME(mux_sclk_cif3_src_p) = { "pclk_vip", "clk_cif3_chn_out", "pclkin_cvbs2cif" }; +PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" }; +PNAME(mux_dclk_hdmiphy_p) = { "hdmiphy", "xin24m" }; +PNAME(mux_dclk_vop_p) = { "dclk_hdmiphy", "dclk_vop_src" }; +PNAME(mux_hdmi_cec_src_p) = { "dpll", "gpll", "xin24m" }; +PNAME(mux_cvbs_src_p) = { "apll", "io_cvbs_clkin", "hdmiphy", "gpll" }; static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = { [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0), - RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates), + RV1108_PLL_CON(3), 8, 0, 0, rv1108_pll_rates), [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8), - RV1108_PLL_CON(11), 8, 31, 0, NULL), + RV1108_PLL_CON(11), 8, 1, 0, NULL), [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16), - RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates), + RV1108_PLL_CON(19), 8, 2, 0, rv1108_pll_rates), }; #define MFLAGS CLK_MUX_HIWORD_MASK @@ -170,10 +197,10 @@ static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata = RV1108_CLKSEL_CON(7), 12, 2, MFLAGS); static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { - MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, - RV1108_MISC_CON, 13, 2, MFLAGS), + MUX(0, "hdmiphy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, + RV1108_MISC_CON, 13, 1, MFLAGS), MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, - RV1108_MISC_CON, 15, 2, MFLAGS), + RV1108_MISC_CON, 15, 1, MFLAGS), /* * Clock-Architecture Diagram 2 */ @@ -197,63 +224,281 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { RV1108_CLKGATE_CON(11), 1, GFLAGS), /* PD_RKVENC */ + COMPOSITE(0, "aclk_rkvenc_pre", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS, + RV1108_CLKGATE_CON(8), 8, GFLAGS), + FACTOR_GATE(0, "hclk_rkvenc_pre", "aclk_rkvenc_pre", 0, 1, 4, + RV1108_CLKGATE_CON(8), 10, GFLAGS), + COMPOSITE(SCLK_VENC_CORE, "clk_venc_core", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(37), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKGATE_CON(8), 9, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 0, + RV1108_CLKGATE_CON(19), 8, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 0, + RV1108_CLKGATE_CON(19), 9, GFLAGS), + GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(19), 11, GFLAGS), + GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(19), 10, GFLAGS), /* PD_RKVDEC */ + COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS, + RV1108_CLKGATE_CON(8), 2, GFLAGS), + FACTOR_GATE(0, "hclk_rkvdec_pre", "sclk_hevc_core", 0, 1, 4, + RV1108_CLKGATE_CON(8), 10, GFLAGS), + COMPOSITE(SCLK_HEVC_CABAC, "clk_hevc_cabac", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKGATE_CON(8), 1, GFLAGS), + + COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS, + RV1108_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKGATE_CON(8), 3, GFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, + RV1108_CLKGATE_CON(19), 0, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, + RV1108_CLKGATE_CON(19), 1, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, + RV1108_CLKGATE_CON(19), 2, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_rkvdec_pre", 0, + RV1108_CLKGATE_CON(19), 3, GFLAGS), + GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(19), 4, GFLAGS), + GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(19), 5, GFLAGS), + GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(19), 6, GFLAGS), /* PD_PMU_wrapper */ COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, RV1108_CLKSEL_CON(38), 0, 5, DFLAGS, RV1108_CLKGATE_CON(8), 12, GFLAGS), - GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, + GATE(0, "pclk_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(10), 0, GFLAGS), - GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, + GATE(0, "pclk_intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(10), 1, GFLAGS), - GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, + GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pmu_24m_ena", 0, RV1108_CLKGATE_CON(10), 2, GFLAGS), - GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, + GATE(0, "pclk_pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(10), 3, GFLAGS), - GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED, + GATE(0, "pclk_pmu_niu", "pmu_24m_ena", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(10), 4, GFLAGS), - GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, + GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pmu_24m_ena", 0, RV1108_CLKGATE_CON(10), 5, GFLAGS), - GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, + GATE(PCLK_PWM0_PMU, "pclk_pwm0_pmu", "pmu_24m_ena", 0, RV1108_CLKGATE_CON(10), 6, GFLAGS), - COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, + COMPOSITE(SCLK_PWM0_PMU, "sclk_pwm0_pmu", mux_pll_src_2plls_p, 0, RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(8), 15, GFLAGS), - COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, + COMPOSITE(SCLK_I2C0_PMU, "sclk_i2c0_pmu", mux_pll_src_2plls_p, 0, RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(8), 14, GFLAGS), GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(8), 13, GFLAGS), /* + * Clock-Architecture Diagram 3 + */ + COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_wifi_src_p, 0, + RV1108_CLKSEL_CON(28), 15, 1, MFLAGS, 8, 6, DFLAGS, + RV1108_CLKGATE_CON(9), 8, GFLAGS), + COMPOSITE_NODIV(0, "sclk_cifout_src", mux_cifout_src_p, 0, + RV1108_CLKSEL_CON(40), 8, 1, MFLAGS, + RV1108_CLKGATE_CON(9), 11, GFLAGS), + COMPOSITE_NOGATE(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0, + RV1108_CLKSEL_CON(40), 12, 1, MFLAGS, 0, 5, DFLAGS), + COMPOSITE_NOMUX(SCLK_MIPI_CSI_OUT, "sclk_mipi_csi_out", "xin24m", 0, + RV1108_CLKSEL_CON(41), 0, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 12, GFLAGS), + + GATE(0, "pclk_acodecphy", "pclk_top_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(14), 6, GFLAGS), + GATE(0, "pclk_usbgrf", "pclk_top_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(14), 14, GFLAGS), + + INVERTER(0, "pclk_vip", "pclkin_vip", + RV1108_CLKSEL_CON(31), 8, IFLAGS), + GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(7), 6, GFLAGS), + GATE(PCLK_ISP, "pclk_isp", "pclk_isp_pre", 0, + RV1108_CLKGATE_CON(18), 10, GFLAGS), + GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio1_pre", 0, + RV1108_CLKGATE_CON(18), 10, GFLAGS), + GATE(HCLK_CIF0, "hclk_cif0", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(18), 10, GFLAGS), + COMPOSITE_NODIV(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_src_p, 0, + RV1108_CLKSEL_CON(31), 0, 2, MFLAGS, + RV1108_CLKGATE_CON(7), 9, GFLAGS), + GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1_pre", 0, + RV1108_CLKGATE_CON(17), 6, GFLAGS), + GATE(HCLK_CIF1, "hclk_cif1", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(17), 7, GFLAGS), + COMPOSITE_NODIV(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_src_p, 0, + RV1108_CLKSEL_CON(31), 2, 2, MFLAGS, + RV1108_CLKGATE_CON(7), 10, GFLAGS), + GATE(ACLK_CIF2, "aclk_cif2", "aclk_vio1_pre", 0, + RV1108_CLKGATE_CON(17), 8, GFLAGS), + GATE(HCLK_CIF2, "hclk_cif2", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(17), 9, GFLAGS), + COMPOSITE_NODIV(SCLK_CIF2, "sclk_cif2", mux_sclk_cif2_src_p, 0, + RV1108_CLKSEL_CON(31), 4, 2, MFLAGS, + RV1108_CLKGATE_CON(7), 11, GFLAGS), + GATE(ACLK_CIF3, "aclk_cif3", "aclk_vio1_pre", 0, + RV1108_CLKGATE_CON(17), 10, GFLAGS), + GATE(HCLK_CIF3, "hclk_cif3", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(17), 11, GFLAGS), + COMPOSITE_NODIV(SCLK_CIF3, "sclk_cif3", mux_sclk_cif3_src_p, 0, + RV1108_CLKSEL_CON(31), 6, 2, MFLAGS, + RV1108_CLKGATE_CON(7), 12, GFLAGS), + GATE(0, "pclk_cif1to4", "pclk_vip", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(7), 8, GFLAGS), + + /* PD_DSP_wrapper */ + COMPOSITE(SCLK_DSP, "sclk_dsp", mux_dsp_src_p, 0, + RV1108_CLKSEL_CON(42), 8, 2, MFLAGS, 0, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 0, GFLAGS), + GATE(0, "clk_dsp_sys_wd", "sclk_dsp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 0, GFLAGS), + GATE(0, "clk_dsp_epp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 1, GFLAGS), + GATE(0, "clk_dsp_edp_wd", "sclk_dsp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 2, GFLAGS), + GATE(0, "clk_dsp_iop_wd", "sclk_dsp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 3, GFLAGS), + GATE(0, "clk_dsp_free", "sclk_dsp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 13, GFLAGS), + COMPOSITE_NOMUX(SCLK_DSP_IOP, "sclk_dsp_iop", "sclk_dsp", 0, + RV1108_CLKSEL_CON(44), 0, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 1, GFLAGS), + COMPOSITE_NOMUX(SCLK_DSP_EPP, "sclk_dsp_epp", "sclk_dsp", 0, + RV1108_CLKSEL_CON(44), 8, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 2, GFLAGS), + COMPOSITE_NOMUX(SCLK_DSP_EDP, "sclk_dsp_edp", "sclk_dsp", 0, + RV1108_CLKSEL_CON(45), 0, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 3, GFLAGS), + COMPOSITE_NOMUX(SCLK_DSP_EDAP, "sclk_dsp_edap", "sclk_dsp", 0, + RV1108_CLKSEL_CON(45), 8, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 4, GFLAGS), + GATE(0, "pclk_dsp_iop_niu", "sclk_dsp_iop", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 4, GFLAGS), + GATE(0, "aclk_dsp_epp_niu", "sclk_dsp_epp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 5, GFLAGS), + GATE(0, "aclk_dsp_edp_niu", "sclk_dsp_edp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 6, GFLAGS), + GATE(0, "pclk_dsp_dbg_niu", "sclk_dsp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 7, GFLAGS), + GATE(0, "aclk_dsp_edap_niu", "sclk_dsp_edap", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 14, GFLAGS), + COMPOSITE_NOMUX(SCLK_DSP_PFM, "sclk_dsp_pfm", "sclk_dsp", 0, + RV1108_CLKSEL_CON(43), 0, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 5, GFLAGS), + COMPOSITE_NOMUX(PCLK_DSP_CFG, "pclk_dsp_cfg", "sclk_dsp", 0, + RV1108_CLKSEL_CON(43), 8, 5, DFLAGS, + RV1108_CLKGATE_CON(9), 6, GFLAGS), + GATE(0, "pclk_dsp_cfg_niu", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 8, GFLAGS), + GATE(0, "pclk_dsp_pfm_mon", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 9, GFLAGS), + GATE(0, "pclk_intc", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 10, GFLAGS), + GATE(0, "pclk_dsp_grf", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 11, GFLAGS), + GATE(0, "pclk_mailbox", "pclk_dsp_cfg", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 12, GFLAGS), + GATE(0, "aclk_dsp_epp_perf", "sclk_dsp_epp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(16), 15, GFLAGS), + GATE(0, "aclk_dsp_edp_perf", "sclk_dsp_edp", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(11), 8, GFLAGS), + + /* * Clock-Architecture Diagram 4 */ - COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, + COMPOSITE(0, "aclk_vio0_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, RV1108_CLKGATE_CON(6), 0, GFLAGS), - GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED, + GATE(ACLK_VIO0, "aclk_vio0", "aclk_vio0_pre", 0, RV1108_CLKGATE_CON(17), 0, GFLAGS), COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, RV1108_CLKSEL_CON(29), 0, 5, DFLAGS, RV1108_CLKGATE_CON(7), 2, GFLAGS), + GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(17), 2, GFLAGS), COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, RV1108_CLKSEL_CON(29), 8, 5, DFLAGS, RV1108_CLKGATE_CON(7), 3, GFLAGS), + GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0, + RV1108_CLKGATE_CON(17), 3, GFLAGS), + + COMPOSITE(0, "aclk_vio1_pre", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, + RV1108_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKGATE_CON(6), 1, GFLAGS), + GATE(ACLK_VIO1, "aclk_vio1", "aclk_vio1_pre", 0, + RV1108_CLKGATE_CON(17), 1, GFLAGS), - INVERTER(0, "pclk_vip", "ext_vip", - RV1108_CLKSEL_CON(31), 8, IFLAGS), - GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(7), 6, GFLAGS), - GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(18), 10, GFLAGS), GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(6), 5, GFLAGS), GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(6), 4, GFLAGS), - COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0, - RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS), + COMPOSITE_NOGATE(0, "dclk_hdmiphy_pre", mux_dclk_hdmiphy_pre_p, 0, + RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 8, 6, DFLAGS), + COMPOSITE_NOGATE(DCLK_VOP_SRC, "dclk_vop_src", mux_dclk_hdmiphy_pre_p, 0, + RV1108_CLKSEL_CON(32), 6, 1, MFLAGS, 0, 6, DFLAGS), + MUX(DCLK_HDMIPHY, "dclk_hdmiphy", mux_dclk_hdmiphy_p, CLK_SET_RATE_PARENT, + RV1108_CLKSEL_CON(32), 15, 1, MFLAGS), + MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT, + RV1108_CLKSEL_CON(32), 7, 1, MFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vio0_pre", 0, + RV1108_CLKGATE_CON(18), 0, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(18), 1, GFLAGS), + GATE(ACLK_IEP, "aclk_iep", "aclk_vio0_pre", 0, + RV1108_CLKGATE_CON(18), 2, GFLAGS), + GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(18), 3, GFLAGS), + + GATE(ACLK_RGA, "aclk_rga", "aclk_vio1_pre", 0, + RV1108_CLKGATE_CON(18), 4, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(18), 5, GFLAGS), + COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 5, DFLAGS, + RV1108_CLKGATE_CON(6), 6, GFLAGS), + + COMPOSITE(SCLK_CVBS_HOST, "sclk_cvbs_host", mux_cvbs_src_p, 0, + RV1108_CLKSEL_CON(33), 13, 2, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKGATE_CON(6), 7, GFLAGS), + FACTOR(0, "sclk_cvbs_27m", "sclk_cvbs_host", 0, 1, 2), + + GATE(SCLK_HDMI_SFR, "sclk_hdmi_sfr", "xin24m", 0, + RV1108_CLKGATE_CON(6), 8, GFLAGS), + + COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_hdmi_cec_src_p, 0, + RV1108_CLKSEL_CON(34), 14, 2, MFLAGS, 0, 14, DFLAGS, + RV1108_CLKGATE_CON(6), 9, GFLAGS), + GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vio_pre", 0, + RV1108_CLKGATE_CON(18), 8, GFLAGS), + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_vio_pre", 0, + RV1108_CLKGATE_CON(18), 9, GFLAGS), + + GATE(ACLK_ISP, "aclk_isp", "aclk_vio1_pre", 0, + RV1108_CLKGATE_CON(18), 12, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0, + RV1108_CLKGATE_CON(18), 11, GFLAGS), + COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_4plls_p, 0, + RV1108_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKGATE_CON(6), 3, GFLAGS), + + GATE(0, "clk_dsiphy24m", "xin24m", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(9), 10, GFLAGS), + GATE(0, "pclk_vdacphy", "pclk_top_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(14), 9, GFLAGS), + GATE(0, "pclk_mipi_dsiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(14), 11, GFLAGS), + GATE(0, "pclk_mipi_csiphy", "pclk_top_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(14), 12, GFLAGS), /* * Clock-Architecture Diagram 5 @@ -261,10 +506,38 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { FACTOR(0, "xin12m", "xin24m", 0, 1, 2), - COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, + /* PD_BUS */ + GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(1), 0, GFLAGS), + GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(1), 1, GFLAGS), + GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE_NOGATE(ACLK_BUS, "aclk_bus_pre", mux_aclk_bus_src_p, 0, + RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), + COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus_pre", "aclk_bus_pre", 0, + RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, + RV1108_CLKGATE_CON(1), 4, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_bus_pre", "aclk_bus_pre", 0, + RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, + RV1108_CLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0, + RV1108_CLKGATE_CON(1), 6, GFLAGS), + GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(1), 7, GFLAGS), + GATE(0, "pclk_ddr_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(1), 8, GFLAGS), + GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0, + RV1108_CLKGATE_CON(1), 9, GFLAGS), + GATE(SCLK_TIMER1, "clk_timer1", "xin24m", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(13), 4, GFLAGS), + + COMPOSITE(SCLK_I2S0_SRC, "i2s0_src", mux_pll_src_2plls_p, 0, RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(2), 0, GFLAGS), - COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, + COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, RV1108_CLKSEL_CON(8), 0, RV1108_CLKGATE_CON(2), 1, GFLAGS, &rv1108_i2s0_fracmux), @@ -274,7 +547,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { RV1108_CLKSEL_CON(5), 15, 1, MFLAGS, RV1108_CLKGATE_CON(2), 3, GFLAGS), - COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, + COMPOSITE(SCLK_I2S1_SRC, "i2s1_src", mux_pll_src_2plls_p, 0, RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(2), 4, GFLAGS), COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, @@ -284,7 +557,7 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, RV1108_CLKGATE_CON(2), 6, GFLAGS), - COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, + COMPOSITE(SCLK_I2S2_SRC, "i2s2_src", mux_pll_src_2plls_p, 0, RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(3), 8, GFLAGS), COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, @@ -293,42 +566,34 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { &rv1108_i2s2_fracmux), GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, RV1108_CLKGATE_CON(2), 10, GFLAGS), - - /* PD_BUS */ - GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 0, GFLAGS), - GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 1, GFLAGS), - GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 2, GFLAGS), - COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, - RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), - COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0, - RV1108_CLKSEL_CON(3), 0, 5, DFLAGS, - RV1108_CLKGATE_CON(1), 4, GFLAGS), - COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0, - RV1108_CLKSEL_CON(3), 8, 5, DFLAGS, - RV1108_CLKGATE_CON(1), 5, GFLAGS), - GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 6, GFLAGS), - GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 7, GFLAGS), - GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 8, GFLAGS), - GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 9, GFLAGS), - GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(1), 10, GFLAGS), - GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, - RV1108_CLKGATE_CON(13), 4, GFLAGS), - - COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, + RV1108_CLKGATE_CON(12), 7, GFLAGS), + GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_bus_pre", 0, + RV1108_CLKGATE_CON(12), 8, GFLAGS), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, + RV1108_CLKGATE_CON(12), 9, GFLAGS), + + GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, + RV1108_CLKGATE_CON(12), 10, GFLAGS), + GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, + RV1108_CLKGATE_CON(12), 11, GFLAGS), + COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0, + RV1108_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS, + RV1108_CLKGATE_CON(2), 12, GFLAGS), + + COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_2plls_p, 0, + RV1108_CLKSEL_CON(11), 15, 1, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKGATE_CON(3), 0, GFLAGS), + GATE(PCLK_SPI, "pclk_spi", "pclk_bus_pre", 0, + RV1108_CLKGATE_CON(13), 5, GFLAGS), + + COMPOSITE(SCLK_UART0_SRC, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(3), 1, GFLAGS), - COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, + COMPOSITE(SCLK_UART1_SRC, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(3), 3, GFLAGS), - COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, + COMPOSITE(SCLK_UART2_SRC, "uart2_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(3), 5, GFLAGS), @@ -344,44 +609,58 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { RV1108_CLKSEL_CON(18), 0, RV1108_CLKGATE_CON(3), 6, GFLAGS, &rv1108_uart2_fracmux), - GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 10, GFLAGS), - GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 11, GFLAGS), - GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 12, GFLAGS), - COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, - RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS, + COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_2plls_p, 0, + RV1108_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, RV1108_CLKGATE_CON(3), 7, GFLAGS), - COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, - RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS, + COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_2plls_p, 0, + RV1108_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(3), 8, GFLAGS), - COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, - RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS, + COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_2plls_p, 0, + RV1108_CLKSEL_CON(20), 15, 1, MFLAGS, 8, 7, DFLAGS, RV1108_CLKGATE_CON(3), 9, GFLAGS), - GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 0, GFLAGS), - GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 1, GFLAGS), - GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 2, GFLAGS), - COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, + COMPOSITE(SCLK_PWM1, "clk_pwm1", mux_pll_src_2plls_p, 0, RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, RV1108_CLKGATE_CON(3), 10, GFLAGS), - GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 6, GFLAGS), - GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 3, GFLAGS), - GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 7, GFLAGS), - GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 8, GFLAGS), - GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_pre", 0, RV1108_CLKGATE_CON(13), 9, GFLAGS), GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(14), 0, GFLAGS), + GATE(PCLK_EFUSE0, "pclk_efuse0", "pclk_bus_pre", 0, + RV1108_CLKGATE_CON(12), 12, GFLAGS), + GATE(PCLK_EFUSE1, "pclk_efuse1", "pclk_bus_pre", 0, + RV1108_CLKGATE_CON(12), 13, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_pre", 0, + RV1108_CLKGATE_CON(13), 13, GFLAGS), + COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0, + RV1108_CLKSEL_CON(21), 0, 10, DFLAGS, + RV1108_CLKGATE_CON(3), 11, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_pre", 0, + RV1108_CLKGATE_CON(13), 14, GFLAGS), + COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0, + RV1108_CLKSEL_CON(22), 0, 10, DFLAGS, + RV1108_CLKGATE_CON(3), 12, GFLAGS), GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, RV1108_CLKGATE_CON(12), 2, GFLAGS), @@ -397,18 +676,24 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { RV1108_CLKGATE_CON(0), 9, GFLAGS), GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(0), 10, GFLAGS), - COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, + COMPOSITE_NOGATE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED, RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, - DFLAGS | CLK_DIVIDER_POWER_OF_TWO, + DFLAGS | CLK_DIVIDER_POWER_OF_TWO), + FACTOR(0, "clk_ddr", "clk_ddrphy_src", 0, 1, 2), + GATE(0, "clk_ddrphy4x", "clk_ddr", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(10), 9, GFLAGS), - GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED, + GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(12), 4, GFLAGS), - GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED, + GATE(0, "nclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(12), 5, GFLAGS), - GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED, + GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(12), 6, GFLAGS), GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(0), 11, GFLAGS), + GATE(0, "pclk_mschniu", "pclk_ddr_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(14), 2, GFLAGS), + GATE(0, "pclk_ddrphy", "pclk_ddr_pre", CLK_IGNORE_UNUSED, + RV1108_CLKGATE_CON(14), 4, GFLAGS), /* * Clock-Architecture Diagram 6 @@ -418,23 +703,23 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, RV1108_CLKSEL_CON(23), 10, 5, DFLAGS, RV1108_CLKGATE_CON(4), 5, GFLAGS), - GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, + GATE(PCLK_PERI, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 13, GFLAGS), COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, RV1108_CLKSEL_CON(23), 5, 5, DFLAGS, RV1108_CLKGATE_CON(4), 4, GFLAGS), - GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, + GATE(HCLK_PERI, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 12, GFLAGS), GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(4), 1, GFLAGS), GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(4), 2, GFLAGS), - COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED, - RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS, + COMPOSITE(ACLK_PERI, "aclk_periph", mux_aclk_peri_src_p, 0, + RV1108_CLKSEL_CON(23), 15, 1, MFLAGS, 0, 5, DFLAGS, RV1108_CLKGATE_CON(15), 11, GFLAGS), - COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, + COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, RV1108_CLKGATE_CON(5), 0, GFLAGS), @@ -454,23 +739,29 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS), COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, - RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS, + RV1108_CLKSEL_CON(27), 14, 1, MFLAGS, 8, 5, DFLAGS, RV1108_CLKGATE_CON(5), 3, GFLAGS), GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS), + GATE(HCLK_HOST0, "hclk_host0", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 6, GFLAGS), + GATE(0, "hclk_host0_arb", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 7, GFLAGS), + GATE(HCLK_OTG, "hclk_otg", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 8, GFLAGS), + GATE(0, "hclk_otg_pmu", "hclk_periph", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(15), 9, GFLAGS), + GATE(SCLK_USBPHY, "clk_usbphy", "xin24m", CLK_IGNORE_UNUSED, RV1108_CLKGATE_CON(5), 5, GFLAGS), + COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, - RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS, + RV1108_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS, RV1108_CLKGATE_CON(5), 4, GFLAGS), GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS), - COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0, - RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS, + COMPOSITE(SCLK_MACPHY_PRE, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0, + RV1108_CLKSEL_CON(24), 12, 1, MFLAGS, 0, 5, DFLAGS, RV1108_CLKGATE_CON(4), 10, GFLAGS), - MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT, - RV1108_CLKSEL_CON(24), 8, 2, MFLAGS), - GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), - GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), - GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), + MUX(SCLK_MACPHY, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT, + RV1108_CLKSEL_CON(24), 8, 1, MFLAGS), + GATE(SCLK_MACPHY_RX, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS), + GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS), + GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS), MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1), MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1), @@ -484,10 +775,16 @@ static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = { static const char *const rv1108_critical_clocks[] __initconst = { "aclk_core", - "aclk_bus_src_gpll", + "aclk_bus", + "hclk_bus", + "pclk_bus", "aclk_periph", "hclk_periph", "pclk_periph", + "nclk_ddrupctl", + "pclk_ddrmon", + "pclk_acodecphy", + "pclk_pmu", }; static void __init rv1108_clk_init(struct device_node *np) -- 2.7.4 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 02/14] clk: rockchip: support more clks for rv1108 2017-07-31 10:08 ` [PATCH 02/14] clk: rockchip: support more clks for rv1108 Andy Yan @ 2017-07-31 23:31 ` Heiko Stuebner 0 siblings, 0 replies; 26+ messages in thread From: Heiko Stuebner @ 2017-07-31 23:31 UTC (permalink / raw) To: Andy Yan Cc: devicetree, linux-clk, linux-kernel, linux-rockchip, robh+dt, shawn.lin, zhangqing, mturquette, sboyd, linux-arm-kernel Am Montag, 31. Juli 2017, 18:08:39 CEST schrieb Andy Yan: > From: Elaine Zhang <zhangqing@rock-chips.com> > > 1. Added the description of the missing clock, > make the clock more complete. > 2. fix up some clk descriptions error. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Again, this should be split into multiple patches that are easier to review. - pll-fixes - fixes for existing clocks - renames of things - new clock-definitions And should definitly include a bit more explanation. Thanks Heiko ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 03/14] pinctrl: rockchip: add input schmitt support for rv1108 2017-07-31 10:04 [PATCH 00/14] Support more devices on rockchip rv1108 Andy Yan 2017-07-31 10:08 ` [PATCH 02/14] clk: rockchip: support more clks for rv1108 Andy Yan @ 2017-07-31 10:10 ` Andy Yan 2017-07-31 11:26 ` Heiko Stübner [not found] ` <1501495822-21503-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-07-31 10:11 ` [PATCH 04/14] dt-bindings: i2c: rk3x: add " Andy Yan ` (2 subsequent siblings) 4 siblings, 2 replies; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:10 UTC (permalink / raw) To: heiko, linus.walleij Cc: devicetree, linux-clk, linux-kernel, linux-rockchip, linux-gpio, Andy Yan Some pins like i2c SCL/SDA need the schmitt input function to avoid crosstalk problems. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> --- drivers/pinctrl/pinctrl-rockchip.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index e831647..868cb9c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1084,6 +1084,36 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, *bit *= RV1108_DRV_BITS_PER_PIN; } +#define RV1108_SCHMITT_PMU_OFFSET 0x30 +#define RV1108_SCHMITT_GRF_OFFSET 0x388 +#define RV1108_SCHMITT_BANK_STRIDE 8 +#define RV1108_SCHMITT_PINS_PER_GRF_REG 16 +#define RV1108_SCHMITT_PINS_PER_PMU_REG 8 + +static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + int pins_per_reg; + + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RV1108_SCHMITT_PMU_OFFSET; + pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; + } else { + *regmap = info->regmap_base; + *reg = RV1108_SCHMITT_GRF_OFFSET; + pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; + *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; + } + *reg += ((pin_num / pins_per_reg) * 4); + *bit = pin_num % pins_per_reg; + + return 0; +} + #define RK2928_PULL_OFFSET 0x118 #define RK2928_PULL_PINS_PER_REG 16 #define RK2928_PULL_BANK_STRIDE 8 @@ -3017,6 +3047,7 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pmu_mux_offset = 0x0, .pull_calc_reg = rv1108_calc_pull_reg_and_bit, .drv_calc_reg = rv1108_calc_drv_reg_and_bit, + .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, }; static struct rockchip_pin_bank rk2928_pin_banks[] = { -- 2.7.4 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 03/14] pinctrl: rockchip: add input schmitt support for rv1108 2017-07-31 10:10 ` [PATCH 03/14] pinctrl: rockchip: add input schmitt support " Andy Yan @ 2017-07-31 11:26 ` Heiko Stübner [not found] ` <1501495822-21503-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 1 sibling, 0 replies; 26+ messages in thread From: Heiko Stübner @ 2017-07-31 11:26 UTC (permalink / raw) To: Andy Yan Cc: linus.walleij, devicetree, linux-clk, linux-kernel, linux-rockchip, linux-gpio Am Montag, 31. Juli 2017, 18:10:22 CEST schrieb Andy Yan: > Some pins like i2c SCL/SDA need the schmitt input function > to avoid crosstalk problems. > > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <1501495822-21503-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH 03/14] pinctrl: rockchip: add input schmitt support for rv1108 [not found] ` <1501495822-21503-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2017-08-07 8:49 ` Linus Walleij 0 siblings, 0 replies; 26+ messages in thread From: Linus Walleij @ 2017-08-07 8:49 UTC (permalink / raw) To: Andy Yan Cc: Heiko Stübner, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, open list:ARM/Rockchip SoC..., linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org On Mon, Jul 31, 2017 at 12:10 PM, Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote: > Some pins like i2c SCL/SDA need the schmitt input function > to avoid crosstalk problems. > > Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Patch applied with Heiko's review tag. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 04/14] dt-bindings: i2c: rk3x: add support for rv1108 2017-07-31 10:04 [PATCH 00/14] Support more devices on rockchip rv1108 Andy Yan 2017-07-31 10:08 ` [PATCH 02/14] clk: rockchip: support more clks for rv1108 Andy Yan 2017-07-31 10:10 ` [PATCH 03/14] pinctrl: rockchip: add input schmitt support " Andy Yan @ 2017-07-31 10:11 ` Andy Yan 2017-07-31 10:19 ` [PATCH 11/14] ARM: dts: rockchip: add saradc " Andy Yan [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 4 siblings, 0 replies; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:11 UTC (permalink / raw) To: heiko; +Cc: devicetree, robh+dt, linux-kernel, linux-rockchip, wsa, Andy Yan Add dt Document for i2c controller on rv1108 Signed-off-by: Andy Yan <andy.yan@rock-chips.com> --- Documentation/devicetree/bindings/i2c/i2c-rk3x.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt index e18445d..22f2eeb 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt @@ -7,6 +7,7 @@ Required properties : - reg : Offset and length of the register set for the device - compatible: should be one of the following: + - "rockchip,rv1108-i2c": for rv1108 - "rockchip,rk3066-i2c": for rk3066 - "rockchip,rk3188-i2c": for rk3188 - "rockchip,rk3228-i2c": for rk3228 -- 2.7.4 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 11/14] ARM: dts: rockchip: add saradc support for rv1108 2017-07-31 10:04 [PATCH 00/14] Support more devices on rockchip rv1108 Andy Yan ` (2 preceding siblings ...) 2017-07-31 10:11 ` [PATCH 04/14] dt-bindings: i2c: rk3x: add " Andy Yan @ 2017-07-31 10:19 ` Andy Yan 2017-07-31 23:11 ` Heiko Stuebner [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 4 siblings, 1 reply; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:19 UTC (permalink / raw) To: heiko; +Cc: devicetree, linux-kernel, linux-rockchip, robh+dt, Andy Yan Add saradc device tree node for rv1108 Signed-off-by: Andy Yan <andy.yan@rock-chips.com> --- arch/arm/boot/dts/rv1108.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 1fc467e..958fecd 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -275,6 +275,18 @@ status = "disabled"; }; + adc: adc@1038c000 { + compatible = "rockchip,rk3399-saradc"; + reg = <0x1038c000 0x100>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + io-channel-ranges; + clock-frequency = <1000000>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + i2c0: i2c@20000000 { compatible = "rockchip,rv1108-i2c"; reg = <0x20000000 0x1000>; -- 2.7.4 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 11/14] ARM: dts: rockchip: add saradc support for rv1108 2017-07-31 10:19 ` [PATCH 11/14] ARM: dts: rockchip: add saradc " Andy Yan @ 2017-07-31 23:11 ` Heiko Stuebner 0 siblings, 0 replies; 26+ messages in thread From: Heiko Stuebner @ 2017-07-31 23:11 UTC (permalink / raw) To: Andy Yan; +Cc: devicetree, linux-kernel, linux-rockchip, robh+dt Hi Andy, Am Montag, 31. Juli 2017, 18:19:19 CEST schrieb Andy Yan: > Add saradc device tree node for rv1108 > > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> > --- > > arch/arm/boot/dts/rv1108.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi > index 1fc467e..958fecd 100644 > --- a/arch/arm/boot/dts/rv1108.dtsi > +++ b/arch/arm/boot/dts/rv1108.dtsi > @@ -275,6 +275,18 @@ > status = "disabled"; > }; > > + adc: adc@1038c000 { > + compatible = "rockchip,rk3399-saradc"; you should amend the binding txt to make this something like compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc" See for example the bindings/mmc/rockchip-dw-mshc.txt as inspiration. Heiko ^ permalink raw reply [flat|nested] 26+ messages in thread
[parent not found: <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* [PATCH 01/14] clk: rockchip: add more clk ids for rv1108 [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2017-07-31 10:06 ` Andy Yan 2017-07-31 23:27 ` Heiko Stuebner 2017-07-31 10:12 ` [PATCH 05/14] i2c: rk3x: add support " Andy Yan ` (8 subsequent siblings) 9 siblings, 1 reply; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:06 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, shawn.lin-TNX95d0MmH7DzftRWevZcw, zhangqing-TNX95d0MmH7DzftRWevZcw, Andy Yan From: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Added the missing clock ids, make the clock more complete. Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- include/dt-bindings/clock/rv1108-cru.h | 128 ++++++++++++++++++++++++++++----- 1 file changed, 109 insertions(+), 19 deletions(-) diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h index ae26f81..e284b1e 100644 --- a/include/dt-bindings/clock/rv1108-cru.h +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -43,12 +43,73 @@ #define SCLK_SDMMC_SAMPLE 84 #define SCLK_SDIO_SAMPLE 85 #define SCLK_EMMC_SAMPLE 86 +#define SCLK_VENC_CORE 87 +#define SCLK_HEVC_CORE 88 +#define SCLK_HEVC_CABAC 89 +#define SCLK_PWM0_PMU 90 +#define SCLK_I2C0_PMU 91 +#define SCLK_WIFI 92 +#define SCLK_CIFOUT 93 +#define SCLK_MIPI_CSI_OUT 94 +#define SCLK_CIF0 95 +#define SCLK_CIF1 96 +#define SCLK_CIF2 97 +#define SCLK_CIF3 98 +#define SCLK_DSP 99 +#define SCLK_DSP_IOP 100 +#define SCLK_DSP_EPP 101 +#define SCLK_DSP_EDP 102 +#define SCLK_DSP_EDAP 103 +#define SCLK_CVBS_HOST 104 +#define SCLK_HDMI_SFR 105 +#define SCLK_HDMI_CEC 106 +#define SCLK_CRYPTO 107 +#define SCLK_SPI 108 +#define SCLK_SARADC 109 +#define SCLK_TSADC 110 +#define SCLK_MACPHY_PRE 111 +#define SCLK_MACPHY 112 +#define SCLK_MACPHY_RX 113 +#define SCLK_MAC_REF 114 +#define SCLK_MAC_REFOUT 115 +#define SCLK_DSP_PFM 116 +#define SCLK_RGA 117 +#define SCLK_I2C1 118 +#define SCLK_I2C2 119 +#define SCLK_I2C3 120 +#define SCLK_PWM1 121 +#define SCLK_ISP 122 +#define SCLK_USBPHY 123 +#define SCLK_I2S0_SRC 124 +#define SCLK_I2S1_SRC 125 +#define SCLK_I2S2_SRC 126 +#define SCLK_UART0_SRC 127 +#define SCLK_UART1_SRC 128 +#define SCLK_UART2_SRC 129 + +#define DCLK_VOP_SRC 185 +#define DCLK_HDMIPHY 186 +#define DCLK_VOP 187 /* aclk gates */ #define ACLK_DMAC 192 -#define ACLK_PRE 193 +#define ACLK_BUS 193 #define ACLK_CORE 194 #define ACLK_ENMCORE 195 +#define ACLK_RKVENC 196 +#define ACLK_RKVDEC 197 +#define ACLK_VPU 198 +#define ACLK_CIF0 199 +#define ACLK_VIO0 200 +#define ACLK_VIO1 201 +#define ACLK_VOP 202 +#define ACLK_IEP 203 +#define ACLK_RGA 204 +#define ACLK_ISP 205 +#define ACLK_CIF1 206 +#define ACLK_CIF2 207 +#define ACLK_CIF3 208 +#define ACLK_PERI 209 /* pclk gates */ #define PCLK_GPIO1 256 @@ -59,18 +120,30 @@ #define PCLK_I2C2 261 #define PCLK_I2C3 262 #define PCLK_SPI 263 -#define PCLK_SFC 264 #define PCLK_UART0 265 #define PCLK_UART1 266 #define PCLK_UART2 267 #define PCLK_TSADC 268 -#define PCLK_PWM 269 +#define PCLK_PWM1 269 #define PCLK_TIMER 270 #define PCLK_PERI 271 +#define PCLK_GPIO0_PMU 272 +#define PCLK_I2C0_PMU 273 +#define PCLK_PWM0_PMU 274 +#define PCLK_ISP 275 +#define PCLK_VIO 276 +#define PCLK_MIPI_DSI 277 +#define PCLK_HDMI_CTRL 278 +#define PCLK_SARADC 279 +#define PCLK_DSP_CFG 280 +#define PCLK_BUS 281 +#define PCLK_EFUSE0 282 +#define PCLK_EFUSE1 283 +#define PCLK_WDT 284 /* hclk gates */ #define HCLK_I2S0_8CH 320 -#define HCLK_I2S1_8CH 321 +#define HCLK_I2S1_2CH 321 #define HCLK_I2S2_2CH 322 #define HCLK_NANDC 323 #define HCLK_SDMMC 324 @@ -78,20 +151,37 @@ #define HCLK_EMMC 326 #define HCLK_PERI 327 #define HCLK_SFC 328 +#define HCLK_RKVENC 329 +#define HCLK_RKVDEC 330 +#define HCLK_CIF0 331 +#define HCLK_VIO 332 +#define HCLK_VOP 333 +#define HCLK_IEP 334 +#define HCLK_RGA 335 +#define HCLK_ISP 336 +#define HCLK_CRYPTO_MST 337 +#define HCLK_CRYPTO_SLV 338 +#define HCLK_HOST0 339 +#define HCLK_OTG 340 +#define HCLK_CIF1 341 +#define HCLK_CIF2 342 +#define HCLK_CIF3 343 +#define HCLK_BUS 344 +#define HCLK_VPU 345 -#define CLK_NR_CLKS (HCLK_SFC + 1) +#define CLK_NR_CLKS (HCLK_VPU + 1) /* reset id */ -#define SRST_CORE_PO_AD 0 +#define SRST_CORE_PO_AD 0 #define SRST_CORE_AD 1 #define SRST_L2_AD 2 -#define SRST_CPU_NIU_AD 3 +#define SRST_CPU_NIU_AD 3 #define SRST_CORE_PO 4 #define SRST_CORE 5 -#define SRST_L2 6 +#define SRST_L2 6 #define SRST_CORE_DBG 8 #define PRST_DBG 9 -#define RST_DAP 10 +#define RST_DAP 10 #define PRST_DBG_NIU 11 #define ARST_STRC_SYS_AD 15 @@ -158,9 +248,9 @@ #define HRST_SYSBUS 75 #define PRST_USBGRF 76 -#define ARST_PERIPH_NIU 80 -#define HRST_PERIPH_NIU 81 -#define PRST_PERIPH_NIU 82 +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 #define HRST_PERIPH 83 #define HRST_SDMMC 84 #define HRST_SDIO 85 @@ -178,7 +268,7 @@ #define HRST_HOST0_AUX 96 #define HRST_HOST0_ARB 97 #define SRST_HOST0_EHCIPHY 98 -#define SRST_HOST0_UTMI 99 +#define SRST_HOST0_UTMI 99 #define SRST_USBPOR 100 #define SRST_UTMI0 101 #define SRST_UTMI1 102 @@ -225,21 +315,21 @@ #define HRST_VPU_NIU 141 #define ARST_VPU 142 #define HRST_VPU 143 -#define ARST_RKVDEC_NIU 144 -#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 #define ARST_RKVDEC 146 #define HRST_RKVDEC 147 #define SRST_RKVDEC_CABAC 148 #define SRST_RKVDEC_CORE 149 -#define ARST_RKVENC_NIU 150 -#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 #define ARST_RKVENC 152 #define HRST_RKVENC 153 #define SRST_RKVENC_CORE 154 #define SRST_DSP_CORE 156 #define SRST_DSP_SYS 157 -#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_GLOBAL 158 #define SRST_DSP_OECM 159 #define PRST_DSP_IOP_NIU 160 #define ARST_DSP_EPP_NIU 161 @@ -257,7 +347,7 @@ #define SRST_PMU_I2C0 173 #define PRST_PMU_I2C0 174 #define PRST_PMU_GPIO0 175 -#define PRST_PMU_INTMEM 176 +#define PRST_PMU_INTMEM 176 #define PRST_PMU_PWM0 177 #define SRST_PMU_PWM0 178 #define PRST_PMU_GRF 179 -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 01/14] clk: rockchip: add more clk ids for rv1108 2017-07-31 10:06 ` [PATCH 01/14] clk: rockchip: add more clk ids " Andy Yan @ 2017-07-31 23:27 ` Heiko Stuebner 0 siblings, 0 replies; 26+ messages in thread From: Heiko Stuebner @ 2017-07-31 23:27 UTC (permalink / raw) To: linux-rockchip Cc: Andy Yan, devicetree, shawn.lin, zhangqing, linux-kernel, robh+dt, linux-clk Hi Andy, Am Montag, 31. Juli 2017, 18:06:42 CEST schrieb Andy Yan: > From: Elaine Zhang <zhangqing@rock-chips.com> > > Added the missing clock ids, make the clock more complete. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> this clock-id patch is way to overloaded. Please split into 3 parts: - completely new clock-ids - changes to existing clock-ids This also needs a very good reasoning, as such constant ids are considered part of api and should not change to prevent breakage with old devicetrees. So please double-check if the rename is really necessary. - cosmetics ... aka the indentation stuff [...] > /* aclk gates */ > #define ACLK_DMAC 192 > -#define ACLK_PRE 193 > +#define ACLK_BUS 193 This is one such case where you need a very good reason [...] > @@ -59,18 +120,30 @@ > #define PCLK_I2C2 261 > #define PCLK_I2C3 262 > #define PCLK_SPI 263 > -#define PCLK_SFC 264 why is this clock going away? > #define PCLK_UART0 265 > #define PCLK_UART1 266 > #define PCLK_UART2 267 > #define PCLK_TSADC 268 > -#define PCLK_PWM 269 > +#define PCLK_PWM1 269 In your pwm patch, all blocks use the same clocks, so this rename should be unnecessary > /* hclk gates */ > #define HCLK_I2S0_8CH 320 > -#define HCLK_I2S1_8CH 321 > +#define HCLK_I2S1_2CH 321 Again reasoning required (that i2s1 has 2 channels but not 8 should be ok for that) > #define HCLK_I2S2_2CH 322 > #define HCLK_NANDC 323 > #define HCLK_SDMMC 324 Heiko ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 05/14] i2c: rk3x: add support for rv1108 [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-07-31 10:06 ` [PATCH 01/14] clk: rockchip: add more clk ids " Andy Yan @ 2017-07-31 10:12 ` Andy Yan [not found] ` <1501495963-21608-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-07-31 10:13 ` [PATCH 06/14] ARM: dts: rockchip: add i2c dt node " Andy Yan ` (7 subsequent siblings) 9 siblings, 1 reply; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:12 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-i2c-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, wsa-z923LK4zBo2bacvFa/9K2g, Andy Yan Support for the i2c controller on rv1108 Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- drivers/i2c/busses/i2c-rk3x.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c index df22066..fe23457 100644 --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -1131,6 +1131,11 @@ static const struct i2c_algorithm rk3x_i2c_algorithm = { .functionality = rk3x_i2c_func, }; +static const struct rk3x_i2c_soc_data rv1108_soc_data = { + .grf_offset = -1, + .calc_timings = rk3x_i2c_v1_calc_timings, +}; + static const struct rk3x_i2c_soc_data rk3066_soc_data = { .grf_offset = 0x154, .calc_timings = rk3x_i2c_v0_calc_timings, @@ -1158,6 +1163,10 @@ static const struct rk3x_i2c_soc_data rk3399_soc_data = { static const struct of_device_id rk3x_i2c_match[] = { { + .compatible = "rockchip,rv1108-i2c", + .data = (void *)&rv1108_soc_data + }, + { .compatible = "rockchip,rk3066-i2c", .data = (void *)&rk3066_soc_data }, -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
[parent not found: <1501495963-21608-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH 05/14] i2c: rk3x: add support for rv1108 [not found] ` <1501495963-21608-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2017-07-31 11:26 ` Heiko Stübner 0 siblings, 0 replies; 26+ messages in thread From: Heiko Stübner @ 2017-07-31 11:26 UTC (permalink / raw) To: Andy Yan Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-i2c-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, wsa-z923LK4zBo2bacvFa/9K2g Am Montag, 31. Juli 2017, 18:12:43 CEST schrieb Andy Yan: > Support for the i2c controller on rv1108 > > Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Reviewed-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 06/14] ARM: dts: rockchip: add i2c dt node for rv1108 [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-07-31 10:06 ` [PATCH 01/14] clk: rockchip: add more clk ids " Andy Yan 2017-07-31 10:12 ` [PATCH 05/14] i2c: rk3x: add support " Andy Yan @ 2017-07-31 10:13 ` Andy Yan 2017-07-31 10:15 ` [PATCH 07/14] spi: rockchip: add compatible string for rv1108 spi Andy Yan ` (6 subsequent siblings) 9 siblings, 0 replies; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:13 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-i2c-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, wsa-z923LK4zBo2bacvFa/9K2g, Andy Yan There are four i2c controllers on rv1108, add device tree node for them. Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rv1108.dtsi | 72 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 0da144c..a4d34d9 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -52,6 +52,10 @@ interrupt-parent = <&gic>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -154,11 +158,67 @@ status = "disabled"; }; + i2c1: i2c@10240000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x10240000 0x1000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@10250000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x10250000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "disabled"; + }; + + i2c3: i2c@10260000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x10260000 0x1000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + grf: syscon@10300000 { compatible = "rockchip,rv1108-grf", "syscon"; reg = <0x10300000 0x1000>; }; + i2c0: i2c@20000000 { + compatible = "rockchip,rv1108-i2c"; + reg = <0x20000000 0x1000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + pmugrf: syscon@20060000 { compatible = "rockchip,rv1108-pmugrf", "syscon"; reg = <0x20060000 0x1000>; @@ -330,6 +390,18 @@ input-enable; }; + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>, + <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>; + }; + }; + i2c1 { i2c1_xfer: i2c1-xfer { rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 07/14] spi: rockchip: add compatible string for rv1108 spi [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (2 preceding siblings ...) 2017-07-31 10:13 ` [PATCH 06/14] ARM: dts: rockchip: add i2c dt node " Andy Yan @ 2017-07-31 10:15 ` Andy Yan [not found] ` <1501496103-21713-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-07-31 10:16 ` [PATCH 08/14] ARM: dts: rockchip: add spi dt node for rv1108 Andy Yan ` (5 subsequent siblings) 9 siblings, 1 reply; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:15 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-spi-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, broonie-DgEjT+Ai2ygdnm+yROfE0A, Andy Yan The spi on rv1108 is the same as other rockchip based socs, add compatible string for it. Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- Documentation/devicetree/bindings/spi/spi-rockchip.txt | 1 + drivers/spi/spi-rockchip.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt index 83da493..6e3ffac 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt @@ -6,6 +6,7 @@ and display controllers using the SPI communication interface. Required Properties: - compatible: should be one of the following. + "rockchip,rv1108-spi" for rv1108 SoCs. "rockchip,rk3036-spi" for rk3036 SoCS. "rockchip,rk3066-spi" for rk3066 SoCs. "rockchip,rk3188-spi" for rk3188 SoCs. diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 0b4a52b..6235b14 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -919,6 +919,7 @@ static const struct dev_pm_ops rockchip_spi_pm = { }; static const struct of_device_id rockchip_spi_dt_match[] = { + { .compatible = "rockchip,rv1108-spi", } { .compatible = "rockchip,rk3036-spi", }, { .compatible = "rockchip,rk3066-spi", }, { .compatible = "rockchip,rk3188-spi", }, -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
[parent not found: <1501496103-21713-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH 07/14] spi: rockchip: add compatible string for rv1108 spi [not found] ` <1501496103-21713-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2017-07-31 13:16 ` kbuild test robot 0 siblings, 0 replies; 26+ messages in thread From: kbuild test robot @ 2017-07-31 13:16 UTC (permalink / raw) Cc: kbuild-all-JC7UmRfGjtg, heiko-4mtYJXux2i+zQB+pC5nmwQ, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-spi-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, broonie-DgEjT+Ai2ygdnm+yROfE0A, Andy Yan [-- Attachment #1: Type: text/plain, Size: 2445 bytes --] Hi Andy, [auto build test ERROR on rockchip/for-next] [also build test ERROR on v4.13-rc3 next-20170731] [cannot apply to robh/for-next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Andy-Yan/Support-more-devices-on-rockchip-rv1108/20170731-200355 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next config: xtensa-allmodconfig (attached as .config) compiler: xtensa-linux-gcc (GCC) 4.9.0 reproduce: wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=xtensa All errors (new ones prefixed by >>): >> drivers/spi/spi-rockchip.c:923:2: error: expected '}' before '{' token { .compatible = "rockchip,rk3036-spi", }, ^ vim +923 drivers/spi/spi-rockchip.c 64e36824 addy ke 2014-07-01 920 64e36824 addy ke 2014-07-01 921 static const struct of_device_id rockchip_spi_dt_match[] = { b8251f6e Andy Yan 2017-07-31 922 { .compatible = "rockchip,rv1108-spi", } aa29ea3d Caesar Wang 2016-05-20 @923 { .compatible = "rockchip,rk3036-spi", }, 64e36824 addy ke 2014-07-01 924 { .compatible = "rockchip,rk3066-spi", }, b839b785 Addy Ke 2014-07-11 925 { .compatible = "rockchip,rk3188-spi", }, aa29ea3d Caesar Wang 2016-05-20 926 { .compatible = "rockchip,rk3228-spi", }, b839b785 Addy Ke 2014-07-11 927 { .compatible = "rockchip,rk3288-spi", }, aa29ea3d Caesar Wang 2016-05-20 928 { .compatible = "rockchip,rk3368-spi", }, 9b7a5622 Xu Jianqun 2016-02-18 929 { .compatible = "rockchip,rk3399-spi", }, 64e36824 addy ke 2014-07-01 930 { }, 64e36824 addy ke 2014-07-01 931 }; 64e36824 addy ke 2014-07-01 932 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 64e36824 addy ke 2014-07-01 933 :::::: The code at line 923 was first introduced by commit :::::: aa29ea3df27dbba19ef59023d0f7330f2fdc58ae spi/rockchip: add the rk3036/rk3228/rk3368 to match for driver :::::: TO: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org> :::::: CC: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 50916 bytes --] ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 08/14] ARM: dts: rockchip: add spi dt node for rv1108 [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (3 preceding siblings ...) 2017-07-31 10:15 ` [PATCH 07/14] spi: rockchip: add compatible string for rv1108 spi Andy Yan @ 2017-07-31 10:16 ` Andy Yan 2017-07-31 10:17 ` [PATCH 09/14] ARM: dts: rockchip: add pwm " Andy Yan ` (4 subsequent siblings) 9 siblings, 0 replies; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:16 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-spi-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Andy Yan Add SPI device tree node for rv1108 Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rv1108.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index a4d34d9..6ae83a8 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -200,6 +200,19 @@ status = "disabled"; }; + spi: spi@10270000 { + compatible = "rockchip,rv1108-spi"; + reg = <0x10270000 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&pdma 8>, <&pdma 9>; + #dma-cells = <2>; + status = "disabled"; + }; + grf: syscon@10300000 { compatible = "rockchip,rv1108-grf", "syscon"; reg = <0x10300000 0x1000>; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 09/14] ARM: dts: rockchip: add pwm dt node for rv1108 [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (4 preceding siblings ...) 2017-07-31 10:16 ` [PATCH 08/14] ARM: dts: rockchip: add spi dt node for rv1108 Andy Yan @ 2017-07-31 10:17 ` Andy Yan [not found] ` <1501496265-21910-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> 2017-07-31 10:18 ` [PATCH 10/14] ARM: dts: rockchip: add watchdog " Andy Yan ` (3 subsequent siblings) 9 siblings, 1 reply; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:17 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Andy Yan Add pwm device tree node for rv1108 Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rv1108.dtsi | 143 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 6ae83a8..7fcc6de 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -213,6 +213,54 @@ status = "disabled"; }; + pwm4: pwm@10280000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280000 0x10>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@10280010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280010 0x10>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@10280020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280020 0x10>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm6_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@10280030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x10280030 0x10>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + grf: syscon@10300000 { compatible = "rockchip,rv1108-grf", "syscon"; reg = <0x10300000 0x1000>; @@ -232,6 +280,53 @@ status = "disabled"; }; + pwm0: pwm@20040000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040000 0x10>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@20040010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040010 0x10>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@20040020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040020 0x10>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@20040030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0x20040030 0x10>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; pmugrf: syscon@20060000 { compatible = "rockchip,rv1108-pmugrf", "syscon"; reg = <0x20060000 0x1000>; @@ -453,6 +548,54 @@ }; }; + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm4 { + pwm4_pin: pwm4-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + pwm5 { + pwm5_pin: pwm5-pin { + rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm6 { + pwm6_pin: pwm6-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm7 { + pwm7_pin: pwm7-pin { + rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
[parent not found: <1501496265-21910-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]
* Re: [PATCH 09/14] ARM: dts: rockchip: add pwm dt node for rv1108 [not found] ` <1501496265-21910-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> @ 2017-07-31 11:28 ` Heiko Stübner 0 siblings, 0 replies; 26+ messages in thread From: Heiko Stübner @ 2017-07-31 11:28 UTC (permalink / raw) To: Andy Yan Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Andy, Am Montag, 31. Juli 2017, 18:17:45 CEST schrieb Andy Yan: > Add pwm device tree node for rv1108 > > Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > --- > > arch/arm/boot/dts/rv1108.dtsi | 143 > ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 143 > insertions(+) > > diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi > index 6ae83a8..7fcc6de 100644 > --- a/arch/arm/boot/dts/rv1108.dtsi > +++ b/arch/arm/boot/dts/rv1108.dtsi > @@ -213,6 +213,54 @@ > status = "disabled"; > }; > > + pwm4: pwm@10280000 { > + compatible = "rockchip,rk3288-pwm"; please make that a compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; and update the binding accordingly. Thanks Heiko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 10/14] ARM: dts: rockchip: add watchdog dt node for rv1108 [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (5 preceding siblings ...) 2017-07-31 10:17 ` [PATCH 09/14] ARM: dts: rockchip: add pwm " Andy Yan @ 2017-07-31 10:18 ` Andy Yan 2017-08-01 15:16 ` Heiko Stuebner 2017-07-31 10:19 ` [PATCH 12/14] ARM: dts: rockchip: add pwm backlight for rv1108 evb Andy Yan ` (2 subsequent siblings) 9 siblings, 1 reply; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:18 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Andy Yan Add watchdog device tree node for rv1108 Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rv1108.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 7fcc6de..1fc467e 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -266,6 +266,15 @@ reg = <0x10300000 0x1000>; }; + watchdog: wdt@10360000 { + compatible = "snps,dw-wdt"; + reg = <0x10360000 0x100>; + clocks = <&cru PCLK_WDT>; + clock-names = "pclk_wdt"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c0: i2c@20000000 { compatible = "rockchip,rv1108-i2c"; reg = <0x20000000 0x1000>; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH 10/14] ARM: dts: rockchip: add watchdog dt node for rv1108 2017-07-31 10:18 ` [PATCH 10/14] ARM: dts: rockchip: add watchdog " Andy Yan @ 2017-08-01 15:16 ` Heiko Stuebner 2017-08-01 18:55 ` Heiko Stuebner 0 siblings, 1 reply; 26+ messages in thread From: Heiko Stuebner @ 2017-08-01 15:16 UTC (permalink / raw) To: Andy Yan; +Cc: devicetree, linux-kernel, linux-rockchip Hi Andy, Am Montag, 31. Juli 2017, 18:18:30 CEST schrieb Andy Yan: > Add watchdog device tree node for rv1108 > > Signed-off-by: Andy Yan <andy.yan@rock-chips.com> I've adapted this patch to apply against the current rv1108.dtsi and applied it for 4.14. So resends of your series should take this change into account please :-) . See https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/log/?h=v4.14-armsoc/dts32 for reference Heiko ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 10/14] ARM: dts: rockchip: add watchdog dt node for rv1108 2017-08-01 15:16 ` Heiko Stuebner @ 2017-08-01 18:55 ` Heiko Stuebner 2017-08-02 0:34 ` Andy Yan 0 siblings, 1 reply; 26+ messages in thread From: Heiko Stuebner @ 2017-08-01 18:55 UTC (permalink / raw) To: Andy Yan Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Andy, Am Dienstag, 1. August 2017, 17:16:40 CEST schrieb Heiko Stuebner: > Am Montag, 31. Juli 2017, 18:18:30 CEST schrieb Andy Yan: > > Add watchdog device tree node for rv1108 > > > > Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> > > I've adapted this patch to apply against the current rv1108.dtsi > and applied it for 4.14. So resends of your series should take this > change into account please :-) . as the kbuild robot noticed that it doesn't build and I somehow missed that (heat and all), I've dropped the patch again. So we'll need to wait for your v2 of the series. Heiko -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH 10/14] ARM: dts: rockchip: add watchdog dt node for rv1108 2017-08-01 18:55 ` Heiko Stuebner @ 2017-08-02 0:34 ` Andy Yan 0 siblings, 0 replies; 26+ messages in thread From: Andy Yan @ 2017-08-02 0:34 UTC (permalink / raw) To: Heiko Stuebner Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hi Heiko: On 2017年08月02日 02:55, Heiko Stuebner wrote: > Hi Andy, > > Am Dienstag, 1. August 2017, 17:16:40 CEST schrieb Heiko Stuebner: >> Am Montag, 31. Juli 2017, 18:18:30 CEST schrieb Andy Yan: >>> Add watchdog device tree node for rv1108 >>> >>> Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> >> I've adapted this patch to apply against the current rv1108.dtsi >> and applied it for 4.14. So resends of your series should take this >> change into account please :-) . > as the kbuild robot noticed that it doesn't build and I somehow missed > that (heat and all), I've dropped the patch again. > > So we'll need to wait for your v2 of the series. All the dts series depend on the clk id parts. I will send the V2 today. > > Heiko > > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 12/14] ARM: dts: rockchip: add pwm backlight for rv1108 evb [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (6 preceding siblings ...) 2017-07-31 10:18 ` [PATCH 10/14] ARM: dts: rockchip: add watchdog " Andy Yan @ 2017-07-31 10:19 ` Andy Yan 2017-07-31 10:20 ` [PATCH 13/14] ARM: dts: rockchip: add pmic rk805 dt node " Andy Yan 2017-07-31 10:21 ` [PATCH 14/14] ARM: dts: rockchip: add accelerometer bma250e " Andy Yan 9 siblings, 0 replies; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:19 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Andy Yan RV1108 EVB uses pwm0 modulate the backlight, add dt node to enable it. Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rv1108-evb.dts | 43 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 58ee0fb..8a5a88f 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -54,6 +54,49 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + +&pwm0 { + status = "okay"; }; &sdmmc { -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 13/14] ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (7 preceding siblings ...) 2017-07-31 10:19 ` [PATCH 12/14] ARM: dts: rockchip: add pwm backlight for rv1108 evb Andy Yan @ 2017-07-31 10:20 ` Andy Yan 2017-07-31 10:21 ` [PATCH 14/14] ARM: dts: rockchip: add accelerometer bma250e " Andy Yan 9 siblings, 0 replies; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:20 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, zhangqing-TNX95d0MmH7DzftRWevZcw, Andy Yan RK805 is used as the voltage regulator on rv1108 evaluation board. Add device tree node for it. Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rv1108-evb.dts | 108 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 8a5a88f..5675975 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -93,6 +93,114 @@ 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + clock-frequency = <400000>; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_core: DCDC_REG1 { + regulator-name= "vdd_core"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <900000>; + }; + }; + + vdd_cam: DCDC_REG2 { + regulator-name= "vdd_cam"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2000000>; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name= "vcc_ddr"; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-state-enabled; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name= "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <3300000>; + }; + }; + + vdd_10: LDO_REG1 { + regulator-name= "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vcc_18: LDO_REG2 { + regulator-name= "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-state-disabled; + }; + }; + + vdd10_pmu: LDO_REG3 { + regulator-name= "vdd10_pmu"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-state-enabled; + regulator-state-uv = <1000000>; + }; + }; + }; + }; }; &pwm0 { -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH 14/14] ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb [not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> ` (8 preceding siblings ...) 2017-07-31 10:20 ` [PATCH 13/14] ARM: dts: rockchip: add pmic rk805 dt node " Andy Yan @ 2017-07-31 10:21 ` Andy Yan 9 siblings, 0 replies; 26+ messages in thread From: Andy Yan @ 2017-07-31 10:21 UTC (permalink / raw) To: heiko-4mtYJXux2i+zQB+pC5nmwQ Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Andy Yan Add dt node of bosch accelerometer bma250e on rv1108 evb. Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org> --- arch/arm/boot/dts/rv1108-evb.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index 5675975..60bb501 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -109,6 +109,13 @@ i2c-scl-falling-time-ns = <16>; clock-frequency = <400000>; + bma250: accelerometer@19 { + compatible = "bosch,bma250e"; + reg = <0x19>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB3 IRQ_TYPE_LEVEL_LOW>; + }; + rk805: pmic@18 { compatible = "rockchip,rk805"; reg = <0x18>; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
end of thread, other threads:[~2017-08-07 8:49 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-07-31 10:04 [PATCH 00/14] Support more devices on rockchip rv1108 Andy Yan
2017-07-31 10:08 ` [PATCH 02/14] clk: rockchip: support more clks for rv1108 Andy Yan
2017-07-31 23:31 ` Heiko Stuebner
2017-07-31 10:10 ` [PATCH 03/14] pinctrl: rockchip: add input schmitt support " Andy Yan
2017-07-31 11:26 ` Heiko Stübner
[not found] ` <1501495822-21503-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-08-07 8:49 ` Linus Walleij
2017-07-31 10:11 ` [PATCH 04/14] dt-bindings: i2c: rk3x: add " Andy Yan
2017-07-31 10:19 ` [PATCH 11/14] ARM: dts: rockchip: add saradc " Andy Yan
2017-07-31 23:11 ` Heiko Stuebner
[not found] ` <1501495449-21290-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-07-31 10:06 ` [PATCH 01/14] clk: rockchip: add more clk ids " Andy Yan
2017-07-31 23:27 ` Heiko Stuebner
2017-07-31 10:12 ` [PATCH 05/14] i2c: rk3x: add support " Andy Yan
[not found] ` <1501495963-21608-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-07-31 11:26 ` Heiko Stübner
2017-07-31 10:13 ` [PATCH 06/14] ARM: dts: rockchip: add i2c dt node " Andy Yan
2017-07-31 10:15 ` [PATCH 07/14] spi: rockchip: add compatible string for rv1108 spi Andy Yan
[not found] ` <1501496103-21713-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-07-31 13:16 ` kbuild test robot
2017-07-31 10:16 ` [PATCH 08/14] ARM: dts: rockchip: add spi dt node for rv1108 Andy Yan
2017-07-31 10:17 ` [PATCH 09/14] ARM: dts: rockchip: add pwm " Andy Yan
[not found] ` <1501496265-21910-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2017-07-31 11:28 ` Heiko Stübner
2017-07-31 10:18 ` [PATCH 10/14] ARM: dts: rockchip: add watchdog " Andy Yan
2017-08-01 15:16 ` Heiko Stuebner
2017-08-01 18:55 ` Heiko Stuebner
2017-08-02 0:34 ` Andy Yan
2017-07-31 10:19 ` [PATCH 12/14] ARM: dts: rockchip: add pwm backlight for rv1108 evb Andy Yan
2017-07-31 10:20 ` [PATCH 13/14] ARM: dts: rockchip: add pmic rk805 dt node " Andy Yan
2017-07-31 10:21 ` [PATCH 14/14] ARM: dts: rockchip: add accelerometer bma250e " Andy Yan
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