From mboxrd@z Thu Jan 1 00:00:00 1970 From: Timur Tabi Subject: Endianness of multi-bit 'gpios' property? Date: Tue, 7 Aug 2012 15:39:22 -0500 Message-ID: <50217CFA.7040708@freescale.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: devicetree-discuss-bounces+gldd-devicetree-discuss=m.gmane.org-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Sender: "devicetree-discuss" To: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org List-Id: devicetree@vger.kernel.org When a 'gpios' property defines multiple GPIO pins, is there any kind of expectation on the endian order of those pins? For example, take this: gpios = <&gpio0 0 0 &gpio0 1 0>; If I write a value of "2" to this GPIO pair, should I expect a value of 1 to be written to pin 0 and a value of 0 written to pin 1 (i.e. big-endian), or the other way around? I'm seeing some code that interprets the bits as big-endian, and some code that interprets it as little-endian. -- Timur Tabi Linux kernel developer at Freescale