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Thu, 3 Jul 2025 01:47:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E3.mail.protection.outlook.com (10.167.240.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.20 via Frontend Transport; Thu, 3 Jul 2025 01:47:49 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8B84844C3CB6; Thu, 3 Jul 2025 09:47:48 +0800 (CST) Message-ID: <50592fad-850c-4dab-92d8-a71cb89daf58@cixtech.com> Date: Thu, 3 Jul 2025 09:47:47 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 10/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings To: Krzysztof Kozlowski Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250630041601.399921-1-hans.zhang@cixtech.com> <20250630041601.399921-11-hans.zhang@cixtech.com> <20250630-graceful-horse-of-science-eecc53@krzk-bin> <5b182268-d64c-424c-9ada-0c3f120d2817@kernel.org> <2b608302-c4a6-404d-9cc5-d1ab9a6712bd@cixtech.com> Content-Language: en-US From: Hans Zhang In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jul 2025 01:47:49.0763 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87c819b7-9233-4a72-1f9d-08ddb9d39dc1 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E3.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYPPR06MB8036 On 2025/7/3 04:23, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL > > On 30/06/2025 17:30, Hans Zhang wrote: >> >> >> On 2025/6/30 19:14, Krzysztof Kozlowski wrote: >>> EXTERNAL EMAIL >>> >>> On 30/06/2025 10:29, Hans Zhang wrote: >>>>>> + >>>>>> + num-lanes: >>>>>> + maximum: 8 >>>>>> + >>>>>> + ranges: >>>>>> + maxItems: 3 >>>>>> + >>>>>> + msi-map: >>>>>> + maxItems: 1 >>>>>> + >>>>>> + vendor-id: >>>>>> + const: 0x1f6c >>>>> >>>>> Why? This is implied by compatible. >>>> >>>> Because when we designed the SOC RTL, it was not set to the vendor id >>>> and device id of our company. We are members of PCI-SIG. So we need to >>>> set the vendor id and device id in the Root Port driver. Otherwise, the >>>> output of lspci will be displayed incorrectly. >>> >>> Please read carefully. Previous discussions were also pointlessly >>> ping-ponging on irrelevant arguments. Did I suggest you do not have to >>> set it in root port driver? No. If this is const here, this is implied >>> by compatible and completely redundant, because your driver knows this >>> value already. It already has all the information to deduce this value >>> from the compatible. >>> >>> >> Dear Krzysztof, >> >> Thank you very much for your reply. >> >> These two attributes are also in the following document. Is this place >> out of date? >> Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > > I would need to spend time to investigate that and I choose to do other > things instead. I am recently very grumpy on arguments "I found this > somewhere else". I found bugs somewhere else, so am I okay to introduce > them? > Dear Krzysztof, Thank you very much for your reply. No, no, no. You misunderstood me. I didn't mean to say this because we don't study dt-binding doc every day. So we can only refer to the practices of other SOC manufacturers. If it's incorrect, we will definitely listen to your opinion. Here, I'm just explaining the origin of what I did. Anyway, I have solved this problem by following your method and using compatible. >> >> >> We initially used the logic of Cadence common driver as follows: >> drivers/pci/controller/cadence/pcie-cadence-host.c >> of_property_read_u32(np, "vendor-id", &rc->vendor_id); >> >> of_property_read_u32(np, "device-id", &rc->device_id); >> >> So, can the code in Cadence be deleted? > > Don't know. If this is ABI, then not. > According to my understanding, this is not ABI. Best regards, Hans > > Best regards, > Krzysztof